Intel Atom® x6200FE Series Processor Presets
The following table provides a brief description of each preset.
Preset Number | Description | Usage Notes |
|---|---|---|
1 | Dedicated cache for 1 real-time workload, no software SRAM, shared cache for best-effort workloads on CPU. | Enables 1 real-time workload.
For this preset, disable the Software SRAM Setting. |
2 | Dedicated cache for 1 real-time workload, 1 x L3 software SRAM (1 way),
shared cache for best-effort workloads on CPU. | Similar to Preset 1, but adds software SRAM in L3 cache.
A good starting point for developers looking to experiment with software SRAM. |
3 | Dedicated cache for 2 real-time workloads, 1 x L3 software SRAM (1 way), 1 x L2
software SRAM, shared cache for best-effort workloads on CPU. | Similar to Preset 2, but adds L2 software SRAM and supports 2 real-time workloads.
Useful for real-time workloads that have access latency requirements beyond what L3 cache can provide. |
Preset Configuration Details
The following tables show the configuration of each preset (assuming 12-way L2, 8-way L3).
Key:
Label | Name | Description |
|---|---|---|
S | Software SRAM | Cache ways dedicated for software SRAM buffer |
C[<number>] | CPU[COS ID] | Cache ways assigned to CPU use |
G | GPU | Cache ways assigned to GPU use |
Preset 1
This preset configures L3 cache only.
This preset allows non-real-time (best-effort) workloads running on the CPU to share cache ways 7:2. Cache ways 1:0 are dedicated for use by 1 real-time application.
Cache Level | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
L3 | C[0,2,3] | C[0,2,3] | C[0,2,3] | C[0,2,3] | C[0,2,3] | C[0,2,3] | C[1] | C[1] |
Preset 2
The only difference between Presets 1 and 2 is that cache way 7 is software SRAM.
Cache Level | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
L3 | S | C[0,2,3] | C[0,2,3] | C[0,2,3] | C[0,2,3] | C[0,2,3] | C[1] | C[1] |
Preset 3
This preset configures L2 cache and L3 cache.
In L3 cache, cache way 7 is software SRAM. Cache ways 6:4 are shared among best-effort workloads running on CPU. Cache ways 3:2 are reserved for the first real-time workload, and cache ways 1:0 are reserved for the second real-time workload.
In L2 cache, cache way 11 is software SRAM. The rest of the cache is for
best-effort workloads.
Cache Level | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
L3 | S | C[0,3] | C[0,3] | C[0,3] | C[2] | C[2] | C[1] | C[1] |
Cache Level | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
L2 | S | C | C | C | C | C | C | C | C | C | C | C |