Cache misses negatively affect the latency of real-time applications. With Intel® TCC Tools, you can reduce cache misses by allocating buffers that are less likely to be evicted from processor cache.
The system uses the
process to create low-latency buffers.
is a software construct that uses hardware capabilities to allocate a portion of the physical address space into the cache. The addresses are less likely to be evicted by the same or other processes.
Software SRAM is supported with the Yocto Project*-based BSP and RTCM. If you want to enable software SRAM in a different OS or hypervisor, contact your Intel representative for instructions.
Cache is a limited and precious resource, and is used by the OS/hypervisor, the real-time application, and other applications executing on the system. Reserving a certain amount of cache for real-time applications reduces the overall cache available for the rest of the system by that size. This may impact the performance of other applications and the OS/hypervisor executing on the system. Intel recommends to evaluate the impact of cache reservation to the whole system and adjust the configuration accordingly.
The Cache Configurator subregion in the boot firmware capsule must be signed to preserve the integrity of the subregion data. If the subregion data signers aren’t the subregion data producers, a trusted relationship between the signers and producers must be established to ensure that the subregion data doesn’t contain malware before signing in order to prevent any supply chain attacks.
environments during your experiments with performance, you can use test keys created during Intel® TCC Tools installation or generated by yourself. Keys are used by the Capsule Create Script