MRL (MMIO Read Latency) demonstrates the impact of tuning the core-from-PCIe (MMIO read) data stream.
MRL measures the expected roundtrip latency for a core to initiate a read request to the MMIO addressable region of a PCIe device and then receive a completion with the data requested. The PCIe device used for MRL measurement may be the integrated TSN Ethernet controller or a discrete network card,
such as an Intel® Ethernet Controller I225.
The workload parameters specified can be customized to closely mimic a specific customer use case in terms of performance requirements, computing resources, and targeted MMIO address space.
This section is for reference. It describes the flow of the MRL sample
MRL configures the board as follows:
echo 2 > /sys/devices/cpu/rdpmc
Connect to the Intel® Ethernet Controller I225:
Find the socket, bus, device, and function of the Intel® Ethernet
Ethernet controller: Intel Corporation Device 15f2
After the board is configured, the MRL workload starts running:
Default path to MRL:
This output example shows that MRL started successfully: