- From your host system, connect to the target system:ssh <user>@<target>
- If possible, maximize the terminal window to full size. The real-time readiness checker displays tables of settings that are best viewed in a wide window, though text will wrap and the screen will scroll accordingly.
- In the SSH session, run the real-time readiness checker:tcc_rt_checker | more
- If the tool detects a supported processor, it completes all checks and prints the results. Review the Result column for each checker. Possible results are as follows:
- RT_READY: The target system has the optimal configuration for real-time workloads.
- NOT_RT_READY: The target system does not have the optimal configuration.
usage: tcc_rt_checker [-h] [-l]
Optional. Show this help message and exit.
Optional. Details about NOT_RT_READY results.
- System Information
- Intel® TCC Tools Checkers
- Real-Time BIOS Capabilities Checkers
Checks for the presence of a real-time CPU model.
Prints the frequency of all CPU cores.
Prints the GPU model.
Prints the GPU frequency.
Checks for the presence of a validated BIOS version.
Software SRAM regions list
Cache Allocation Technology
Checks whether the CPU supports Cache Allocation Technology (CAT). The fundamental goal of Cache Allocation Technology is to enable resource allocation based on application priority or Class of Service (COS or CLOS). The processor exposes a set of Classes of Service into which applications (or individual threads) can be assigned. Cache allocation for the respective applications or threads is then restricted based on the class with which they are associated. By assigning different classes to real-time and non-real-time applications, cache access interference from non-real-time applications is eliminated. In addition, CAT is foundational for software SRAM functionality.
Cache Allocation Technology capabilities
Checks the CAT capabilities of the CPU.
Checks that the system is running in the virtualized environment.
Real-Time Configuration Driver checker
Intel® Hyper-Threading Technology
Verifies that Intel® Hyper-Threading Technology (Intel® HT Technology) is disabled or unsupported by the CPU. Hyper-Threading can cause latency as you can only swap threads on instruction boundaries, so a real-time thread can be stalled by a long instruction running on the other logical thread on that core.
Enhanced Intel SpeedStep® Technology
Checks whether Enhanced Intel SpeedStep® Technology (P-states) is disabled. P-states are the various execution power states of the processor. These are the frequency-voltage pairs that dictate the speed at which the processor will run. P-states transitions introduce latencies for real-time applications due to the time it takes to transition between frequencies.
#AC Split Lock
Checks whether Alignment Check is enabled. Split locks are atomic instructions (either explicitly via the LOCK prefix, or implicit, i.e., XCHG) whose operand is split across a cache line boundary. Split locks result in the lock transaction being split across two cache lines forcing a bus lock. The bus lock prevents any other cores or I/O devices from initiating any transactions for the duration of the atomic transaction’s read-modify-write flow. As the system must complete current transactions in flight before the bus lock can be acquired, the jitter introduced by a bus lock can be significant (10s of microseconds). The #AC on Split Lock feature prevents the system from taking a bus lock due to a split lock. This enforcement is achieved by hardware throwing the #AC exception whenever a split lock is encountered, resulting in the offending process being terminated.
Due to the presence of split locks in the bootloader (GRUB) included in the board support package (BSP), the BIOS does not include this feature in Intel® TCC Mode, and this checker is always considered RT_READY.
CPU PCI Express ASPM
Checks whether Active State Power Management (ASPM) is disabled. ASPM is an autonomous hardware-based, active state mechanism that enables power savings even when the connected components are in the D0 state. After a period of idle link time, an ASPM Physical-Layer protocol places the idle link into a lower power state. ASPM causes latency due to the delay for a device to wake from a low power state.
Intel® Speed Shift Technology
Checks whether Intel® Speed Shift Technology is disabled. Intel® Speed Shift Technology lets the hardware switch P-States, which causes latency due to the time it takes to transition between frequencies.
Low Power S0 Idle Capability
Checks whether Low Power S0 Idle is disabled. When disabled, prohibits S0ix states. S0ix states shut off parts of the SoC when they are not in use. S0ix causes latency due to the time it takes for a device to wake from a sleep state. If carefully managed, sleep states can be used in concert with real-time if one ensures that the device will not enter a sleep state during the real-time critical operation.