User and Reference Guide

  • 2021.1
  • 12/04/2020
  • Public Content

Watchdog Timers

Watchdog Timers can be implemented in the platform, the firmware/OS, or some combination of the two.
  • Platform Watchdog Timers are implemented by a non-CPU device that can reset the platform if a heartbeat condition is not seen. If the heartbeat is implemented in software then halting the target via JTAG can result in spontaneous resets, either while the target is halted, or immediately after resuming execution.
  • Firmware/OS Watchdog Timers are implemented entirely in software but may rely on hardware resources such as the Time Stamp Counter to detect hangs on a CPU. If the debugger does not control the simultaneous run/stop of all threads properly then the OS may detect this as an error condition.

Product and Performance Information


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