• 04/03/2020
  • Intel Confidential

Color Copy Pipeline – The “Scan Pre-Process” OpenVX* Graph

Figure 1 presents a high-level diagram for the “Scan Pre-Process” OpenVX* graph implemented in the sample:
Figure 1: Top-level structure of “Scan Pre-Process” OpenVX* graph implemented in the sample
The input to the “Scan Pre-Process” OpenVX graph is packed 10-bit or 12-bit uncalibrated and skewed RGB images. Since the input image provided by the user (using command line option
--input
or
–i
) is an
8bpp
RGB image, the uncalibrated and skewed 10-bit or 12-bit images, which are used as input to the graph, are synthetically generated using the following process:
  1. The input image, which you provide, is skewed using the angle specified by
    --sppskew <degrees>
    . For example,
    --sppskew 3.0
    will rotate the original image counter-clockwise by 3 degrees to generate a skewed image, as illustrated below. The rotation operation is done using OpenVX WarpAffine node with BiCubic interpolation.
    Figure 2: Illustration of applying skew to the input image
  2. The skewed image created in step 1 above is converted to a packed 10-bit or 12-bit image. If you specify
    --sppbits 10
    , a packed 10-bit image is created. If you specify
    --sppbits 12
    , a packed 12-bit image is created. The packing scheme used for 10-bit and 12-bit is specified in the Figures 3 and 4 below.
    Figure 3: Illustration of packing scheme used to pack 10 bit/pixel images into the bytestream. Every 4 sequential 10-bit pixels are packed into 5 sequential bytes. The first 4 bytes hold the lower 8 bits of each of the 10-bit pixels. The last byte holds the upper 2 bits of each of the 10-bit pixels.
    Figure 4: Illustration of packing scheme used to pack 12 bit/pixel images into the bytestream. Every 2 sequential 12-bit pixels are packed into 3 sequential bytes. The first byte holds the lower 8 bits of the first 12-bit pixel. The upper 4 bits of the second byte hold the lower 4 bits of the second 12-bit pixel. The lower 4 bits of the second byte hold the upper 4 bits of the first 12-bit pixel. The third byte holds the upper 8 bits of the second 12-bit pixel.
 
During the conversion, a random gain and offset arrays are generated for the correction process. The sizes of the gain and offset arrays are equal to the width of the skewed image. When the “Scan Pre-Process” graph is executed, the Gain / Offset advanced tiling node will first unpack the 10-bit or 12-bit packed input data to a floating point temporary result, and apply the following formula to produce the 8-bit “calibrated” result:
output_8[x] = (input[x] * gain[x] + offset[x]) * agc
where:
  • input[x]
    is an unpacked pixel at position X for the current line
  • gain[x]
    is the corresponding gain value for positiob X
  • offset[x]
    id the corresponding offset value for position X
  • agc
    (Automatic Gain Correction) is a page constant value
In order to have the Gain / Offset node generate (close to) the original image, the inverse of the above formula is applied to the image during the 8-bit to 10-bit / 12-bit package image conversion process. The formula applies a random gain and offset to column of the image for each R, G, and B plane, synthetically producing an “uncalibrated” image that looks as follows:
Figure 5: Synthetically generated “uncalibrated” and skewed 10-bit / 12-bit image to be used as input to “Scan Pre-Process” graph
This synthetically generated “uncalibrated” and skewed 10-bit/12-bit image is used as an input to the “Scan Pre-Process” graph. The Scan Pre-Process Graph, shown in Figure 1 above, reverses the steps taken to produce the “uncalibrated” input image:
  1. The “uncalibrated” and skewed 10-bit / 12-bit packed input R, G, and B planes are passed as input to the Gain / Offset node(s), producing a calibrated (but still skewed) RGB image.
  2. The skewed image is passed to the OpenVX Warp Affine node to correct the given skew using BiCubic interpolation.
    Figure 6: “Scan Pre-Process” flow from input uncalibrated / skewed image, to calibrated / skew corrected output image

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.