Typically, the FPGA board has its own private
memory on which it primarily operates. The CPU must bulk transfer or
dynamic memory access
(DMA) all data that the kernel needs to access into the FPGA’s local DDR memory. After the kernel completes its operations, results must be transferred over DMA back to the CPU. The transfer speed is bound by the PCIe link itself, as well as the efficiency of the DMA solution. For example, the Intel® PAC with Intel® Arria® 10 GX FPGA has a PCIe Gen 3 x 8 link, and transfers are typically limited to 6-7 GB/s.