FPGA Optimization Guide for Intel® oneAPI Toolkits

Developer Guide

Contents

Latency Controls (Beta)

The following table summarizes the latency controls:
Latency Controls
Argument
Description
Example
sycl::ext::intel::experimental::latency_anchor_id<
N
>
Specifies the ID of the current side-effect operation where it behaves as an anchor. 
// This pipe read() performs as anchor 0 in latency control.
Pipe::read<ext::intel::experimental::latency_anchor_id<0>>();
sycl::ext::intel::experimental::latency_constraint<
A, B, C
>
Specifies the latency constraint when the current side-effect operation behaves as a non-anchor. 
// Set a latency constraint between anchor 0 and this pipe write().
// This pipe write() starts exactly 2 cycles after anchor 0 is done.
Pipe::write<ext::intel::experimental::latency_constraint<0, ext::intel::experimental::type::exact, 2>>(...);
For detailed information about the variables, refer to Latency Controls (Beta).

Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.