FPGA Optimization Guide for Intel® oneAPI Toolkits

Developer Guide

Contents

Handshaking Between Clusters

By default, the handshaking protocol between clusters is a simple stall/valid protocol. Data from the upstream cluster is consumed when the
stall
 signal is low, and the
valid
 signal is high.
Handshaking Between Clusters
Handshaking Between Clusters

Hyper Optimized Handshaking

If the distance across the FPGA between these two clusters is large, handshaking may become the critical path that affects peak f
MAX
 in the design. To improve these cases, the
Intel® oneAPI
DPC++/C++
 Compiler
 can add pipelining registers to the stall/valid protocol to ease the critical path and improve f
MAX
. This enhanced handshaking protocol is called
hyper-optimized handshaking
.
Hyper-Optimized Handshaking Data Flow
The following timing diagram illustrates an example of upstream cluster 1 and downstream cluster 2 with two pipelining registers inserted in-between:
Hyper-Optimized Handshaking
Hyper Optimized Handshaking
Hyper-optimized handshaking is currently available only for the Intel® Agilex™ and Intel® Stratix® 10 device families.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.