FPGA Optimization Guide for Intel® oneAPI Toolkits

Developer Guide

Contents

Global Control of Exit FIFO Latency of Stall-free Clusters (
-Xssfc-exit-fifo-type=
<value>
)

Use the
-Xssfc-exit-fifo-type=
<value>
 flag in the
icpx
 command to direct the
Intel® oneAPI
DPC++/C++
 Compiler
 to globally compile all stall-free clusters in kernels with a specified exit FIFO type. This flag supports the following arguments:
  • default
    : Infers the mid-speed FIFO (implemented with MLABs or M20Ks) for a minimum latency of three cycles.
  • zero-latency
    : Combinational path around the default FIFO for a minimum latency of zero cycles.
  • low-latency
    : Registered path around the default FIFO for a minimum latency of one cycle.
Depending on the specified exit FIFO type and resulting hardware implementation, f
MAX
 or FPGA area use might be affected negatively.
Example
icpx -fsycl -fintelfpga -Xshardware -Xssfc-exit-fifo-type=zero-latency <source_file>.cpp
Clustering the Datapath

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.