Developer Guide


Timing Failures

If your FPGA compile fails to meet timing requirements, the
Intel® oneAPI
deletes the generated FPGA image, prints an error message, and returns an error code. This means that the generated FPGA image did not meet all timing constraints. The best solution is usually to recompile with a different seed (see
in the
Intel® oneAPI Programming Guide
). However, some rare designs where the FPGA is extremely full might require sweeping several seeds to find one that passes the timing checks. If your design has chronic timing failures and you cannot resolve with seed sweeps, consult your BSP vendor.
When a timing failure happens, the compiler generates a
file. The path to this file and file name are dependent on your BSP. This
file lists which clocks in your design had failing paths and the magnitude of failures.

Product and Performance Information


Performance varies by use, configuration and other factors. Learn more at