If your FPGA compile fails to meet timing requirements, the
prints an error message and returns an error code. This means that the generated FPGA image does not meet all timing constraints. The best solution is usually to recompile with a different seed (see
Intel® oneAPI Programming Guide
). However, some rare designs where the FPGA is extremely full might require sweeping several seeds to find one that passes the timing checks. If your design has chronic timing failures and you cannot resolve with seed sweeps, consult your BSP vendor.