Developer Guide

Contents

Timing Failures

If your FPGA compile fails to meet timing requirements, the
Intel® oneAPI
DPC++/C++
Compiler
prints an error message and returns an error code. This means that the generated FPGA image does not meet all timing constraints. The best solution is usually to recompile with a different seed (see
-Xsseed=
<value>
in the
Intel® oneAPI Programming Guide
). However, some rare designs where the FPGA is extremely full might require sweeping several seeds to find one that passes the timing checks. If your design has chronic timing failures and you cannot resolve with seed sweeps, consult your BSP vendor.
When a timing failure happens, the compiler generates a
*.failing_clocks.rpt
file. The path to this file and file name are dependent on your BSP. This
.rpt
file lists which clocks in your design had failing paths and the magnitude of failures.
If the magnitude of the failures is very small (a few ps up to a few tens of ps), your image might be safe to use for limited testing. However, remember that
ANY
timing failure means the resultant FPGA image is not guaranteed to work and could result in unpredictable failures. You must use an image with timing failures only for limited internal testing under lab conditions and never deployed to the field.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.