Developer Guide



The Intel® FPGA Dynamic Profiler for DPC++ has some limitations:
  • Profile data is not persistent across SYCL* programs or multiple devices.
  • The Profiler is unique to each SYCL program and device, meaning, each program on each device has its own profiler information. If your host swaps a new kernel program in and out of the FPGA, the Profiler does not save any data.
  • Profile data is not saved on a device for later profiling.
  • All profiling data is read to the host during execution and is only stored on the device long enough to be read on the next readback. Any reprogramming of new designs or restarting the same design results in new profiling data, erasing any previous data that may have existed.
  • Instrumenting the design with performance counters increases hardware resource utilization (that is, FPGA area use) and typically decreases performance.

Product and Performance Information


Performance varies by use, configuration and other factors. Learn more at