Access HLD FPGA Reports in JSON Format
In addition to the
report.html
file, SYCL* also provides the HLD FPGA report data in JSON files.
The JSON files containing the HLD FPGA report data are available in the
<project_dir>/reports/resources/json
directory. The directory provides the following .json
files:
File
| Description
|
|---|---|
area.json | Area Estimates
|
block.json | Block view of the System Viewer
|
bottleneck.json | Bottleneck view of the Loop Analysis report
|
gmv.json | Global memory view of the System Viewer
|
info.json | Summary of project name, compilation command, versions, and timestamps
|
loops.json | Navigation tree of the Loop Analysis report
|
loops_attr.json | Loop Analysis
|
mav.json | System view of the System Viewer
|
new_lmv.json | Kernel Memory Viewer
|
pipeline.json | Cluster view of the System Viewer
|
quartus.json | Intel® Quartus® Prime compilation summary
|
schedule.json | Schedule Viewer
|
summary.json | Kernel compilation name mapping
|
tree.json | Navigation tree of the System Viewer
|
warnings.json
| Compilation warning messages
|