Development Reference Guides

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Logical Operators

The logical operators use the symbols and intrinsics listed in the following table.
Bitwise Operation
Standard Operator Symbols
Operator Symbols with Assign
Standard Syntax Usage
Syntax Usage with Assign
Corresponding Intrinsic
AND
&
&=
R = A & B
R &= A
_mm_and_si64
_mm_and_si128
OR
|
|=
R = A | B
R |= A
_mm_and_si64
_mm_and_si128
XOR
^
^=
R = A^B
R ^= A
_mm_and_si64
_mm_and_si128
ANDNOT
andnot
N/A
R = A andnot B
N/A
_mm_and_si64
_mm_and_si128
Examples and Miscellaneous Exceptions
  • A and B converted to M64. Result assigned to
    Iu8vec8
    :
    I64vec1 A; Is8vec8 B; Iu8vec8 C; C = A & B;
  • Same size and signedness operators return the nearest common ancestor:
    I32vec2 R = Is32vec2 A ^ Iu32vec2 B;
  • A&B returns M64, which is cast to
    Iu8vec8
    :
    C = Iu8vec8(A&B)+ C;
  • When
    A
    and
    B
    are of the same class, they return the same type. When
    A
    and
    B
    are of different classes, the return value is the return type of the nearest common ancestor.
Ivec Logical Operator Overloading
The logical operator returns values for combinations of classes, listed in the following table, apply when
A
and
B
are of different classes.
Return Value
AND
OR
XOR
NAND
Operand A
Operand B
I64vec1 R
&
|
^
andnot
I[s|u]64vec2 A
I[s|u]64vec2 B
I64vec2 R
&
|
^
andnot
I[s|u]64vec2 A
I[s|u]64vec2 B
I32vec2 R
&
|
^
andnot
I[s|u]32vec2 A
I[s|u]32vec2 B
I32vec4 R
&
|
^
andnot
I[s|u]32vec4 A
I[s|u]32vec4 B
I16vec4 R
&
|
^
andnot
I[s|u]16vec4 A
I[s|u]16vec4 B
I16vec8 R
&
|
^
andnot
I[s|u]16vec8 A
I[s|u]16vec8 B
I8vec8 R
&
|
^
andnot
I[s|u]8vec8 A
I[s|u]8vec8 B
I8vec16 R
&
|
^
andnot
I[s|u]8vec16 A
I[s|u]8vec16 B
Ivec Logical Operator Overloading with Assignment
For logical operators with assignment, the return value of
R
is always the same data type as the pre-declared value of R as listed in the following table:
Return Type
Left Side
AND
OR
XOR
Right Side (Any Ivec Type)
I128vec1
I128vec1 R
&=
|=
^=
I[s|u][N]vec[N] A;
I64vec1
I64vec1 R
&=
|=
^=
I[s|u][N]vec[N] A;
I64vec2
I64vec2 R
&=
|=
^=
I[s|u][N]vec[N] A;
I[x]32vec4
I[x]32vec4 R
&=
|=
^=
I[s|u][N]vec[N] A;
I[x]32vec2
I[x]32vec2 R
&=
|=
^=
I[s|u][N]vec[N] A;
I[x]16vec8
I[x]16vec8 R
&=
|=
^=
I[s|u][N]vec[N] A;
I[x]16vec4
I[x]16vec4 R
&=
|=
^=
I[s|u][N]vec[N] A;
I[x]8vec16
I[x]8vec16 R
&=
|=
^=
I[s|u][N]vec[N] A;
I[x]8vec8
I[x]8vec8 R
&=
|=
^=
I[s|u][N]vec[N] A;

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.