Stratix 10 - Serial Flash Mailbox Client Intel FPGA IP Core Design Example

715080
11/27/2018

Introduction

This reference design implements the Stratix 10 Serial Flash Mailbox Client Intel FPGA IP Core to perform general-purpose memory operations such as read flash device ID, perform sector erase on flash devices, read and write data from and to flash devices. Other than that, it also shows the flow to write Raw Programming Data (.rpd) files into flash devices using Stratix 10 Serial Flash Mailbox Client Intel FPGA IP Core.
IP Cores (27)
IP Core IP Core Category
Top level generated instrumentation fabric Debug & Performance
Reset Controller QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Altera SDM Mbox Bridge Configuration and Programming
Altera FPGA2SDM Bridge Configuration and Programming
Altera SDM2FPGA Bridge Configuration and Programming
Altera SDM GPI Configuration and Programming
Altera SDM IRQ Configuration and Programming
Altera SDM GPO Configuration and Programming
altera_jtag_avalon_master QsysInterconnect
Avalon-ST Bytes to Packets Converter QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Avalon Packets to Transaction Converter QsysInterconnect
MM Interconnect QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Memory-Mapped Router QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
altera_config_stream_endpoint Debug & Performance

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 18.0.0 Pro


Tags Details

Family

Intel® Stratix® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.0

Other Tags

Intel® FPGAs

FPGA Design Store