Stratix 10 - IOPLL Advanced Mode Reconfiguration

715064
12/26/2018

Introduction

In Advanced Mode, individual I/O PLL setting is reconfigured using the IOPLL Reconfig IP core through the Avalon interface. This reference design demonstrates the implementation of the Advanced Mode I/O PLL reconfiguration.
IP Cores (5)
IP Core IP Core Category
Top level generated instrumentation fabric Debug & Performance
Altera SignalTap II Agent Debug and Performance
Altera IOPLL ClocksPLLsResets
Altera IOPLL Reconfig PLL
Altera In-System Sources & Probes SimulationDebugVerification

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* Vendor: Third party from Intel Public Cloud

* ACDS Version: 18.1.0 Pro


Design Details

Device Family

Intel® Stratix® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.1