MAX 10 - SDRAM Nios Test - MAX10 DE10 Lite

715010
1/27/2017

Introduction

This demonstration illustrates how to perform memory access in Qsys. It also shows how Altera's SDRAM controller IP accesses SDRAM and how the Nios II processor reads and writes the SDRAM for hardware verification. The SDRAM controller handles complex aspects of accessing SDRAM such as initializing the memory device, managing SDRAM banks, and keeping the devices refreshed at certain interval.
IP Cores (25)
IP Core IP Core Category
Avalon ALTPLL ClocksPLLsResets
IRQ Mapper QsysInterconnect
JTAG UART ConfigurationProgramming
PIO (Parallel I/O) Other
MM Interconnect QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Avalon-ST Adapter QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Memory-Mapped Router QsysInterconnect
Memory-Mapped Burst Adapter QsysInterconnect
Memory-Mapped Width Adapter QsysInterconnect
Nios II Gen2 Processor NiosII
On-Chip Memory (RAM or ROM) OnChipMemory
Reset Controller QsysInterconnect
SDRAM Controller ExternalMemoryInterfaces
System ID Peripheral Other
Interval Timer Peripherals

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 16.0.0 Standard


Development Kit

MAX® 10 DE10 - Lite

Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

16.0

Other Tags

MAX® 10 DE10 - Lite