Intel® Stratix® 10 FPGA – PCI Express* 3.0 x16 Avalon®-MM DMA with On-Chip Memory Reference Design

Intel® Stratix® 10 FPGA – PCI Express* 3.0 x16 Avalon®-MM DMA with On-Chip Memory Reference Design

714933
12/6/2018

Introduction

This design demonstrates direct memory access (DMA) throughputs with the PCIe* 3.0 x16 Avalon® memory-mapped (Avalon-MM) interface with internal memory.

Design Details

Device Family

Intel® Stratix® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.1

IP Cores (16)
IP Core IP Core Category
Top level generated instrumentation fabric Debug & Performance
Altera IOPLL ClocksPLLsResets
On-Chip Memory (RAM or ROM) OnChipMemory
MM Interconnect QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Memory-Mapped Router QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Avalon-ST Pipeline Stage QsysInterconnect
Memory-Mapped Burst Adapter QsysInterconnect
Reset Controller QsysInterconnect

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>


Design Details

Device Family

Intel® Stratix® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.1