Intel® MAX® 10 FPGA – Nios® II Processor Simple Socket Server Ethernet Design Example for Arrow's DECA Board

Intel® MAX® 10 FPGA – Nios® II Processor Simple Socket Server Ethernet Design Example for Arrow's DECA Board

714921
1/26/2020

Introduction

This design example demonstrates the communication with a telnet client on a development host PC. The telnet client offers a convenient way of issuing commands over a TCP/IP socket to the Ethernet-connected NicheStack TCP/IP running on Arrow's DECA kit with a simple TCP/IP socket server example. The socket server example receives commands sent over a TCP/IP connection and turns LEDs on and off according to the commands. Note that this design uses DDR3 memory and boots uC/OS.

Development Kit

Development Kit

Design Details

Device Family

Intel® MAX® 10 FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

18.1
Other Tags

Arrow* MAX® 10 DECA
IP Cores (0)

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* Vendor: Third party from Arrow

* ACDS Version: 18.1.0 Standard


Development Kit

Development Kit

Design Details

Device Family

Intel® MAX® 10 FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

18.1
Other Tags

Arrow* MAX® 10 DECA