MAX 10 - Nios II Design Example Using Bluetooth and Wifi



In this design example, you will interact with the DECA platform from your Android or iOS smartphone over both Bluetooth and Wi-Fi using the BeagleBone-compatible Wi-Fi cape from Dallas Logic. Note that this is a design extracted from Arrow's DECA workshop series of labs. This is the final solution only. If you would like to work through the lab and learn more about it, visit:
IP Cores (34)
IP Core IP Core Category
Avalon ALTPLL ClocksPLLsResets
Altera Modular ADC core ADC
Altera Modular ADC Control core ADC
Altera Modular ADC Sample Storage core ADC
Altera Modular ADC Sequencer core ADC
PIO (Parallel I/O) Other
SPI (3 Wire Serial) SPI
UART (RS-232 Serial Port) Other
IRQ Mapper QsysInterconnect
JTAG UART ConfigurationProgramming
DDR3 SDRAM Controller with UniPHY ExternalMemoryInterfaces
Altera DDR3 Nextgen Memory Controller ExternalMemoryInterfaces
Altera Nextgen Memory Controller MM-ST Adapter ExternalMemoryInterfaces
Altera DDR3 Nextgen Memory Controller Core ExternalMemoryInterfaces
Altera DDR3 AFI Multiplexer ExternalMemoryInterfaces
DDR3 SDRAM External Memory PHY ExternalMemoryInterfaces
DDR3 SDRAM External Memory PLL/DLL/OCT block ExternalMemoryInterfaces
DDR3 SDRAM Qsys Sequencer ExternalMemoryInterfaces
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
MM Interconnect QsysInterconnect
Avalon-ST Adapter QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Memory-Mapped Router QsysInterconnect
Nios II Gen2 Processor NiosII
Reset Controller QsysInterconnect
System ID Peripheral Other

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

Prepare the design template in the Quartus Prime software command-line

At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par

Once the process completes, then type:

quartus_sh --platform -name <project>


* Vendor: Third party from Arrow

* ACDS Version: 16.0.0 Standard

Development Kit

Development Kit

Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version


Other Tags

Arrow* MAX® 10 DECA