MAX 10 - MIPI CSI2 RX/TX with passive D-PHY

714841
10/3/2016

Introduction

A user guide document for this reference design is included in the associated Quartus project archive: MIPI_to_HDMI_Demo_Users_Guide*.
IP Cores (43)
IP Core IP Core Category
Altera Soft LVDS Other
FIFO OnChipMemory
Avalon ALTPLL ClocksPLLsResets
Altera GPIO Lite Other
Test Pattern Generator II (4K Ready) Other
Frame Buffer II (4K Ready) AudioVideo
Video Input Bridge AudioVideo
Clocked Video Output AudioVideo
PIO (Parallel I/O) Other
IRQ Mapper QsysInterconnect
JTAG UART ConfigurationProgramming
altera_jtag_avalon_master QsysInterconnect
Avalon-ST Bytes to Packets Converter QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Reset Controller QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Avalon Packets to Transaction Converter QsysInterconnect
LPDDR2 SDRAM Controller with UniPHY ExternalMemoryInterfaces
Altera LPDDR2 Nextgen Memory Controller ExternalMemoryInterfaces
Altera Nextgen Memory Controller MM-ST Adapter ExternalMemoryInterfaces
Altera LPDDR2 Nextgen Memory Controller Core ExternalMemoryInterfaces
Altera LPDDR2 AFI Multiplexer ExternalMemoryInterfaces
LPDDR2 SDRAM External Memory PHY ExternalMemoryInterfaces
LPDDR2 SDRAM External Memory PLL/DLL/OCT block ExternalMemoryInterfaces
LPDDR2 SDRAM Qsys Sequencer ExternalMemoryInterfaces
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Avalon-MM Pipeline Bridge QsysInterconnect
MM Interconnect QsysInterconnect
Avalon-ST Adapter QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Memory-Mapped Router QsysInterconnect
Memory-Mapped Burst Adapter QsysInterconnect
Nios II Gen2 Processor NiosII
Nios II Gen2 Processor Unit NiosII
On-Chip Memory (RAM or ROM) OnChipMemory

Detailed Description

pdf

If interested in purchasing or evaluating this IP core, please send an email request to ip@foresys.com to request a license for either the MIPI CSI-2 TX Core or MIPI CSI-2 RX Core. This design cannot be synthesized without an evaluation or production license from Foresys.

This reference design provides an example of video processing of a camera sensor via the MIPI CSI-2 RX and TX interfaces using an external passive D-PHY resistor network.

RX path includes:
- External Camera Sensor [Leopard Imaging LI-CAM-OV10640-MIPI OVT10640 (4D+C)] transmits video stream across MIPI CSI-2 RX interface.
- The Foresys MIPI-RX Core performs the MIPI CSI-2 layer processing and forwards the video stream as Avalon Streaming Video.
- Altera VIP components (process video data)
- The RX Video stream is forwarded to an external monitor via the HDMI connector on the board.

TX path includes:
- The Foresys MIPI-TX Core encodes the Avalon Streaming video stream as MIPI CSI-2 layer formatting and forwards the stream out the MIPI CSI-2 TX connector.
- An external Leopard Imaging [LI-USB30-MIPI-TESTER (CSI2 to USB3 Bridge)] converts the stream to USB3 format.
- The USB3 cable forwards the stream to an external host computer.



Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* Vendor: Third party from Foresys

* ACDS Version: 18.1.0 Standard


Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

18.1