Arria 10 - Intel FPGA Remote System Update via PCI Express*

714766
1/21/2021

Introduction

This reference design demonstrates remote system update functionality on Arria 10 FPGA Development Kit using PCI Express as the communication protocol. The configuration image from the host system is received via PCI Express in the Intel Arria 10 device and then written into the serial flash by Modular Scatter-Gather DMA. The reconfiguration process of remote update is controlled by the dedicated remote system upgrade circuitry in the Intel Arria 10 device and manage via PCI Express.
IP Cores (28)
IP Core IP Core Category
Reset Controller QsysInterconnect
MM Interconnect QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Memory-Mapped Width Adapter QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Avalon-ST Pipeline Stage QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Memory-Mapped Router QsysInterconnect
Memory-Mapped Burst Adapter QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Arria 10 Hard IP for PCI Express PCIExpress
Arria 10 Transceiver Native PHY TransceiverPHY
Arria 10 FPLL ClocksPLLsResets
Arria 10 Transceiver ATX PLL TransceiverPLL
IRQ Mapper QsysInterconnect
Altera Remote Update ConfigurationProgramming
Altera Remote Update Core ConfigurationProgramming
Avalon Remote Update Controller Configuration and Programming
Altera IOPLL ClocksPLLsResets
Modular Scatter-Gather DMA BridgesAndAdaptors
Read Master QsysInterconnect
Write Master QsysInterconnect
Modular SGDMA Dispatcher BridgesAndAdaptors

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 20.4.0 Pro


Tags Details

Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

20.4

Other Tags

Intel® FPGAs

FPGA Design Store