Arria 10 - DisplayPort UHD Scaler and Mixer Design Example

714642
3/6/2017

Introduction

The design runs on Arria 10 GX FPGA Development Kit. The Bitec FMC daughter card is used to receive video data from the Graphic Processor Unit (GPU) on the PC graphic card and transmit video data to a monitor. This reference design receives video data (either 1080p or 2160p resolution) over the DP RX link. The received video is converted to the Avalon-ST video stream, up or down scaling the video stream and stored into the external memory. The buffered image is then mixed with a 3840 x 2160 color bar background and OSD icon and is sent to the DP source. The combined image is transmitted to a DP capable monitor over DP TX link.
IP Cores (52)
IP Core IP Core Category
Avalon FIFO Memory OnChipMemory
Nios II Gen2 Processor NiosII
Nios II Gen2 Processor Unit NiosII
DisplayPort AudioVideo
IRQ Mapper QsysInterconnect
IRQ Clock Crosser QsysInterconnect
JTAG UART ConfigurationProgramming
altera_jtag_avalon_master QsysInterconnect
Avalon-ST Bytes to Packets Converter QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Reset Controller QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Avalon Packets to Transaction Converter QsysInterconnect
MM Interconnect QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Avalon-ST Adapter QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Memory-Mapped Router QsysInterconnect
PIO (Parallel I/O) Other
On-Chip Memory (RAM or ROM) OnChipMemory
Interval Timer Peripherals
System ID Peripheral Other
Avalon-ST Data Format Adapter QsysInterconnect
Avalon-ST Video stream cleaner QsysInterconnect
Video Input Bridge AudioVideo
Clipper II (4K Ready) AudioVideo
Clocked Video Input II (4K Ready) AudioVideo
Clocked Video Output II (4K Ready) AudioVideo
Arria 10 External Memory Interfaces ExternalMemoryInterfaces
EMIF Core Component for 20nm Families ExternalMemoryInterfaces
Avalon-MM Pipeline Bridge QsysInterconnect
Mixer II (4K Ready) AudioVideo
Scaler II AudioVideo
Scaler Algorithmic Core AudioVideo
Frame Buffer II (4K Ready) AudioVideo
Arria 10 Transceiver Native PHY TransceiverPHY
Transceiver PHY Reset Controller TransceiverPHY
Arria 10 FPLL ClocksPLLsResets
Altera GPIO Other
Altera GPIO Core Other
Altera IOPLL ClocksPLLsResets
Altera Arria 10 XCVR Reset Sequencer Other

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 16.1.0 Standard


Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

16.1