MAX 10 - DDR3 with Board Test System Console

714608
4/28/2016

Introduction

The MAX 10 FPGA development kit has one 64-Mx16 1Gb DDR3 SDRAM and one 128-Mx8 1Gb DDR3 SDRAM. The MAX 10 FPGA provides full-speed support to a DDR3 300-MHz interface with error correction code (ECC) feature. This design example is used to check out a x24 DDR3 300MHz interface, please download the installer of MAX 10 development kit and use BTS GUI to try it out for a straightforward experience. Note that this design uses DDR3 memory and the pinout on the devkit changes based on the revision of your kit. See the MAX 10 dev kit baseline pinout design for a TCL script with the pinout changes between the different revisions of the development kits.
IP Cores (40)
IP Core IP Core Category
IRQ Mapper QsysInterconnect
IRQ Clock Crosser QsysInterconnect
altera_jtag_avalon_master QsysInterconnect
Avalon-ST Bytes to Packets Converter QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Reset Controller QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Avalon Packets to Transaction Converter QsysInterconnect
DDR3 SDRAM Controller with UniPHY ExternalMemoryInterfaces
Altera DDR3 Nextgen Memory Controller ExternalMemoryInterfaces
Altera Nextgen Memory Controller MM-ST Adapter ExternalMemoryInterfaces
Altera DDR3 Nextgen Memory Controller Core ExternalMemoryInterfaces
Altera DDR3 AFI Multiplexer ExternalMemoryInterfaces
DDR3 SDRAM External Memory PHY ExternalMemoryInterfaces
DDR3 SDRAM External Memory PLL/DLL/OCT block ExternalMemoryInterfaces
DDR3 SDRAM Qsys Sequencer ExternalMemoryInterfaces
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
MM Interconnect QsysInterconnect
Avalon-ST Adapter QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Memory-Mapped Router QsysInterconnect
Memory-Mapped Burst Adapter QsysInterconnect
Memory-Mapped Width Adapter QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Modular SGDMA Dispatcher BridgesAndAdaptors
Read Master QsysInterconnect
Write Master QsysInterconnect
Avalon-MM Pipeline Bridge QsysInterconnect
Avalon-ST Pipeline Stage QsysInterconnect
Avalon-ST Dual Clock FIFO QsysInterconnect
Interval Timer Peripherals

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 16.0.0 Standard


Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

16.0