Arria 10 - Board Update Portal utilizing EPCQ Flash Memory Reference Design

714506
12/21/2016

Introduction

This example is a web-based board update portal (BUP) which contains a NIOS II processor and a Triple Speed Ethernet media access control (MAC) MegaCore function. The design example implements a basic remote configuration features in Nios II-based systems utilizing EPCQ flash memory for Arria 10 GX FPGA device. The design can obtain an IP address from any DHCP server and serve a web page from the flash on the board to any host computer on the same network. Furthermore, this design supports a static IP address, where the developer must insert the required design manually before loading the design into EPCQ flash. The web page allows you to upload new design images for both user hardware and user software. Furthermore, you can trigger reconfiguration from factory image to user image through the web page.
IP Cores (36)
IP Core IP Core Category
Avalon-ST Adapter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
PIO (Parallel I/O) Other
Nios II Gen2 Processor NiosII
Nios II Gen2 Processor Unit NiosII
On-Chip Memory (RAM or ROM) OnChipMemory
Altera Serial Flash Controller Flash
Altera ASMI Parallel ConfigurationProgramming
Altera EPCQ Serial Flash controller core ConfigurationProgramming
Interval Timer Peripherals
Altera IOPLL ClocksPLLsResets
IRQ Mapper QsysInterconnect
IRQ Clock Crosser QsysInterconnect
JTAG UART ConfigurationProgramming
MM Interconnect QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Memory-Mapped Burst Adapter QsysInterconnect
Memory-Mapped Router QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Avalon-MM Pipeline Bridge QsysInterconnect
Reset Controller QsysInterconnect
Altera Remote Update ConfigurationProgramming
Altera Remote Update Core ConfigurationProgramming
Scatter-Gather DMA Controller BridgesAndAdaptors
System ID Peripheral Other
Triple-Speed Ethernet Ethernet
Altera LVDS SERDES Other
altera_lvds_core20 Other

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 16.1.0 Standard


Tags Details

Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

16.1

Other Tags

Intel® FPGAs

FPGA Design Store