Cyclone V - Board Update Portal based on Nios II Processor with EPCQ



This design example is a web-server based board update portal (BUP) design which contains a Nios II processor and a Triple Speed Ethernet media access control (MAC) MegaCore function. The design example implements basic remote configuration features in Nios II-based systems with EPCQ for Cyclone V E FPGA device. The design can obtain an IP address from any DHCP server and serve a web page from the flash on the board to any host computer on the same network. The web page allows you to upload new FPGA designs for both user hardware and user software, at the same time you can also trigger reconfiguration from factory image to user image through the web page.
IP Cores (42)
IP Core IP Core Category
Avalon-ST Adapter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
PIO (Parallel I/O) Other
Nios II Gen2 Processor NiosII
On-Chip Memory (RAM or ROM) OnChipMemory
Altera PLL ClocksPLLsResets
Altera Serial Flash Controller Flash
Altera ASMI Parallel ConfigurationProgramming
Altera EPCQ Serial Flash controller core ConfigurationProgramming
Triple-Speed Ethernet Ethernet
Generic Tri-State Controller Other
Avalon-MM Slave Translator QsysInterconnect
Tristate Controller Aggregator QsysInterconnect
Tristate Controller Translator QsysInterconnect
Interval Timer Peripherals
IRQ Mapper QsysInterconnect
IRQ Clock Crosser QsysInterconnect
JTAG UART ConfigurationProgramming
Altera Avalon LCD 16207 Peripherals
MM Interconnect QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Memory-Mapped Burst Adapter QsysInterconnect
Memory-Mapped Width Adapter QsysInterconnect
Memory-Mapped Router QsysInterconnect
Avalon-MM Pipeline Bridge QsysInterconnect
Altera Remote Update ConfigurationProgramming
Altera Remote Update Core ConfigurationProgramming
Reset Controller QsysInterconnect
Scatter-Gather DMA Controller BridgesAndAdaptors
System ID Peripheral Other
Tri-State Conduit Bridge QsysInterconnect
Tri-State Conduit Pin Sharer QsysInterconnect
Memory-Mapped Arbiter QsysInterconnect
Tri-State Conduit Pin Sharer Core QsysInterconnect

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

Prepare the design template in the Quartus Prime software command-line

At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par

Once the process completes, then type:

quartus_sh --platform -name <project>


* ACDS Version: 16.0.0 Standard