Stratix 10 - AN881: PCIe Gen3x16 Avalon-MM DMA with DDR4 and HBM2 Reference Design



This reference design demonstrates the performance of the Avalon-MM Intel Stratix 10 Hard IP+ for PCI Express, a high-performance DMA controller with two types of memory solutions: external (DDR4) and HBM2 memories. The Read Data Mover moves data from the system memory to the external or HBM2 memory in Avalon-MM space . The Write Data Mover moves data from the external or HBM2 memory in the application logic to the system memory in PCIe* space.
IP Cores (29)
IP Core IP Core Category
Top level generated instrumentation fabric Debug & Performance
Avalon-ST Single Clock FIFO QsysInterconnect
MM Interconnect QsysInterconnect
Memory-Mapped Router QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Memory-Mapped Burst Adapter QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Reset Controller QsysInterconnect
Avalon-MM Clock Crossing Bridge QsysInterconnect
Altera IOPLL ClocksPLLsResets
AXI Translator HardProcessorComponents
AXI Slave Agent HardProcessorComponents
Stratix 10 External Memory Interfaces Memory Interfaces and Controllers
EMIF Architecture Component for the Stratix 10 Device Family Internal Components
Arria 10 External Memory Interfaces Debug Component ExternalMemoryInterfaces
Avalon-MM Pipeline Bridge QsysInterconnect
alt_mem_if JTAG to Avalon Master Bridge BridgesAndAdaptors
Avalon Packets to Transaction Converter QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Avalon-ST Bytes to Packets Converter QsysInterconnect
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
AXI Bridge Memory Mapped

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

Prepare the design template in the Quartus Prime software command-line

At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par

Once the process completes, then type:

quartus_sh --platform -name <project>


* ACDS Version: 19.2.0 Pro

Design Details

Device Family

Intel® Stratix® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version