Intel® Arria® 10 GX 660 FPGA
Specifications
Compare Intel® Products
Essentials
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Product Collection
Intel® Arria® 10 GX FPGA
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Marketing Status
Launched
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Launch Date
2013
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Lithography
20 nm
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Resources
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Logic Elements (LE)
660000
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Adaptive Logic Modules (ALM)
250540
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Adaptive Logic Module (ALM) Registers
1002160
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Fabric and I/O Phase-Locked Loops (PLLs)
32
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Maximum Embedded Memory
47.7 Mb
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Digital Signal Processing (DSP) Blocks
1687
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Digital Signal Processing (DSP) Format
Multiply, Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, DDR3, QDR II, QDR II+, RLDRAM 3, QDR IV, LPDDR3, DDR3L
I/O Specifications
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Maximum User I/O Count†
696
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I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
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Maximum LVDS Pairs
270
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Maximum Non-Return to Zero (NRZ) Transceivers†
48
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Maximum Non-Return to Zero (NRZ) Data Rate†
17.4 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3
Advanced Technologies
Package Specifications
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Package Options
F1152, F1517
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Retired and discontinued
Trade compliance information
- ECCN Varies By Product
- CCATS Varies By Product
- US HTS 8542390001
PCN Information
SR4JE
- 965433 PCN
SR4BL
- 965191 PCN
SR6FN
- 967704 PCN
SR6FM
- 967703 PCN
SR4BJ
- 965189 PCN
SR6FL
- 967702 PCN
SR6FK
- 967701 PCN
SR6FJ
- 967700 PCN
SR4BG
- 965187 PCN
SR4FK
- 965333 PCN
SR6FH
- 967699 PCN
SR4J9
- 965428 PCN
SR4J8
- 965427 PCN
SR4J7
- 965425 PCN
SR4J6
- 965424 PCN
SR4J5
- 965423 PCN
SR4JD
- 965432 PCN
SR4JC
- 965431 PCN
SR4JB
- 965430 PCN
SR4JA
- 965429 PCN
SRC2X
- 974706 PCN
SRC2W
- 974705 PCN
SR4AC
- 965149 PCN
SR4AB
- 965148 PCN
SRKFU
- 99A8R8 PCN
SR6EA
- 967657 PCN
SR4J4
- 965422 PCN
SR4AE
- 965151 PCN
SR4AD
- 965150 PCN
SR4LZ
- 965524 PCN
SR4LY
- 965523 PCN
SRBHG
- 973607 PCN
SR4LX
- 965522 PCN
SRBHF
- 973606 PCN
SR4LW
- 965521 PCN
SRBHE
- 973604 PCN
SR6E9
- 967656 PCN
SR4DY
- 965276 PCN
SR6E8
- 967655 PCN
SR4DX
- 965275 PCN
SR6E7
- 967653 PCN
SR6E6
- 967652 PCN
SRBH9
- 973599 PCN
SRBH8
- 973598 PCN
SRBH7
- 973596 PCN
SRBH6
- 973595 PCN
SR4LV
- 965520 PCN
SRBHD
- 973603 PCN
SR4LU
- 965519 PCN
SRBHC
- 973602 PCN
SRBHB
- 973601 PCN
SRBHA
- 973600 PCN
SR4M3
- 965528 PCN
SR4M2
- 965527 PCN
SR4M1
- 965526 PCN
SR4M0
- 965525 PCN
SR59J
- 966298 PCN
SR59H
- 966297 PCN
SR59G
- 966296 PCN
SR59F
- 966295 PCN
SR59E
- 966294 PCN
SR59D
- 966293 PCN
SR59C
- 966292 PCN
SR59K
- 966299 PCN
SR59B
- 966291 PCN
SR4BP
- 965195 PCN
SR6FQ
- 967706 PCN
SR4BN
- 965194 PCN
SR6FP
- 967705 PCN
SR4BM
- 965192 PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.