Stratix® V 5SGSD4 FPGA
Specifications
Compare Intel® Products
Essentials
-
Product Collection
Stratix® V GS FPGA
-
Marketing Status
Launched
-
Launch Date
2010
-
Lithography
28 nm
Sign in with your CNDA account to view additional SKU details.
Resources
-
Logic Elements (LE)
360000
-
Adaptive Logic Modules (ALM)
135840
-
Adaptive Logic Module (ALM) Registers
543360
-
Fabric and I/O Phase-Locked Loops (PLLs)
24
-
Maximum Embedded Memory
23.15 Mb
-
Digital Signal Processing (DSP) Blocks
1044
-
Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP)
-
Hard Memory Controllers
No
-
External Memory Interfaces (EMIF)
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3
I/O Specifications
-
Maximum User I/O Count†
696
-
I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, HSTL, HSUL, Differential SSTL, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL, BLVDS
-
Maximum LVDS Pairs
348
-
Maximum Non-Return to Zero (NRZ) Transceivers†
36
-
Maximum Non-Return to Zero (NRZ) Data Rate†
14.1 Gbps
-
Transceiver Protocol Hard IP
PCIe Gen3
Package Specifications
-
Package Options
F780, F1152, F1517
Supplemental Information
-
Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
Sign in with your CNDA account to view additional SKU details.
Ordering and spec information
Retired and discontinued
Trade compliance information
- ECCN Varies By Product
- CCATS Varies By Product
- US HTS 8542390001
PCN Information
SRHES
- 999XJ5 PCN
SRHF4
- 999XJL PCN
SRHER
- 999XJ4 PCN
SRHEQ
- 999XJ3 PCN
SRHEP
- 999XJ2 PCN
SRHEN
- 999XJ1 PCN
SRHEM
- 999XJ0 PCN
SRHEX
- 999XJC PCN
SRHEW
- 999XJA PCN
SRHEV
- 999XJ9 PCN
SRHEU
- 999XJ7 PCN
SRHET
- 999XJ6 PCN
SR80X
- 969581 PCN
SR818
- 969592 PCN
SR81A
- 969594 PCN
SR817
- 969591 PCN
SR816
- 969590 PCN
SR814
- 969588 PCN
SR813
- 969587 PCN
SR811
- 969585 PCN
SRHHA
- 999XML PCN
SRHGU
- 999XLX PCN
SRHGT
- 999XLW PCN
SRHGS
- 999XLV PCN
SRHH4
- 999XMC PCN
SRHGR
- 999XLT PCN
SRHH3
- 999XM9 PCN
SRHGQ
- 999XLR PCN
SRHH2
- 999XM8 PCN
SRHGP
- 999XLP PCN
SRHH1
- 999XM6 PCN
SRHH0
- 999XM5 PCN
SRHGN
- 999XLN PCN
SRHGZ
- 999XM4 PCN
SRHGY
- 999XM3 PCN
SRHH9
- 999XMK PCN
SRHGW
- 999XM0 PCN
SRHH8
- 999XMJ PCN
SRHH7
- 999XMH PCN
SR87E
- 969802 PCN
SRHGD
- 999XLA PCN
SR87C
- 969800 PCN
SRHGC
- 999XL9 PCN
SRHGB
- 999XL8 PCN
SR8XB
- 970698 PCN
SRHGA
- 999XL6 PCN
SRHGM
- 999XLM PCN
SRHFT
- 999XKJ PCN
SR874
- 969792 PCN
SRHFS
- 999XKH PCN
SR873
- 969791 PCN
SR8X4
- 970691 PCN
SRHFR
- 999XKF PCN
SR872
- 969790 PCN
SRHFQ
- 999XKD PCN
SRHG2
- 999XKX PCN
SR8X2
- 970689 PCN
SRHFP
- 999XKC PCN
SRHG1
- 999XKW PCN
SR8X1
- 970688 PCN
SRHG0
- 999XKT PCN
SRHFN
- 999XKA PCN
SRHFM
- 999XK9 PCN
SR8WZ
- 970686 PCN
SRHG9
- 999XL5 PCN
SR877
- 969795 PCN
SR8X8
- 970695 PCN
SRHFL
- 999XK8 PCN
SRHFK
- 999XK7 PCN
SRHJN
- 999XPF PCN
SRHJM
- 999XPC PCN
Drivers and Software
Description
Type
More
OS
Version
Date
All
View Details
Download
No results found for
Y
/apps/intel/arksuite/template/arkProductPageTemplate
Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.