Serial Gigabit Media Independent Interface

The LVDS I/Os in the Intel® Stratix® 10, Intel® Arria® 10, Stratix® V, Stratix® IV, Stratix® III, Arria® V, Arria® II GX (fast speed grade), Intel® Cyclone® 10 GX and LP FPGAs allow you to easily implement the Serial Gigabit Media Independent Interface (SGMII) for 10/100/1000 Mb or Gigabit Ethernet. These devices have built-in serializer/deserializer (SERDES) circuitry that supports high-speed LVDS interfaces at data rates up to 1.4 Gbps. The SERDES circuitry is configured to support source synchronous and asynchronous serial data communication for the SGMII interface at 1.25 Gbps. This SGMII solution meets the SGMII specification and saves cost and power in systems that have low to high port-count Gigabit Ethernet per device.

The integrated gigabit serial transceivers in Intel Stratix 10, Intel Arria 10, Stratix V, Stratix IV, Stratix® II GX, Arria series, Intel Cyclone 10 GX, Cyclone® V GX, Cyclone V GT, and Cyclone® IV GX also support the SGMII interface.

SGMII Applications

A typical chip-to-chip SGMII application can use between 12 to 48 full-duplex SGMII for 10/100/1000 Mbps Ethernet or Gigabit Ethernet links. For applications with SGMII links, the LVDS I/Os offer a preferred solution with low-power differential signaling capability compared to transceiver based SGMII implementations.

Figure 1 shows examples of a Gigabit Ethernet line card design consisting of the Intel FPGA Triple-Speed Ethernet Intel FPGA IP function connected by SGMII either to a backplane or through a PHY device to a 10/100/1000 Mbps Ethernet network or backplane. These two examples show that both LVDS I/O and serial transceivers in different Intel FPGA devices can be used to realize SGMII.

Figure 1. SGMII Connectivity Choices with an Intel FPGA and a PHY Device

Note:

  1. Marvell 88E1112S and 88E1240 and Broadcom BCM5461S and 8012S are examples of PHY devices.

These Intel FPGAs with SGMII capable LVDS I/Os can also provide connectivity between a Gigabit Ethernet small form-factor pluggable (SFP) optical or copper module port, a host processor, and a backplane driver on a line card using SGMII interface with LVDS I/Os. Figure 2 shows two examples of a Gigabit Ethernet line card with an Intel FPGA connected by the SGMII interface to a 10/100/1000 Mbps or Gigabit Ethernet SFP pluggable module with LVDS I/Os and serial transceivers, respectively.

Figure 2. SGMII Connectivity Choices with an Intel FPGA and an SFP Module

SGMII Features in Intel® FPGAs

Intel® FPGAs with SGMII capable LVDS I/Os support three receiver datapath modes with LVDS I/Os:

  • Dynamic phase alignment (DPA) mode
  • Non-DPA mode
  • Soft-clock data recovery (CDR) mode

For SGMII, use soft-CDR mode and DPA mode (source synchronous mode) in the receive datapath for data communication.

  • Soft-CDR mode in asynchronous systems. In these systems, there is no source synchronous clock sent with the data channels from the upstream transmitter. The transmitter and receiver use reference clocks from two different sources.
  • Soft-CDR mode in synchronous systems. The transmitter and receiver use reference clocks from the same sources.
  • Source synchronous mode. In these systems, a source synchronous clock is sent with the data channels. The receiver nodes use this source synchronous clock to recover the received data.

The LVDS transmitters in Intel FPGA devices with SGMII capable LVDS I/Os have programmable output voltage settings, output common mode range, and settings for pre-emphasis to drive various system channel characteristics flexibly. On the receiver side, these devices can operate with a wide range of input voltage amplitudes and input common modes for proper operation in various systems channels.

Triple-Speed Ethernet MegaCore Function

Intel offers a complete innovative logic solution for Ethernet applications with Stratix V, Stratix IV, Stratix III, Stratix II GX, and Arria series devices using the Triple-Speed Ethernet Intel FPGA IP for physical media attachment (PMA), physical coding sublayer (PCS), and media access control (MAC). The Triple-Speed Ethernet Intel FPGA IP can use the LVDS hard macro of the Stratix V, Stratix IV, Stratix III, Arria V, and Arria II GX device configured as soft-CDR. Contact your Intel FPGA sales representative for more information about the Triple-Speed Ethernet Intel FPGA IP.