Intel(R) 64 Architecture x2APIC Specification

Intel(R) 64 Architecture x2APIC Specification

Intel(R) 64 Architecture x2APIC Specification

Intel® 64 Architecture x2APIC Specification


The xAPIC architecture provided a key mechanism for interrupt delivery in many generations of Intel processors and platforms across different market segments. This document describes the x2APIC architecture which is extended from the xAPIC architecture (the latter was first implemented on Intel® Pentium® 4 Processors, and... extended the APIC architecture implemented on Pentium and P6 processors). Extensions to the xAPIC architecture are intended primarily to increase processor addressability. The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations. Specifically, x2APIC
• Retains all key elements of compatibility to the xAPIC architecture:
• delivery modes,
• interrupt and processor priorities,
• interrupt sources,
• interrupt destination types;
• Provides extensions to scale processor addressability for both the logical and physical destination modes;
• Adds new features to enhance performance of interrupt delivery;
• Reduces complexity of logical destination mode interrupt delivery on link based architectures.

Impacted Platform Components

x2APIC is architected to extend from the xAPIC architecture while minimizing the impact on platform components. Specifically, support for the x2APIC architecture can be implemented in the local APIC unit. All existing PCI/MSI capable devices and IOxAPIC unit should work with the x2APIC extensions defined in this document. The x2APIC architecture also provides flexibility to cope with the underlying fabrics that connect the PCI devices, IOxAPICs and Local APIC units. Modifications to ACPI interfaces to support x2APIC are described in the ACPI 4.0 specification.

Read the full Intel® 64 Architecture x2APIC Specification.

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