Use the "keep" attribute to preserve the constant wire as shown in the code below:
For VHDL:
signal const_zero_sig : std_logic;
attribute keep: boolean;
attribute keep of const_zero_sig: signal is true;
begin
const_zero_sig <= \'0\';
TRI_PIN <= const_zero_sig when ENABLE=\'1\' else \'Z\';
For Verilog:
wire const_zero_sig /* synthesis keep */;
assign const_zero_sig = 1\'b0;
assign TRI_PIN = enable? const_zero_sig : 1\'bz;
This problem is scheduled to be resolved in a future release of the Quartus II software.