Article ID: 000075796 Content Type: Error Messages Last Reviewed: 08/14/2023

Error: Could not find a location with: OCT_CAL_BLOCK_ID

Environment

  • Quartus® II Subscription Edition
  • DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When compiling a design with multiple UniPHY-based DDR2 or DDR3 memory controllers in the Quartus® II software version 12.1, you may experience the following error:

    Error : Illegal constraint of pin to the region (X1, Y1) to (X2, Y2): no valid locations in region

    Info : The pin name: mem_ck

    Info : The I/O pad is constrained to the location PIN_NUM due to: User Location Constraints (PIN_NUM)

    Error: Could not find a location with: OCT_CAL_BLOCK_ID of 2 (1 location affected)

    Info: pin containing PIN_NUM

    The error is generated because the mem_ck pin is assigned to the wrong OCT termination control block.

    Resolution

    The workaround is to add the following termination control block assignment to the QSF file or Assignment Editor:

     

    set_instance_assignment -name TERMINATION_CONTROL_BLOCK “<hierarchy>|altera_mem_if_oct_stratixv:oct0|sd1a_0" -to mem_ck*

     

    This issue has been fixed in the Quartus® II software 14.1 version.

     

    Related Products

    This article applies to 18 products

    Cyclone® V E FPGA
    Stratix® V E FPGA
    Stratix® IV E FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V SX SoC FPGA
    Stratix® V GX FPGA
    Cyclone® V GX FPGA
    Stratix® V GT FPGA
    Arria® V GZ FPGA
    Stratix® V GS FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Stratix® III FPGAs
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA