Article ID: 000074088 Content Type: Error Messages Last Reviewed: 11/09/2010

Warning (14320): Synthesized away node "<node name>:ALTLVDS_RX_component||fast_clock"

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see this warning when compiling a VHDL variation file using the ALTLVDS_RX megafunction in the Quartus® II software version 10.0 SP1 and implementing the SERDES in LE mode. Depending on your selections in the ALTLVDS_RX MegaWizard™ Plug-In Manager, the rx_outclock port may be declared as STD_LOGIC_VECTOR (0 DOWNTO 0) instead of simply STD_LOGIC.

This problem may be triggered if you toggle the What is the clock resource used for 'rx_outclock'? setting.

To work around this problem, edit the ALTLVDS_RX variation file. There are four locations that need to be edited:

  • In the ENTITY PORT section, replace the text OUT STD_LOGIC_VECTOR (0 DOWNTO 0) with the text OUT STD_LOGIC.
  • In the COMPONENT PORT section, replace the text OUT STD_LOGIC_VECTOR (0 DOWNTO 0) with the text OUT STD_LOGIC.
  • Under BEGIN, locate the sub_wire that maps the signal to rx_outclock and remove the text (0 DOWNTO 0).
  • In the ARCHITECTURE section before the COMPONENT, locate the sub_wire used in the previous step and replace the text STD_LOGIC_VECTOR (0 DOWNTO 0) with the text STD_LOGIC.

This problem is scheduled to be fixed in a future version of the Quartus II software.

Related Products

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Intel® Programmable Devices