Intel® Arria® 10 FPGA – UHD Video Reference Design

Intel® Arria® 10 FPGA – UHD Video Reference Design

715141
9/13/2017

Introduction

The Intel® Arria® 10 FPGA UHD video reference design demonstrates HDMI 2.0 video connectivity with a video processing pipeline based on IP cores from the Video and Image Processing Suite Intel FPGA IP.

Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

17.0

IP Cores (61)
IP Core IP Core Category
Altera Arria 10 XCVR Reset Sequencer Other
Altera IOPLL ClocksPLLsResets
Reset Controller QsysInterconnect
ALTCLKCTRL ClocksPLLsResets
RAM: 1-PORT OnChipMemory
Arria 10 Transceiver Native PHY TransceiverPHY
Transceiver PHY Reset Controller TransceiverPHY
Altera HDMI AudioVideo
Altera GPIO Other
Altera GPIO Core Other
Altera PLL Reconfig ClocksPLLsResets
Arria 10 FPLL ClocksPLLsResets
Avalon-ST Adapter QsysInterconnect
Avalon-ST Data Format Adapter QsysInterconnect
Nios II Gen2 Processor NiosII
Nios II Gen2 Processor Unit NiosII
On-Chip Memory (RAM or ROM) OnChipMemory
Arria 10 External Memory Interfaces ExternalMemoryInterfaces
EMIF Core Component for 20nm Families ExternalMemoryInterfaces
Avalon-MM Pipeline Bridge QsysInterconnect
MM Interconnect QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Arria 10 External Memory Interfaces Debug Component ExternalMemoryInterfaces
alt_mem_if JTAG to Avalon Master Bridge BridgesAndAdaptors
Avalon-ST Bytes to Packets Converter QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Avalon Packets to Transaction Converter QsysInterconnect
Altera Avalon-MM Efficiency Monitor and Protcol Checker Core QsysInterconnect
altera_jtag_avalon_master QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Memory-Mapped Router QsysInterconnect
IRQ Mapper QsysInterconnect
IRQ Clock Crosser QsysInterconnect
JTAG UART ConfigurationProgramming
PIO (Parallel I/O) Other
Avalon-ST Pipeline Stage QsysInterconnect
Memory-Mapped Width Adapter QsysInterconnect
System ID Peripheral Other
Avalon-ST Video stream cleaner QsysInterconnect
Clipper II (4K Ready) AudioVideo
Deinterlacer II (with Sobel based HQ mode) AudioVideo
Video Input Bridge AudioVideo
Clocked Video Input II (4K Ready) AudioVideo
Clocked Video Output II (4K Ready) AudioVideo
Color Space Converter (CSC) II (4K Ready) AudioVideo
CSC Algorithmic Core Other
Mixer II (4K Ready) AudioVideo
Scaler II AudioVideo
Frame Buffer II (4K Ready) AudioVideo
Interval Timer Peripherals
Avalon-ST Multiplexer QsysInterconnect

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 17.0.0 Standard


Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

17.0