---

CH0_TRANSFORM

video_transform v1.0

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>clock</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>csi_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>rsi_reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>rgbin</name> <type>avalon_streaming</type> <isStart>false</isStart> <ports> <port> <name>asi_rgbin_ready</name> <role>ready</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>asi_rgbin_valid</name> <role>valid</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>asi_rgbin_data</name> <role>data</role> <direction>Input</direction> <width>24</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>associatedReset</key> <value>reset</value> </entry> <entry> <key>beatsPerCycle</key> <value>1</value> </entry> <entry> <key>dataBitsPerSymbol</key> <value>8</value> </entry> <entry> <key>emptyWithinPacket</key> <value>false</value> </entry> <entry> <key>errorDescriptor</key> </entry> <entry> <key>firstSymbolInHighOrderBits</key> <value>true</value> </entry> <entry> <key>highOrderSymbolAtMSB</key> <value>false</value> </entry> <entry> <key>maxChannel</key> <value>0</value> </entry> <entry> <key>packetDescription</key> <value></value> </entry> <entry> <key>readyLatency</key> <value>0</value> </entry> <entry> <key>symbolsPerBeat</key> <value>1</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>s0</name> <type>avalon</type> <isStart>false</isStart> <ports> <port> <name>avs_s0_write</name> <role>write</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avs_s0_read</name> <role>read</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avs_s0_address</name> <role>address</role> <direction>Input</direction> <width>4</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avs_s0_writedata</name> <role>writedata</role> <direction>Input</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avs_s0_readdata</name> <role>readdata</role> <direction>Output</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>embeddedsw.configuration.isFlash</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isMemoryDevice</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isNonVolatileStorage</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isPrintableDevice</key> <value>0</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>addressAlignment</key> <value>DYNAMIC</value> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressSpan</key> <value>64</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>associatedReset</key> <value>reset</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>bridgedAddressOffset</key> <value>0</value> </entry> <entry> <key>bridgesToMaster</key> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>explicitAddressSpan</key> <value>0</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isFlash</key> <value>false</value> </entry> <entry> <key>isMemoryDevice</key> <value>false</value> </entry> <entry> <key>isNonVolatileStorage</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>0</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>minimumUninterruptedRunLength</key> <value>1</value> </entry> <entry> <key>printableDevice</key> <value>false</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitStates</key> <value>0</value> </entry> <entry> <key>readWaitTime</key> <value>0</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>transparentBridge</key> <value>false</value> </entry> <entry> <key>wellBehavedWaitrequest</key> <value>false</value> </entry> <entry> <key>writeLatency</key> <value>0</value> </entry> <entry> <key>writeWaitStates</key> <value>0</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>xyzout</name> <type>avalon_streaming</type> <isStart>true</isStart> <ports> <port> <name>aso_xyzout_ready</name> <role>ready</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>aso_xyzout_valid</name> <role>valid</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>aso_xyzout_data</name> <role>data</role> <direction>Output</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>associatedReset</key> <value>reset</value> </entry> <entry> <key>beatsPerCycle</key> <value>1</value> </entry> <entry> <key>dataBitsPerSymbol</key> <value>8</value> </entry> <entry> <key>emptyWithinPacket</key> <value>false</value> </entry> <entry> <key>errorDescriptor</key> </entry> <entry> <key>firstSymbolInHighOrderBits</key> <value>true</value> </entry> <entry> <key>highOrderSymbolAtMSB</key> <value>false</value> </entry> <entry> <key>maxChannel</key> <value>0</value> </entry> <entry> <key>packetDescription</key> <value></value> </entry> <entry> <key>readyLatency</key> <value>0</value> </entry> <entry> <key>symbolsPerBeat</key> <value>1</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>video_transform</className> <version>1.0</version> <displayName>video_transform</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors/> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos> <entry> <key>s0</key> <value> <connectionPointName>s0</connectionPointName> <suppliedSystemInfos> <entry> <key>ADDRESS_MAP</key> <value>&lt;address-map&gt;&lt;slave name='s0' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value> </entry> <entry> <key>ADDRESS_WIDTH</key> <value>6</value> </entry> <entry> <key>MAX_SLAVE_DATA_WIDTH</key> <value>32</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> </connPtSystemInfos> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_CH0_TRANSFORM</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_CH0_TRANSFORM</fileSetName> <fileSetFixedName>system_CH0_TRANSFORM</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_CH0_TRANSFORM</fileSetName> <fileSetFixedName>system_CH0_TRANSFORM</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_CH0_TRANSFORM</fileSetName> <fileSetFixedName>system_CH0_TRANSFORM</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView ip\system\system_CH0_TRANSFORM.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG deviceFamily Arria 10 generateLegacySim false

  

Software Assignments (none)

---

DDR_subsystem

sysA v1.0

Parameters AUTO_GENERATION_ID 1481055122 AUTO_UNIQUE_ID system_DDR_subsystem AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG AUTO_DEVICE_SPEEDGRADE 3 AUTO_DDR4_CONTROLLER_PLL_REF_CLK_CLOCK_RATE 0 AUTO_DDR4_CONTROLLER_PLL_REF_CLK_CLOCK_DOMAIN 5 AUTO_DDR4_CONTROLLER_PLL_REF_CLK_RESET_DOMAIN 5 deviceFamily Arria 10 generateLegacySim false

  

Software Assignments (none)

---

DDR_subsystem_bb_emif_master

system_generic_component_0 v1.0

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>status</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>local_cal_success</name> <role>local_cal_success</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>local_cal_fail</name> <role>local_cal_fail</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>emif_usr_reset_n</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>emif_usr_reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>emif_usr_clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>emif_usr_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>200000000</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>ctrl_amm_0</name> <type>avalon</type> <isStart>true</isStart> <ports> <port> <name>amm_ready_0</name> <role>waitrequest_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_read_0</name> <role>read</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_write_0</name> <role>write</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_address_0</name> <role>address</role> <direction>Output</direction> <width>27</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_readdata_0</name> <role>readdata</role> <direction>Input</direction> <width>576</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_writedata_0</name> <role>writedata</role> <direction>Output</direction> <width>576</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_burstcount_0</name> <role>burstcount</role> <direction>Output</direction> <width>7</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_byteenable_0</name> <role>byteenable</role> <direction>Output</direction> <width>72</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_readdatavalid_0</name> <role>readdatavalid</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>adaptsTo</key> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>emif_usr_clk</value> </entry> <entry> <key>associatedReset</key> <value>emif_usr_reset_n</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>dBSBigEndian</key> <value>false</value> </entry> <entry> <key>doStreamReads</key> <value>false</value> </entry> <entry> <key>doStreamWrites</key> <value>false</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isAsynchronous</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isReadable</key> <value>false</value> </entry> <entry> <key>isWriteable</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maxAddressWidth</key> <value>32</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>64</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitTime</key> <value>1</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>system_generic_component_0</className> <version>1.0</version> <displayName>system_generic_component_0</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors/> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos/> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>bb_emif_status</hdlLibraryName> <fileSets> <fileSet> <fileSetName>QUARTUS_SYNTH</fileSetName> <fileSetFixedName>bb_emif_status</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>SIM_VERILOG</fileSetName> <fileSetFixedName>bb_emif_status</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>SIM_VHDL</fileSetName> <fileSetFixedName>bb_emif_status</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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DDR_subsystem_ddr4_controller

altera_emif v16.1

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>ctrl_amm_0</name> <type>avalon</type> <isStart>false</isStart> <ports> <port> <name>amm_ready_0</name> <role>waitrequest_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_read_0</name> <role>read</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_write_0</name> <role>write</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_address_0</name> <role>address</role> <direction>Input</direction> <width>26</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_readdata_0</name> <role>readdata</role> <direction>Output</direction> <width>576</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_writedata_0</name> <role>writedata</role> <direction>Input</direction> <width>576</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_burstcount_0</name> <role>burstcount</role> <direction>Input</direction> <width>7</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_byteenable_0</name> <role>byteenable</role> <direction>Input</direction> <width>72</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_readdatavalid_0</name> <role>readdatavalid</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>embeddedsw.configuration.isFlash</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isMemoryDevice</key> <value>1</value> </entry> <entry> <key>embeddedsw.configuration.isNonVolatileStorage</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isPrintableDevice</key> <value>0</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>addressAlignment</key> <value>DYNAMIC</value> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressSpan</key> <value>4831838208</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>emif_usr_clk</value> </entry> <entry> <key>associatedReset</key> <value>emif_usr_reset_n</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>bridgedAddressOffset</key> <value>0</value> </entry> <entry> <key>bridgesToMaster</key> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>explicitAddressSpan</key> <value>0</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isFlash</key> <value>false</value> </entry> <entry> <key>isMemoryDevice</key> <value>true</value> </entry> <entry> <key>isNonVolatileStorage</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>64</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>minimumUninterruptedRunLength</key> <value>1</value> </entry> <entry> <key>printableDevice</key> <value>false</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitStates</key> <value>1</value> </entry> <entry> <key>readWaitTime</key> <value>1</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>transparentBridge</key> <value>false</value> </entry> <entry> <key>wellBehavedWaitrequest</key> <value>false</value> </entry> <entry> <key>writeLatency</key> <value>0</value> </entry> <entry> <key>writeWaitStates</key> <value>0</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>emif_usr_clk</name> <type>clock</type> <isStart>true</isStart> <ports> <port> <name>emif_usr_clk</name> <role>clk</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedDirectClock</key> </entry> <entry> <key>clockRate</key> <value>200000000</value> </entry> <entry> <key>clockRateKnown</key> <value>true</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>emif_usr_reset_n</name> <type>reset</type> <isStart>true</isStart> <ports> <port> <name>emif_usr_reset_n</name> <role>reset_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedDirectReset</key> </entry> <entry> <key>associatedResetSinks</key> <value>global_reset_n</value> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>global_reset_n</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>global_reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>mem</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>mem_ck</name> <role>mem_ck</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_ck_n</name> <role>mem_ck_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_a</name> <role>mem_a</role> <direction>Output</direction> <width>17</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_act_n</name> <role>mem_act_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_ba</name> <role>mem_ba</role> <direction>Output</direction> <width>2</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_bg</name> <role>mem_bg</role> <direction>Output</direction> <width>2</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_cke</name> <role>mem_cke</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_cs_n</name> <role>mem_cs_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_odt</name> <role>mem_odt</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_reset_n</name> <role>mem_reset_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_par</name> <role>mem_par</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_alert_n</name> <role>mem_alert_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_dqs</name> <role>mem_dqs</role> <direction>Bidir</direction> <width>9</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_dqs_n</name> <role>mem_dqs_n</role> <direction>Bidir</direction> <width>9</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_dq</name> <role>mem_dq</role> <direction>Bidir</direction> <width>72</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_dbi_n</name> <role>mem_dbi_n</role> <direction>Bidir</direction> <width>9</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>oct</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>oct_rzqin</name> <role>oct_rzqin</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>pll_ref_clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>pll_ref_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>status</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>local_cal_success</name> <role>local_cal_success</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>local_cal_fail</name> <role>local_cal_fail</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>altera_emif</className> <version>16.1</version> <displayName>Arria 10 External Memory Interfaces</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors> <descriptor> <parameterDefaultValue>50000000</parameterDefaultValue> <parameterName>CAL_DEBUG_CLOCK_FREQUENCY</parameterName> <parameterType>java.lang.Long</parameterType> <systemInfoArgs>cal_debug_clk_clock_sink</systemInfoArgs> <systemInfotype>CLOCK_RATE</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>SYS_INFO_DEVICE</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>SYS_INFO_DEVICE_FAMILY</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE_FAMILY</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>SYS_INFO_DEVICE_SPEEDGRADE</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>SYS_INFO_UNIQUE_ID</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>UNIQUE_ID</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue>0</parameterDefaultValue> <parameterName>TRAIT_SUPPORTS_VID</parameterName> <parameterType>java.lang.String</parameterType> <systemInfoArgs>SUPPORTS_VID</systemInfoArgs> <systemInfotype>PART_TRAIT</systemInfotype> </descriptor> </descriptors> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos> <entry> <key>ctrl_amm_0</key> <value> <connectionPointName>ctrl_amm_0</connectionPointName> <suppliedSystemInfos> <entry> <key>ADDRESS_MAP</key> <value>&lt;address-map&gt;&lt;slave name='ctrl_amm_0' start='0x0' end='0x120000000' datawidth='576' /&gt;&lt;/address-map&gt;</value> </entry> <entry> <key>ADDRESS_WIDTH</key> <value>33</value> </entry> <entry> <key>MAX_SLAVE_DATA_WIDTH</key> <value>576</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> <entry> <key>emif_usr_clk</key> <value> <connectionPointName>emif_usr_clk</connectionPointName> <suppliedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>200000000</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> </connPtSystemInfos> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_emif_0</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_emif_0</fileSetName> <fileSetFixedName>system_emif_0</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_emif_0</fileSetName> <fileSetFixedName>system_emif_0</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_emif_0</fileSetName> <fileSetFixedName>system_emif_0</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView ip/system/system_emif_0.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> CAL_DEBUG_CLOCK_FREQUENCY 50000000 SYS_INFO_DEVICE 10AX115R4F40I3SG SYS_INFO_DEVICE_FAMILY ARRIA10 SYS_INFO_DEVICE_SPEEDGRADE 3 SYS_INFO_UNIQUE_ID sysA_ddr4_controller TRAIT_SUPPORTS_VID 0 AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG deviceFamily Arria 10 generateLegacySim false

  

Software Assignments (none)

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RGB_DATA

altera_avalon_onchip_memory2 v16.1

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>clk1</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset1</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>reset</name> <role>reset</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>reset_req</name> <role>reset_req</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clk1</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>s1</name> <type>avalon</type> <isStart>false</isStart> <ports> <port> <name>address</name> <role>address</role> <direction>Input</direction> <width>10</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>clken</name> <role>clken</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>chipselect</name> <role>chipselect</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>write</name> <role>write</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>readdata</name> <role>readdata</role> <direction>Output</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>writedata</name> <role>writedata</role> <direction>Input</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>byteenable</name> <role>byteenable</role> <direction>Input</direction> <width>4</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>embeddedsw.configuration.isFlash</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isMemoryDevice</key> <value>1</value> </entry> <entry> <key>embeddedsw.configuration.isNonVolatileStorage</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isPrintableDevice</key> <value>0</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>addressAlignment</key> <value>DYNAMIC</value> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressSpan</key> <value>4096</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>clk1</value> </entry> <entry> <key>associatedReset</key> <value>reset1</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>bridgedAddressOffset</key> <value>0</value> </entry> <entry> <key>bridgesToMaster</key> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>explicitAddressSpan</key> <value>4096</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isFlash</key> <value>false</value> </entry> <entry> <key>isMemoryDevice</key> <value>true</value> </entry> <entry> <key>isNonVolatileStorage</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>0</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>minimumUninterruptedRunLength</key> <value>1</value> </entry> <entry> <key>printableDevice</key> <value>false</value> </entry> <entry> <key>readLatency</key> <value>1</value> </entry> <entry> <key>readWaitStates</key> <value>0</value> </entry> <entry> <key>readWaitTime</key> <value>0</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>transparentBridge</key> <value>false</value> </entry> <entry> <key>wellBehavedWaitrequest</key> <value>false</value> </entry> <entry> <key>writeLatency</key> <value>0</value> </entry> <entry> <key>writeWaitStates</key> <value>0</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>altera_avalon_onchip_memory2</className> <version>16.1</version> <displayName>On-Chip Memory (RAM or ROM)</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>autoInitializationFileName</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>UNIQUE_ID</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue>NONE</parameterDefaultValue> <parameterName>deviceFamily</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE_FAMILY</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue>NONE</parameterDefaultValue> <parameterName>deviceFeatures</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE_FEATURES</systemInfotype> </descriptor> </descriptors> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos> <entry> <key>s1</key> <value> <connectionPointName>s1</connectionPointName> <suppliedSystemInfos> <entry> <key>ADDRESS_MAP</key> <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value> </entry> <entry> <key>ADDRESS_WIDTH</key> <value>12</value> </entry> <entry> <key>MAX_SLAVE_DATA_WIDTH</key> <value>32</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> </connPtSystemInfos> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_RGB_DATA</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_RGB_DATA</fileSetName> <fileSetFixedName>system_RGB_DATA</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_RGB_DATA</fileSetName> <fileSetFixedName>system_RGB_DATA</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_RGB_DATA</fileSetName> <fileSetFixedName>system_RGB_DATA</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView ip\system\system_RGB_DATA.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap> <entry> <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key> <value>1</value> </entry> <entry> <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key> <value>0</value> </entry> <entry> <key>embeddedsw.CMacro.CONTENTS_INFO</key> <value>""</value> </entry> <entry> <key>embeddedsw.CMacro.DUAL_PORT</key> <value>0</value> </entry> <entry> <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key> <value>AUTO</value> </entry> <entry> <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key> <value>RGB_DATA</value> </entry> <entry> <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key> <value>1</value> </entry> <entry> <key>embeddedsw.CMacro.INSTANCE_ID</key> <value>RGBB</value> </entry> <entry> <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key> <value>1</value> </entry> <entry> <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key> <value>AUTO</value> </entry> <entry> <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key> <value>DONT_CARE</value> </entry> <entry> <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key> <value>0</value> </entry> <entry> <key>embeddedsw.CMacro.SIZE_MULTIPLE</key> <value>1</value> </entry> <entry> <key>embeddedsw.CMacro.SIZE_VALUE</key> <value>4096</value> </entry> <entry> <key>embeddedsw.CMacro.WRITABLE</key> <value>1</value> </entry> <entry> <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key> <value>SIM_DIR</value> </entry> <entry> <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key> <value>1</value> </entry> <entry> <key>embeddedsw.memoryInfo.GENERATE_HEX</key> <value>1</value> </entry> <entry> <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key> <value>0</value> </entry> <entry> <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key> <value>QPF_DIR</value> </entry> <entry> <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key> <value>32</value> </entry> <entry> <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key> <value>RGB_DATA</value> </entry> <entry> <key>postgeneration.simulation.init_file.param_name</key> <value>INIT_FILE</value> </entry> <entry> <key>postgeneration.simulation.init_file.type</key> <value>MEM_INIT</value> </entry> </assignmentValueMap> </assignmentDefinition> autoInitializationFileName system_RGB_DATA deviceFamily ARRIA10 deviceFeatures ADDRESS_STALL 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG generateLegacySim false

  

Software Assignments ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 1 ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 CONTENTS_INFO "" DUAL_PORT 0 GUI_RAM_BLOCK_TYPE AUTO INIT_CONTENTS_FILE RGB_DATA INIT_MEM_CONTENT 1 INSTANCE_ID RGBB NON_DEFAULT_INIT_FILE_ENABLED 1 RAM_BLOCK_TYPE AUTO READ_DURING_WRITE_MODE DONT_CARE SINGLE_CLOCK_OP 0 SIZE_MULTIPLE 1 SIZE_VALUE 4096 WRITABLE 1

---

byte_extract

byte_extract v1.0

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>clock</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>csi_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>rgbin</name> <type>avalon_streaming</type> <isStart>false</isStart> <ports> <port> <name>asi_rgbin_ready</name> <role>ready</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>asi_rgbin_valid</name> <role>valid</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>asi_rgbin_data</name> <role>data</role> <direction>Input</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>associatedReset</key> </entry> <entry> <key>beatsPerCycle</key> <value>1</value> </entry> <entry> <key>dataBitsPerSymbol</key> <value>8</value> </entry> <entry> <key>emptyWithinPacket</key> <value>false</value> </entry> <entry> <key>errorDescriptor</key> </entry> <entry> <key>firstSymbolInHighOrderBits</key> <value>true</value> </entry> <entry> <key>highOrderSymbolAtMSB</key> <value>false</value> </entry> <entry> <key>maxChannel</key> <value>0</value> </entry> <entry> <key>packetDescription</key> <value></value> </entry> <entry> <key>readyLatency</key> <value>0</value> </entry> <entry> <key>symbolsPerBeat</key> <value>1</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>xyzout</name> <type>avalon_streaming</type> <isStart>true</isStart> <ports> <port> <name>aso_xyzout_ready</name> <role>ready</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>aso_xyzout_valid</name> <role>valid</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>aso_xyzout_data</name> <role>data</role> <direction>Output</direction> <width>24</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>aso_xyzout_channel</name> <role>channel</role> <direction>Output</direction> <width>2</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>associatedReset</key> </entry> <entry> <key>beatsPerCycle</key> <value>1</value> </entry> <entry> <key>dataBitsPerSymbol</key> <value>8</value> </entry> <entry> <key>emptyWithinPacket</key> <value>false</value> </entry> <entry> <key>errorDescriptor</key> </entry> <entry> <key>firstSymbolInHighOrderBits</key> <value>true</value> </entry> <entry> <key>highOrderSymbolAtMSB</key> <value>false</value> </entry> <entry> <key>maxChannel</key> <value>3</value> </entry> <entry> <key>packetDescription</key> <value></value> </entry> <entry> <key>readyLatency</key> <value>0</value> </entry> <entry> <key>symbolsPerBeat</key> <value>1</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>byte_extract</className> <version>1.0</version> <displayName>byte_extract</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors/> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos/> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_byte_extract</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_byte_extract</fileSetName> <fileSetFixedName>system_byte_extract</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_byte_extract</fileSetName> <fileSetFixedName>system_byte_extract</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_byte_extract</fileSetName> <fileSetFixedName>system_byte_extract</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView ip\system\system_byte_extract.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG deviceFamily Arria 10 generateLegacySim false

  

Software Assignments (none)

---

clk

clock_source v0

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>clk</name> <type>clock</type> <isStart>true</isStart> <ports> <port> <name>clk_out</name> <role>clk</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedDirectClock</key> <value>clk_in</value> </entry> <entry> <key>clockRate</key> <value>50000000</value> </entry> <entry> <key>clockRateKnown</key> <value>true</value> </entry> <entry> <key>externallyDriven</key> <value>true</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>clk_in</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>in_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>qsys.ui.export_name</key> <value>clk</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>50000000</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>clk_in_reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>qsys.ui.export_name</key> <value>reset</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clk_in</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>clk_reset</name> <type>reset</type> <isStart>true</isStart> <ports> <port> <name>reset_n_out</name> <role>reset_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clk</value> </entry> <entry> <key>associatedDirectReset</key> <value>clk_in_reset</value> </entry> <entry> <key>associatedResetSinks</key> <value>clk_in_reset</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>clock_source</className> <version>0</version> <displayName>Clock Source</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors> <descriptor> <parameterDefaultValue>0</parameterDefaultValue> <parameterName>inputClockFrequency</parameterName> <parameterType>java.lang.Long</parameterType> <systemInfoArgs>clk_in</systemInfoArgs> <systemInfotype>CLOCK_RATE</systemInfotype> </descriptor> </descriptors> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos> <entry> <key>clk</key> <value> <connectionPointName>clk</connectionPointName> <suppliedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>50000000</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> <entry> <key>clk_in</key> <value> <connectionPointName>clk_in</connectionPointName> <suppliedSystemInfos/> <consumedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>0</value> </entry> </consumedSystemInfos> </value> </entry> </connPtSystemInfos> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_clk</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_clk</fileSetName> <fileSetFixedName>system_clk</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_clk</fileSetName> <fileSetFixedName>system_clk</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_clk</fileSetName> <fileSetFixedName>system_clk</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView ip\system\system_clk.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> inputClockFrequency 0 AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG deviceFamily Arria 10 generateLegacySim false

  

Software Assignments (none)

---

csr_slave

system_generic_component_0 v1.0

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>reset_sink</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>hw_reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>host_clk</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>avalon_slave_0</name> <type>avalon</type> <isStart>false</isStart> <ports> <port> <name>writeDataBus</name> <role>writedata</role> <direction>Input</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>addrBus</name> <role>address</role> <direction>Input</direction> <width>11</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>readDataBus</name> <role>readdata</role> <direction>Output</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>read_en</name> <role>read</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>write_en</name> <role>write</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>embeddedsw.configuration.isFlash</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isMemoryDevice</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isNonVolatileStorage</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isPrintableDevice</key> <value>0</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>addressAlignment</key> <value>DYNAMIC</value> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressSpan</key> <value>4096</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>host_clk</value> </entry> <entry> <key>associatedReset</key> <value>reset_sink</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>bridgedAddressOffset</key> </entry> <entry> <key>bridgesToMaster</key> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>explicitAddressSpan</key> <value>0</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isFlash</key> <value>false</value> </entry> <entry> <key>isMemoryDevice</key> <value>false</value> </entry> <entry> <key>isNonVolatileStorage</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>0</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>minimumUninterruptedRunLength</key> <value>1</value> </entry> <entry> <key>printableDevice</key> <value>false</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitStates</key> <value>1</value> </entry> <entry> <key>readWaitTime</key> <value>1</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>transparentBridge</key> <value>false</value> </entry> <entry> <key>wellBehavedWaitrequest</key> <value>false</value> </entry> <entry> <key>writeLatency</key> <value>0</value> </entry> <entry> <key>writeWaitStates</key> <value>0</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>host_clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>host_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>gpo_status</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>gpo_cr1</name> <role>gpo1</role> <direction>Output</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>gpo_cr2</name> <role>gpo2</role> <direction>Output</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>status1</name> <role>status1</role> <direction>Input</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>status2</name> <role>status2</role> <direction>Input</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>host_clk</value> </entry> <entry> <key>associatedReset</key> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>system_generic_component_0</className> <version>1.0</version> <displayName>system_generic_component_0</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors/> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos> <entry> <key>avalon_slave_0</key> <value> <connectionPointName>avalon_slave_0</connectionPointName> <suppliedSystemInfos> <entry> <key>ADDRESS_MAP</key> </entry> <entry> <key>ADDRESS_WIDTH</key> </entry> <entry> <key>MAX_SLAVE_DATA_WIDTH</key> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> </connPtSystemInfos> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>csr_slave</hdlLibraryName> <fileSets> <fileSet> <fileSetName>QUARTUS_SYNTH</fileSetName> <fileSetFixedName>cs_regs</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles> <fileSetFile> <fileSource>cs_regs.v</fileSource> <fileOutput>cs_regs.v</fileOutput> <fileKind>VERILOG</fileKind> <fileAttributes> <entry> <key>TOP_LEVEL_FILE</key> <value>true</value> </entry> </fileAttributes> </fileSetFile> </fileSetFiles> </fileSet> <fileSet> <fileSetName>SIM_VERILOG</fileSetName> <fileSetFixedName>cs_regs</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles> <fileSetFile> <fileSource>cs_regs.v</fileSource> <fileOutput>cs_regs.v</fileOutput> <fileKind>VERILOG</fileKind> <fileAttributes> <entry> <key>TOP_LEVEL_FILE</key> <value>true</value> </entry> </fileAttributes> </fileSetFile> </fileSetFiles> </fileSet> <fileSet> <fileSetName>SIM_VHDL</fileSetName> <fileSetFixedName>cs_regs</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles> <fileSetFile> <fileSource>cs_regs.v</fileSource> <fileOutput>cs_regs.v</fileOutput> <fileKind>VERILOG</fileKind> <fileAttributes> <entry> <key>TOP_LEVEL_FILE</key> <value>true</value> </entry> </fileAttributes> </fileSetFile> </fileSetFiles> </fileSet> </fileSets> </generationInfoDefinition> logicalView moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

custom_logic_bb

system_generic_component_0 v1.0

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>clock</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>clock_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>reset_reset</name> <role>reset</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>asi_in0</name> <type>avalon_streaming</type> <isStart>false</isStart> <ports> <port> <name>avalonst_source_valid</name> <role>valid</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_source_data</name> <role>data</role> <direction>Input</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalonst_source_channel</name> <role>channel</role> <direction>Input</direction> <width>8</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalonst_source_error</name> <role>error</role> <direction>Input</direction> <width>8</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalonst_source_startofpacket</name> <role>startofpacket</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_source_endofpacket</name> <role>endofpacket</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_source_empty</name> <role>empty</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_source_ready</name> <role>ready</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>associatedReset</key> <value>reset</value> </entry> <entry> <key>beatsPerCycle</key> <value>1</value> </entry> <entry> <key>dataBitsPerSymbol</key> <value>8</value> </entry> <entry> <key>emptyWithinPacket</key> <value>false</value> </entry> <entry> <key>errorDescriptor</key> </entry> <entry> <key>firstSymbolInHighOrderBits</key> <value>true</value> </entry> <entry> <key>highOrderSymbolAtMSB</key> <value>false</value> </entry> <entry> <key>maxChannel</key> <value>255</value> </entry> <entry> <key>packetDescription</key> <value></value> </entry> <entry> <key>readyLatency</key> <value>1</value> </entry> <entry> <key>symbolsPerBeat</key> <value>2</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>conduit_end</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>custom_bus</name> <role>custom_bus</role> <direction>Input</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>custom_signal1</name> <role>custom_signal1</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>custom_signal_2</name> <role>custom_signal_2</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>custom_irq</name> <role>irq</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>associatedReset</key> <value>reset</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>avalon_slave</name> <type>avalon</type> <isStart>false</isStart> <ports> <port> <name>avalon_slave_address</name> <role>address</role> <direction>Input</direction> <width>5</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalon_slave_read</name> <role>read</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalon_slave_readdata</name> <role>readdata</role> <direction>Output</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalon_slave_write</name> <role>write</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalon_slave_writedata</name> <role>writedata</role> <direction>Input</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>embeddedsw.configuration.isFlash</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isMemoryDevice</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isNonVolatileStorage</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isPrintableDevice</key> <value>0</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>addressAlignment</key> <value>DYNAMIC</value> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressSpan</key> <value>64</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>associatedReset</key> <value>reset</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>bridgedAddressOffset</key> </entry> <entry> <key>bridgesToMaster</key> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>explicitAddressSpan</key> <value>0</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isFlash</key> <value>false</value> </entry> <entry> <key>isMemoryDevice</key> <value>false</value> </entry> <entry> <key>isNonVolatileStorage</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>0</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>minimumUninterruptedRunLength</key> <value>1</value> </entry> <entry> <key>printableDevice</key> <value>false</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitStates</key> <value>1</value> </entry> <entry> <key>readWaitTime</key> <value>1</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>transparentBridge</key> <value>false</value> </entry> <entry> <key>wellBehavedWaitrequest</key> <value>false</value> </entry> <entry> <key>writeLatency</key> <value>0</value> </entry> <entry> <key>writeWaitStates</key> <value>0</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>system_generic_component_0</className> <version>1.0</version> <displayName>system_generic_component_0</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors/> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos> <entry> <key>avalon_slave</key> <value> <connectionPointName>avalon_slave</connectionPointName> <suppliedSystemInfos> <entry> <key>ADDRESS_MAP</key> </entry> <entry> <key>ADDRESS_WIDTH</key> </entry> <entry> <key>MAX_SLAVE_DATA_WIDTH</key> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> </connPtSystemInfos> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_fifo_bb</hdlLibraryName> <fileSets> <fileSet> <fileSetName>QUARTUS_SYNTH</fileSetName> <fileSetFixedName>fifo_bb</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>SIM_VERILOG</fileSetName> <fileSetFixedName>fifo_bb</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>SIM_VHDL</fileSetName> <fileSetFixedName>fifo_bb</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

fifo_2_custom_logic

altera_avalon_fifo v16.1

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>clk_in</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>wrclock</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>in</name> <type>avalon_streaming</type> <isStart>false</isStart> <ports> <port> <name>avalonst_sink_valid</name> <role>valid</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_sink_data</name> <role>data</role> <direction>Input</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalonst_sink_channel</name> <role>channel</role> <direction>Input</direction> <width>8</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalonst_sink_error</name> <role>error</role> <direction>Input</direction> <width>8</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalonst_sink_startofpacket</name> <role>startofpacket</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_sink_endofpacket</name> <role>endofpacket</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_sink_empty</name> <role>empty</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_sink_ready</name> <role>ready</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clk_in</value> </entry> <entry> <key>associatedReset</key> <value>reset_in</value> </entry> <entry> <key>beatsPerCycle</key> <value>1</value> </entry> <entry> <key>dataBitsPerSymbol</key> <value>8</value> </entry> <entry> <key>emptyWithinPacket</key> <value>false</value> </entry> <entry> <key>errorDescriptor</key> </entry> <entry> <key>firstSymbolInHighOrderBits</key> <value>true</value> </entry> <entry> <key>highOrderSymbolAtMSB</key> <value>false</value> </entry> <entry> <key>maxChannel</key> <value>255</value> </entry> <entry> <key>packetDescription</key> <value></value> </entry> <entry> <key>readyLatency</key> <value>1</value> </entry> <entry> <key>symbolsPerBeat</key> <value>2</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>out</name> <type>avalon_streaming</type> <isStart>true</isStart> <ports> <port> <name>avalonst_source_valid</name> <role>valid</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_source_data</name> <role>data</role> <direction>Output</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalonst_source_channel</name> <role>channel</role> <direction>Output</direction> <width>8</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalonst_source_error</name> <role>error</role> <direction>Output</direction> <width>8</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avalonst_source_startofpacket</name> <role>startofpacket</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_source_endofpacket</name> <role>endofpacket</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_source_empty</name> <role>empty</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avalonst_source_ready</name> <role>ready</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clk_in</value> </entry> <entry> <key>associatedReset</key> <value>reset_in</value> </entry> <entry> <key>beatsPerCycle</key> <value>1</value> </entry> <entry> <key>dataBitsPerSymbol</key> <value>8</value> </entry> <entry> <key>emptyWithinPacket</key> <value>false</value> </entry> <entry> <key>errorDescriptor</key> </entry> <entry> <key>firstSymbolInHighOrderBits</key> <value>true</value> </entry> <entry> <key>highOrderSymbolAtMSB</key> <value>false</value> </entry> <entry> <key>maxChannel</key> <value>255</value> </entry> <entry> <key>packetDescription</key> <value></value> </entry> <entry> <key>readyLatency</key> <value>1</value> </entry> <entry> <key>symbolsPerBeat</key> <value>2</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset_in</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clk_in</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>altera_avalon_fifo</className> <version>16.1</version> <displayName>Avalon FIFO Memory</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>deviceFamilyString</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE_FAMILY</systemInfotype> </descriptor> </descriptors> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos/> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_fifo_0</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_fifo_0</fileSetName> <fileSetFixedName>system_fifo_0</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_fifo_0</fileSetName> <fileSetFixedName>system_fifo_0</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_fifo_0</fileSetName> <fileSetFixedName>system_fifo_0</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView ip/system/system_fifo_0.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap> <entry> <key>embeddedsw.CMacro.AVALONMM_AVALONMM_DATA_WIDTH</key> <value>32</value> </entry> <entry> <key>embeddedsw.CMacro.AVALONMM_AVALONST_DATA_WIDTH</key> <value>32</value> </entry> <entry> <key>embeddedsw.CMacro.BITS_PER_SYMBOL</key> <value>8</value> </entry> <entry> <key>embeddedsw.CMacro.CHANNEL_WIDTH</key> <value>8</value> </entry> <entry> <key>embeddedsw.CMacro.ERROR_WIDTH</key> <value>8</value> </entry> <entry> <key>embeddedsw.CMacro.FIFO_DEPTH</key> <value>32</value> </entry> <entry> <key>embeddedsw.CMacro.SINGLE_CLOCK_MODE</key> <value>1</value> </entry> <entry> <key>embeddedsw.CMacro.SYMBOLS_PER_BEAT</key> <value>2</value> </entry> <entry> <key>embeddedsw.CMacro.USE_AVALONMM_READ_SLAVE</key> <value>0</value> </entry> <entry> <key>embeddedsw.CMacro.USE_AVALONMM_WRITE_SLAVE</key> <value>0</value> </entry> <entry> <key>embeddedsw.CMacro.USE_AVALONST_SINK</key> <value>1</value> </entry> <entry> <key>embeddedsw.CMacro.USE_AVALONST_SOURCE</key> <value>1</value> </entry> <entry> <key>embeddedsw.CMacro.USE_BACKPRESSURE</key> <value>1</value> </entry> <entry> <key>embeddedsw.CMacro.USE_IRQ</key> <value>0</value> </entry> <entry> <key>embeddedsw.CMacro.USE_PACKET</key> <value>1</value> </entry> <entry> <key>embeddedsw.CMacro.USE_READ_CONTROL</key> <value>0</value> </entry> <entry> <key>embeddedsw.CMacro.USE_REGISTER</key> <value>0</value> </entry> <entry> <key>embeddedsw.CMacro.USE_WRITE_CONTROL</key> <value>0</value> </entry> </assignmentValueMap> </assignmentDefinition> deviceFamilyString ARRIA10 AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG deviceFamily Arria 10 generateLegacySim false

  

Software Assignments AVALONMM_AVALONMM_DATA_WIDTH 32 AVALONMM_AVALONST_DATA_WIDTH 32 BITS_PER_SYMBOL 8 CHANNEL_WIDTH 8 ERROR_WIDTH 8 FIFO_DEPTH 32 SINGLE_CLOCK_MODE 1 SYMBOLS_PER_BEAT 2 USE_AVALONMM_READ_SLAVE 0 USE_AVALONMM_WRITE_SLAVE 0 USE_AVALONST_SINK 1 USE_AVALONST_SOURCE 1 USE_BACKPRESSURE 1 USE_IRQ 0 USE_PACKET 1 USE_READ_CONTROL 0 USE_REGISTER 0 USE_WRITE_CONTROL 0

---

iopll_0

altera_iopll v16.1

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>locked</name> <type>reset</type> <isStart>true</isStart> <ports> <port> <name>locked</name> <role>reset_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedDirectReset</key> </entry> <entry> <key>associatedResetSinks</key> <value></value> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>outclk0</name> <type>clock</type> <isStart>true</isStart> <ports> <port> <name>outclk_0</name> <role>clk</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>ui.blockdiagram.direction</key> <value>output</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedDirectClock</key> </entry> <entry> <key>clockRate</key> <value>75000000</value> </entry> <entry> <key>clockRateKnown</key> <value>true</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>refclk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>refclk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>ui.blockdiagram.direction</key> <value>input</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>50000000</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>rst</name> <role>reset</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>ui.blockdiagram.direction</key> <value>input</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>altera_iopll</className> <version>16.1</version> <displayName>Altera IOPLL</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>system_info_device_component</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>system_info_device_family</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE_FAMILY</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>system_info_device_speed_grade</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>system_part_trait_speed_grade</parameterName> <parameterType>java.lang.String</parameterType> <systemInfoArgs>DEVICE_SPEEDGRADE</systemInfoArgs> <systemInfotype>PART_TRAIT</systemInfotype> </descriptor> </descriptors> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos> <entry> <key>outclk0</key> <value> <connectionPointName>outclk0</connectionPointName> <suppliedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>75000000</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> </connPtSystemInfos> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_iopll_0</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_iopll_0</fileSetName> <fileSetFixedName>system_iopll_0</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_iopll_0</fileSetName> <fileSetFixedName>system_iopll_0</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_iopll_0</fileSetName> <fileSetFixedName>system_iopll_0</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView ip\system\system_iopll_0.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap> <entry> <key>embeddedsw.dts.compatible</key> <value>altr,pll</value> </entry> <entry> <key>embeddedsw.dts.group</key> <value>clock</value> </entry> <entry> <key>embeddedsw.dts.vendor</key> <value>altr</value> </entry> </assignmentValueMap> </assignmentDefinition> system_info_device_component 10AX115R4F40I3SG system_info_device_family ARRIA10 system_info_device_speed_grade 3 system_part_trait_speed_grade 3 AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG deviceFamily Arria 10 generateLegacySim false

  

Software Assignments (none)

---

slave_burst_0

Avalon_Slave_Burst v1.0

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>clock</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>reset</name> <role>reset</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>s0</name> <type>avalon</type> <isStart>false</isStart> <ports> <port> <name>avs_s0_address</name> <role>address</role> <direction>Input</direction> <width>16</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avs_s0_read</name> <role>read</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avs_s0_readdata</name> <role>readdata</role> <direction>Output</direction> <width>64</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avs_s0_write</name> <role>write</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avs_s0_writedata</name> <role>writedata</role> <direction>Input</direction> <width>64</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avs_s0_waitrequest</name> <role>waitrequest</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avs_s0_burstcount</name> <role>burstcount</role> <direction>Input</direction> <width>4</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>avs_s0_begintransfer</name> <role>begintransfer</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avs_s0_readdatavalid</name> <role>readdatavalid</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>avs_s0_beginbursttransfer</name> <role>beginbursttransfer</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>embeddedsw.configuration.isFlash</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isMemoryDevice</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isNonVolatileStorage</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isPrintableDevice</key> <value>0</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>addressAlignment</key> <value>DYNAMIC</value> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressSpan</key> <value>524288</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>associatedReset</key> <value>reset</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>bridgedAddressOffset</key> <value>0</value> </entry> <entry> <key>bridgesToMaster</key> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>true</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>explicitAddressSpan</key> <value>0</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isFlash</key> <value>false</value> </entry> <entry> <key>isMemoryDevice</key> <value>false</value> </entry> <entry> <key>isNonVolatileStorage</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>1</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>minimumUninterruptedRunLength</key> <value>1</value> </entry> <entry> <key>printableDevice</key> <value>false</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitStates</key> <value>1</value> </entry> <entry> <key>readWaitTime</key> <value>1</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>transparentBridge</key> <value>false</value> </entry> <entry> <key>wellBehavedWaitrequest</key> <value>false</value> </entry> <entry> <key>writeLatency</key> <value>0</value> </entry> <entry> <key>writeWaitStates</key> <value>0</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>Avalon_Slave_Burst</className> <version>1.0</version> <displayName>avalon_slave_burst</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors/> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos> <entry> <key>s0</key> <value> <connectionPointName>s0</connectionPointName> <suppliedSystemInfos> <entry> <key>ADDRESS_MAP</key> <value>&lt;address-map&gt;&lt;slave name='s0' start='0x0' end='0x80000' datawidth='64' /&gt;&lt;/address-map&gt;</value> </entry> <entry> <key>ADDRESS_WIDTH</key> <value>19</value> </entry> <entry> <key>MAX_SLAVE_DATA_WIDTH</key> <value>64</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> </connPtSystemInfos> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_Avalon_Slave_Burst_0</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_Avalon_Slave_Burst_0</fileSetName> <fileSetFixedName>system_Avalon_Slave_Burst_0</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_Avalon_Slave_Burst_0</fileSetName> <fileSetFixedName>system_Avalon_Slave_Burst_0</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_Avalon_Slave_Burst_0</fileSetName> <fileSetFixedName>system_Avalon_Slave_Burst_0</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView ip/system/system_Avalon_Slave_Burst_0.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG deviceFamily Arria 10 generateLegacySim false

  

Software Assignments (none)

---

state_machine

avalon_state_machine_master v2.0

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>avalon_master</name> <type>avalon</type> <isStart>true</isStart> <ports> <port> <name>am_waitreq</name> <role>waitrequest</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>am_data_in</name> <role>readdata</role> <direction>Input</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>am_addr</name> <role>address</role> <direction>Output</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>am_data_out</name> <role>writedata</role> <direction>Output</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>am_rd</name> <role>read</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>am_wr</name> <role>write</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>adaptsTo</key> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressUnits</key> <value>SYMBOLS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>associatedReset</key> <value>reset</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>true</value> </entry> <entry> <key>dBSBigEndian</key> <value>false</value> </entry> <entry> <key>doStreamReads</key> <value>false</value> </entry> <entry> <key>doStreamWrites</key> <value>false</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isAsynchronous</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isReadable</key> <value>false</value> </entry> <entry> <key>isWriteable</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maxAddressWidth</key> <value>32</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>0</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitTime</key> <value>1</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>clock</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>rst</name> <role>reset</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clock</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>avalon_state_machine_master</className> <version>2.0</version> <displayName>Avalon State Machine Master</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors/> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos/> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_state_machine</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_state_machine</fileSetName> <fileSetFixedName>system_state_machine</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_state_machine</fileSetName> <fileSetFixedName>system_state_machine</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_state_machine</fileSetName> <fileSetFixedName>system_state_machine</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView ip\system\system_state_machine.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG deviceFamily Arria 10 generateLegacySim false

  

Software Assignments (none)

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system_reset_controller_0

altera_reset_controller v16.1

Parameters componentDefinition <componentDefinition> <boundary> <interfaces> <interface> <name>clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset_in0</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>reset_in0</name> <role>reset</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset_in1</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>reset_in1</name> <role>reset</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset_out</name> <type>reset</type> <isStart>true</isStart> <ports> <port> <name>reset_out</name> <role>reset</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clk</value> </entry> <entry> <key>associatedDirectReset</key> </entry> <entry> <key>associatedResetSinks</key> <value>reset_in0,reset_in1</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>altera_reset_controller</className> <version>16.1</version> <displayName>Merlin Reset Controller</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors/> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos/> </systemInfos> </componentDefinition> generationInfoDefinition <generationInfoDefinition> <hdlLibraryName>system_reset_controller_0</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_reset_controller_0</fileSetName> <fileSetFixedName>system_reset_controller_0</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_reset_controller_0</fileSetName> <fileSetFixedName>system_reset_controller_0</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_reset_controller_0</fileSetName> <fileSetFixedName>system_reset_controller_0</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition> logicalView ip/system/system_reset_controller_0.ip moduleAssignmentDefinition <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition> AUTO_DEVICE_FAMILY ARRIA10 AUTO_DEVICE 10AX115R4F40I3SG deviceFamily Arria 10 generateLegacySim false

  

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