// This file is dynamically generated and is for information purposes only.
// It is not used during compilation or simulation.

SEQ_GPT
   0x3800   SEQ_GPT_GLOBAL_PAR_VER        : 1          0x00000001
   0x3804   SEQ_GPT_NIOS_C_VER            : 1          0x00000001
   0x3808   SEQ_GPT_COLUMN_ID             : 1          0x00000001
   0x380C   SEQ_GPT_NUM_IOPACKS           : 11         0x0000000B
   0x3810   SEQ_GPT_NIOS_CLK_FREQ_KHZ     : 1590000    0x001842F0
   0x3814   SEQ_GPT_PARAM_TABLE_SIZE      : 360        0x00000168
   0x3818   SEQ_GPT_INTERFACE_PAR_PTRS    
   0x3818      static_array_elem [0]      : 68         0x00000044
   0x381C      static_array_elem [1]      : 0          0x00000000
   0x3820      static_array_elem [2]      : 0          0x00000000
   0x3824      static_array_elem [3]      : 0          0x00000000
   0x3828      static_array_elem [4]      : 0          0x00000000
   0x382C      static_array_elem [5]      : 0          0x00000000
   0x3830      static_array_elem [6]      : 0          0x00000000
   0x3834      static_array_elem [7]      : 0          0x00000000
   0x3838      static_array_elem [8]      : 0          0x00000000
   0x383C      static_array_elem [9]      : 0          0x00000000
   0x3840      static_array_elem [10]     : 0          0x00000000
SEQ_PT
   0x3844   SEQ_PT_IP_VER                 : 16448      0x4040    
   0x3846   SEQ_PT_INTERFACE_PAR_VER      : 2          0x0002    
   0x3848   SEQ_PT_DEBUG_DATA_PTR         : 0          0x0000    
   0x384A   SEQ_PT_USER_COMMAND_PTR       : 0          0x0000    
   0x384C   SEQ_PT_MEMORY_TYPE            : 1          0x01      
   0x384D   SEQ_PT_DIMM_TYPE              : 0          0x00      
   0x384E   SEQ_PT_CONTROLLER_TYPE        : 0          0x00      
   0x384F   SEQ_PT_RESERVED               : 0          0x00      
   0x3850   SEQ_PT_AFI_CLK_FREQ_KHZ       : 400000     0x00061A80
   0x3854   SEQ_PT_BURST_LEN              : 8          0x08      
   0x3855   SEQ_PT_READ_LATENCY           : 18         0x12      
   0x3856   SEQ_PT_WRITE_LATENCY          : 12         0x0C      
   0x3857   SEQ_PT_NUM_RANKS              : 1          0x01      
   0x3858   SEQ_PT_NUM_DIMMS              : 1          0x01      
   0x3859   SEQ_PT_NUM_DQS_WR             : 9          0x09      
   0x385A   SEQ_PT_NUM_DQS_RD             : 9          0x09      
   0x385B   SEQ_PT_NUM_DQ                 : 72         0x48      
   0x385C   SEQ_PT_NUM_DM                 : 9          0x09      
   0x385D   SEQ_PT_ADDR_WIDTH             : 17         0x11      
   0x385E   SEQ_PT_BANK_WIDTH             : 2          0x02      
   0x385F   SEQ_PT_CS_WIDTH               : 1          0x01      
   0x3860   SEQ_PT_CKE_WIDTH              : 1          0x01      
   0x3861   SEQ_PT_ODT_WIDTH              : 1          0x01      
   0x3862   SEQ_PT_C_WIDTH                : 0          0x00      
   0x3863   SEQ_PT_BANK_GROUP_WIDTH       : 2          0x02      
   0x3864   SEQ_PT_ADDR_MIRROR            : 0          0x00      
   0x3865   SEQ_PT_CK_WIDTH               : 1          0x01      
   0x3866   SEQ_PT_CAL_DATA_SIZE          : 20         0x14      
   0x3867   SEQ_PT_NUM_LRDIMM_CFG         : 0          0x00      
   0x3868   SEQ_PT_NUM_AC_ROM_ENUMS       : 52         0x34      
   0x3869   SEQ_PT_NUM_CENTERS            : 3          0x03      
   0x386A   SEQ_PT_NUM_CA_LANES           : 3          0x03      
   0x386B   SEQ_PT_NUM_DATA_LANES         : 9          0x09      
   0x386C   SEQ_PT_ODT_TABLE_LO           : 4          0x00000004
   0x3870   SEQ_PT_ODT_TABLE_HI           : 0          0x00000000
   0x3874   SEQ_PT_CAL_CONFIG             : 119595137  0x0720E081
   0x3878   SEQ_PT_DBG_CONFIG             : 0          0x0000    
   0x387A   SEQ_PT_CAL_DATA_PTR           : 144        0x0090    
   0x0090      STARTING_VREFIN            : 24         0x00000018 24
   0x0094      CAL_TREFI                  : 7800       0x00001E78 7800
   0x0098      CAL_TRFC                   : 260        0x00000104 260
   0x009C      CAL_ADDR0                  : 0          0x00000000 0
   0x00A0      CAL_ADDR1                  : 8          0x00000008 8
   0x387C   SEQ_PT_DBG_SKIP_RANKS         : 0          0x00000000
   0x3880   SEQ_PT_DBG_SKIP_GROUPS        : 0          0x00000000
   0x3884   SEQ_PT_DBG_SKIP_STEPS         : 62720      0x0000F500
   0x3888   SEQ_PT_NUM_MR                 : 7          0x07      
   0x3889   SEQ_PT_NUM_DIMM_MR            : 7          0x07      
   0x388A   SEQ_PT_TILE_ID_PTR            : 164        0x00A4    
   0x00A4      TILE [0]                   : 12         0x0C       (T) = (1)
   0x00A5      TILE [1]                   : 4          0x04       (T) = (0)
   0x00A6      TILE [2]                   : 20         0x14       (T) = (2)
   0x00A7      AC_LANE [0]                : 8          0x08       (T L) = (1 0)
   0x00A8      AC_LANE [1]                : 9          0x09       (T L) = (1 1)
   0x00A9      AC_LANE [2]                : 10         0x0A       (T L) = (1 2)
   0x00AA      DATA_LANE [0]              : 11         0x0B       (T L) = (1 3)
   0x00AB      DATA_LANE [1]              : 0          0x00       (T L) = (0 0)
   0x00AC      DATA_LANE [2]              : 1          0x01       (T L) = (0 1)
   0x00AD      DATA_LANE [3]              : 2          0x02       (T L) = (0 2)
   0x00AE      DATA_LANE [4]              : 3          0x03       (T L) = (0 3)
   0x00AF      DATA_LANE [5]              : 16         0x10       (T L) = (2 0)
   0x00B0      DATA_LANE [6]              : 17         0x11       (T L) = (2 1)
   0x00B1      DATA_LANE [7]              : 18         0x12       (T L) = (2 2)
   0x00B2      DATA_LANE [8]              : 19         0x13       (T L) = (2 3)
   0x00B3      ALIGN_PAD                  : 0          0x00       
   0x388C   SEQ_PT_PIN_ADDR_PTR           : 180        0x00B4    
   0x00B4      PORT_MEM_CKE [0]           : 6          0x06       (T L P) = (1 0 6 )  AC_LANE [0]
   0x00B5                                 : 0          0x00       UNUSED_AC_PORT
   0x00B6                                 : 0          0x00       UNUSED_AC_PORT
   0x00B7                                 : 0          0x00       UNUSED_AC_PORT
   0x00B8      PORT_MEM_ODT [0]           : 4          0x04       (T L P) = (1 0 4 )  AC_LANE [0]
   0x00B9                                 : 0          0x00       UNUSED_AC_PORT
   0x00BA                                 : 0          0x00       UNUSED_AC_PORT
   0x00BB                                 : 0          0x00       UNUSED_AC_PORT
   0x00BC      PORT_MEM_RESET_N [0]       : 1          0x01       (T L P) = (1 0 1 )  AC_LANE [0]
   0x00BD      PORT_MEM_ACT_N [0]         : 3          0x03       (T L P) = (1 0 3 )  AC_LANE [0]
   0x00BE      PORT_MEM_CS_N [0]          : 2          0x02       (T L P) = (1 0 2 )  AC_LANE [0]
   0x00BF                                 : 0          0x00       UNUSED_AC_PORT
   0x00C0                                 : 0          0x00       UNUSED_AC_PORT
   0x00C1                                 : 0          0x00       UNUSED_AC_PORT
   0x00C2                                 : 0          0x00       UNUSED_AC_PORT
   0x00C3                                 : 0          0x00       UNUSED_AC_PORT
   0x00C4                                 : 0          0x00       UNUSED_AC_PORT
   0x00C5      PORT_MEM_BA [0]            : 41         0x29       (T L P) = (1 2 9 )  AC_LANE [2]
   0x00C6      PORT_MEM_BA [1]            : 42         0x2A       (T L P) = (1 2 10)  AC_LANE [2]
   0x00C7      PORT_MEM_BG [0]            : 43         0x2B       (T L P) = (1 2 11)  AC_LANE [2]
   0x00C8      PORT_MEM_BG [1]            : 0          0x00       (T L P) = (1 0 0 )  AC_LANE [0]
   0x00C9      PORT_MEM_A [0]             : 16         0x10       (T L P) = (1 1 0 )  AC_LANE [1]
   0x00CA      PORT_MEM_A [1]             : 17         0x11       (T L P) = (1 1 1 )  AC_LANE [1]
   0x00CB      PORT_MEM_A [2]             : 18         0x12       (T L P) = (1 1 2 )  AC_LANE [1]
   0x00CC      PORT_MEM_A [3]             : 19         0x13       (T L P) = (1 1 3 )  AC_LANE [1]
   0x00CD      PORT_MEM_A [4]             : 20         0x14       (T L P) = (1 1 4 )  AC_LANE [1]
   0x00CE      PORT_MEM_A [5]             : 21         0x15       (T L P) = (1 1 5 )  AC_LANE [1]
   0x00CF      PORT_MEM_A [6]             : 22         0x16       (T L P) = (1 1 6 )  AC_LANE [1]
   0x00D0      PORT_MEM_A [7]             : 23         0x17       (T L P) = (1 1 7 )  AC_LANE [1]
   0x00D1      PORT_MEM_A [8]             : 24         0x18       (T L P) = (1 1 8 )  AC_LANE [1]
   0x00D2      PORT_MEM_A [9]             : 25         0x19       (T L P) = (1 1 9 )  AC_LANE [1]
   0x00D3      PORT_MEM_A [10]            : 26         0x1A       (T L P) = (1 1 10)  AC_LANE [1]
   0x00D4      PORT_MEM_A [11]            : 27         0x1B       (T L P) = (1 1 11)  AC_LANE [1]
   0x00D5      PORT_MEM_A [12]            : 35         0x23       (T L P) = (1 2 3 )  AC_LANE [2]
   0x00D6      PORT_MEM_A [13]            : 36         0x24       (T L P) = (1 2 4 )  AC_LANE [2]
   0x00D7      PORT_MEM_A [14]            : 37         0x25       (T L P) = (1 2 5 )  AC_LANE [2]
   0x00D8      PORT_MEM_A [15]            : 38         0x26       (T L P) = (1 2 6 )  AC_LANE [2]
   0x00D9      PORT_MEM_A [16]            : 39         0x27       (T L P) = (1 2 7 )  AC_LANE [2]
   0x00DA                                 : 0          0x00       UNUSED_AC_PORT
   0x00DB                                 : 0          0x00       UNUSED_AC_PORT
   0x00DC                                 : 0          0x00       UNUSED_AC_PORT
   0x00DD      PORT_MEM_PAR [0]           : 11         0x0B       (T L P) = (1 0 11)  AC_LANE [0]
   0x00DE      PORT_MEM_ALERT_N [0]       : 15         0x0F       (T L P) = (0 0 0 )  DATA_LANE [1]
   0x00DF                                 : 1          0x01       
   0x00E0                                 : 0          0x00       UNUSED_AC_PORT
   0x00E1      PORT_MEM_CK [0]            : 8          0x08       (T L P) = (1 0 8 )  AC_LANE [0]
   0x00E2      PORT_MEM_CK_N [0]          : 9          0x09       (T L P) = (1 0 9 )  AC_LANE [0]
   0x00E3                                 : 0          0x00       UNUSED_AC_PORT
   0x00E4                                 : 0          0x00       UNUSED_AC_PORT
   0x00E5                                 : 0          0x00       UNUSED_AC_PORT
   0x00E6                                 : 0          0x00       UNUSED_AC_PORT
   0x00E7                                 : 0          0x00       UNUSED_AC_PORT
   0x00E8                                 : 0          0x00       UNUSED_AC_PORT
   0x00E9      PORT_MEM_DQS [0]           : 20         0x14       (T L P) = (0 0 4 )  DATA_LANE [1]
   0x00EA      PORT_MEM_DQS [1]           : 36         0x24       (T L P) = (0 1 4 )  DATA_LANE [2]
   0x00EB      PORT_MEM_DQS [2]           : 52         0x34       (T L P) = (0 2 4 )  DATA_LANE [3]
   0x00EC      PORT_MEM_DQS [3]           : 68         0x44       (T L P) = (0 3 4 )  DATA_LANE [4]
   0x00ED      PORT_MEM_DQS [4]           : 4          0x04       (T L P) = (1 3 4 )  DATA_LANE [0]
   0x00EE      PORT_MEM_DQS [5]           : 84         0x54       (T L P) = (2 0 4 )  DATA_LANE [5]
   0x00EF      PORT_MEM_DQS [6]           : 100        0x64       (T L P) = (2 1 4 )  DATA_LANE [6]
   0x00F0      PORT_MEM_DQS [7]           : 116        0x74       (T L P) = (2 2 4 )  DATA_LANE [7]
   0x00F1      PORT_MEM_DQS [8]           : 132        0x84       (T L P) = (2 3 4 )  DATA_LANE [8]
   0x00F2      PORT_MEM_DQS_N [0]         : 21         0x15       (T L P) = (0 0 5 )  DATA_LANE [1]
   0x00F3      PORT_MEM_DQS_N [1]         : 37         0x25       (T L P) = (0 1 5 )  DATA_LANE [2]
   0x00F4      PORT_MEM_DQS_N [2]         : 53         0x35       (T L P) = (0 2 5 )  DATA_LANE [3]
   0x00F5      PORT_MEM_DQS_N [3]         : 69         0x45       (T L P) = (0 3 5 )  DATA_LANE [4]
   0x00F6      PORT_MEM_DQS_N [4]         : 5          0x05       (T L P) = (1 3 5 )  DATA_LANE [0]
   0x00F7      PORT_MEM_DQS_N [5]         : 85         0x55       (T L P) = (2 0 5 )  DATA_LANE [5]
   0x00F8      PORT_MEM_DQS_N [6]         : 101        0x65       (T L P) = (2 1 5 )  DATA_LANE [6]
   0x00F9      PORT_MEM_DQS_N [7]         : 117        0x75       (T L P) = (2 2 5 )  DATA_LANE [7]
   0x00FA      PORT_MEM_DQS_N [8]         : 133        0x85       (T L P) = (2 3 5 )  DATA_LANE [8]
   0x00FB      PORT_MEM_DBI_N [0]         : 27         0x1B       (T L P) = (0 0 11)  DATA_LANE [1]
   0x00FC      PORT_MEM_DBI_N [1]         : 43         0x2B       (T L P) = (0 1 11)  DATA_LANE [2]
   0x00FD      PORT_MEM_DBI_N [2]         : 59         0x3B       (T L P) = (0 2 11)  DATA_LANE [3]
   0x00FE      PORT_MEM_DBI_N [3]         : 75         0x4B       (T L P) = (0 3 11)  DATA_LANE [4]
   0x00FF      PORT_MEM_DBI_N [4]         : 11         0x0B       (T L P) = (1 3 11)  DATA_LANE [0]
   0x0100      PORT_MEM_DBI_N [5]         : 91         0x5B       (T L P) = (2 0 11)  DATA_LANE [5]
   0x0101      PORT_MEM_DBI_N [6]         : 107        0x6B       (T L P) = (2 1 11)  DATA_LANE [6]
   0x0102      PORT_MEM_DBI_N [7]         : 123        0x7B       (T L P) = (2 2 11)  DATA_LANE [7]
   0x0103      PORT_MEM_DBI_N [8]         : 139        0x8B       (T L P) = (2 3 11)  DATA_LANE [8]
   0x0104      PORT_MEM_DQ [0]            : 17         0x11       (T L P) = (0 0 1 )  DATA_LANE [1]
   0x0105      PORT_MEM_DQ [1]            : 18         0x12       (T L P) = (0 0 2 )  DATA_LANE [1]
   0x0106      PORT_MEM_DQ [2]            : 19         0x13       (T L P) = (0 0 3 )  DATA_LANE [1]
   0x0107      PORT_MEM_DQ [3]            : 22         0x16       (T L P) = (0 0 6 )  DATA_LANE [1]
   0x0108      PORT_MEM_DQ [4]            : 23         0x17       (T L P) = (0 0 7 )  DATA_LANE [1]
   0x0109      PORT_MEM_DQ [5]            : 24         0x18       (T L P) = (0 0 8 )  DATA_LANE [1]
   0x010A      PORT_MEM_DQ [6]            : 25         0x19       (T L P) = (0 0 9 )  DATA_LANE [1]
   0x010B      PORT_MEM_DQ [7]            : 26         0x1A       (T L P) = (0 0 10)  DATA_LANE [1]
   0x010C      PORT_MEM_DQ [8]            : 33         0x21       (T L P) = (0 1 1 )  DATA_LANE [2]
   0x010D      PORT_MEM_DQ [9]            : 34         0x22       (T L P) = (0 1 2 )  DATA_LANE [2]
   0x010E      PORT_MEM_DQ [10]           : 35         0x23       (T L P) = (0 1 3 )  DATA_LANE [2]
   0x010F      PORT_MEM_DQ [11]           : 38         0x26       (T L P) = (0 1 6 )  DATA_LANE [2]
   0x0110      PORT_MEM_DQ [12]           : 39         0x27       (T L P) = (0 1 7 )  DATA_LANE [2]
   0x0111      PORT_MEM_DQ [13]           : 40         0x28       (T L P) = (0 1 8 )  DATA_LANE [2]
   0x0112      PORT_MEM_DQ [14]           : 41         0x29       (T L P) = (0 1 9 )  DATA_LANE [2]
   0x0113      PORT_MEM_DQ [15]           : 42         0x2A       (T L P) = (0 1 10)  DATA_LANE [2]
   0x0114      PORT_MEM_DQ [16]           : 49         0x31       (T L P) = (0 2 1 )  DATA_LANE [3]
   0x0115      PORT_MEM_DQ [17]           : 50         0x32       (T L P) = (0 2 2 )  DATA_LANE [3]
   0x0116      PORT_MEM_DQ [18]           : 51         0x33       (T L P) = (0 2 3 )  DATA_LANE [3]
   0x0117      PORT_MEM_DQ [19]           : 54         0x36       (T L P) = (0 2 6 )  DATA_LANE [3]
   0x0118      PORT_MEM_DQ [20]           : 55         0x37       (T L P) = (0 2 7 )  DATA_LANE [3]
   0x0119      PORT_MEM_DQ [21]           : 56         0x38       (T L P) = (0 2 8 )  DATA_LANE [3]
   0x011A      PORT_MEM_DQ [22]           : 57         0x39       (T L P) = (0 2 9 )  DATA_LANE [3]
   0x011B      PORT_MEM_DQ [23]           : 58         0x3A       (T L P) = (0 2 10)  DATA_LANE [3]
   0x011C      PORT_MEM_DQ [24]           : 65         0x41       (T L P) = (0 3 1 )  DATA_LANE [4]
   0x011D      PORT_MEM_DQ [25]           : 66         0x42       (T L P) = (0 3 2 )  DATA_LANE [4]
   0x011E      PORT_MEM_DQ [26]           : 67         0x43       (T L P) = (0 3 3 )  DATA_LANE [4]
   0x011F      PORT_MEM_DQ [27]           : 70         0x46       (T L P) = (0 3 6 )  DATA_LANE [4]
   0x0120      PORT_MEM_DQ [28]           : 71         0x47       (T L P) = (0 3 7 )  DATA_LANE [4]
   0x0121      PORT_MEM_DQ [29]           : 72         0x48       (T L P) = (0 3 8 )  DATA_LANE [4]
   0x0122      PORT_MEM_DQ [30]           : 73         0x49       (T L P) = (0 3 9 )  DATA_LANE [4]
   0x0123      PORT_MEM_DQ [31]           : 74         0x4A       (T L P) = (0 3 10)  DATA_LANE [4]
   0x0124      PORT_MEM_DQ [32]           : 1          0x01       (T L P) = (1 3 1 )  DATA_LANE [0]
   0x0125      PORT_MEM_DQ [33]           : 2          0x02       (T L P) = (1 3 2 )  DATA_LANE [0]
   0x0126      PORT_MEM_DQ [34]           : 3          0x03       (T L P) = (1 3 3 )  DATA_LANE [0]
   0x0127      PORT_MEM_DQ [35]           : 6          0x06       (T L P) = (1 3 6 )  DATA_LANE [0]
   0x0128      PORT_MEM_DQ [36]           : 7          0x07       (T L P) = (1 3 7 )  DATA_LANE [0]
   0x0129      PORT_MEM_DQ [37]           : 8          0x08       (T L P) = (1 3 8 )  DATA_LANE [0]
   0x012A      PORT_MEM_DQ [38]           : 9          0x09       (T L P) = (1 3 9 )  DATA_LANE [0]
   0x012B      PORT_MEM_DQ [39]           : 10         0x0A       (T L P) = (1 3 10)  DATA_LANE [0]
   0x012C      PORT_MEM_DQ [40]           : 81         0x51       (T L P) = (2 0 1 )  DATA_LANE [5]
   0x012D      PORT_MEM_DQ [41]           : 82         0x52       (T L P) = (2 0 2 )  DATA_LANE [5]
   0x012E      PORT_MEM_DQ [42]           : 83         0x53       (T L P) = (2 0 3 )  DATA_LANE [5]
   0x012F      PORT_MEM_DQ [43]           : 86         0x56       (T L P) = (2 0 6 )  DATA_LANE [5]
   0x0130      PORT_MEM_DQ [44]           : 87         0x57       (T L P) = (2 0 7 )  DATA_LANE [5]
   0x0131      PORT_MEM_DQ [45]           : 88         0x58       (T L P) = (2 0 8 )  DATA_LANE [5]
   0x0132      PORT_MEM_DQ [46]           : 89         0x59       (T L P) = (2 0 9 )  DATA_LANE [5]
   0x0133      PORT_MEM_DQ [47]           : 90         0x5A       (T L P) = (2 0 10)  DATA_LANE [5]
   0x0134      PORT_MEM_DQ [48]           : 97         0x61       (T L P) = (2 1 1 )  DATA_LANE [6]
   0x0135      PORT_MEM_DQ [49]           : 98         0x62       (T L P) = (2 1 2 )  DATA_LANE [6]
   0x0136      PORT_MEM_DQ [50]           : 99         0x63       (T L P) = (2 1 3 )  DATA_LANE [6]
   0x0137      PORT_MEM_DQ [51]           : 102        0x66       (T L P) = (2 1 6 )  DATA_LANE [6]
   0x0138      PORT_MEM_DQ [52]           : 103        0x67       (T L P) = (2 1 7 )  DATA_LANE [6]
   0x0139      PORT_MEM_DQ [53]           : 104        0x68       (T L P) = (2 1 8 )  DATA_LANE [6]
   0x013A      PORT_MEM_DQ [54]           : 105        0x69       (T L P) = (2 1 9 )  DATA_LANE [6]
   0x013B      PORT_MEM_DQ [55]           : 106        0x6A       (T L P) = (2 1 10)  DATA_LANE [6]
   0x013C      PORT_MEM_DQ [56]           : 113        0x71       (T L P) = (2 2 1 )  DATA_LANE [7]
   0x013D      PORT_MEM_DQ [57]           : 114        0x72       (T L P) = (2 2 2 )  DATA_LANE [7]
   0x013E      PORT_MEM_DQ [58]           : 115        0x73       (T L P) = (2 2 3 )  DATA_LANE [7]
   0x013F      PORT_MEM_DQ [59]           : 118        0x76       (T L P) = (2 2 6 )  DATA_LANE [7]
   0x0140      PORT_MEM_DQ [60]           : 119        0x77       (T L P) = (2 2 7 )  DATA_LANE [7]
   0x0141      PORT_MEM_DQ [61]           : 120        0x78       (T L P) = (2 2 8 )  DATA_LANE [7]
   0x0142      PORT_MEM_DQ [62]           : 121        0x79       (T L P) = (2 2 9 )  DATA_LANE [7]
   0x0143      PORT_MEM_DQ [63]           : 122        0x7A       (T L P) = (2 2 10)  DATA_LANE [7]
   0x0144      PORT_MEM_DQ [64]           : 129        0x81       (T L P) = (2 3 1 )  DATA_LANE [8]
   0x0145      PORT_MEM_DQ [65]           : 130        0x82       (T L P) = (2 3 2 )  DATA_LANE [8]
   0x0146      PORT_MEM_DQ [66]           : 131        0x83       (T L P) = (2 3 3 )  DATA_LANE [8]
   0x0147      PORT_MEM_DQ [67]           : 134        0x86       (T L P) = (2 3 6 )  DATA_LANE [8]
   0x0148      PORT_MEM_DQ [68]           : 135        0x87       (T L P) = (2 3 7 )  DATA_LANE [8]
   0x0149      PORT_MEM_DQ [69]           : 136        0x88       (T L P) = (2 3 8 )  DATA_LANE [8]
   0x014A      PORT_MEM_DQ [70]           : 137        0x89       (T L P) = (2 3 9 )  DATA_LANE [8]
   0x014B      PORT_MEM_DQ [71]           : 138        0x8A       (T L P) = (2 3 10)  DATA_LANE [8]
   0x388E   SEQ_PT_MR_PTR                 : 332        0x014C    
   0x014C      MR0                        : 576        0x00000240 00000000001001000000
   0x0150      MR1                        : 65793      0x00010101 00010000000100000001
   0x0154      MR2                        : 131096     0x00020018 00100000000000011000
   0x0158      MR3                        : 197120     0x00030200 00110000001000000000
   0x015C      MR4                        : 264192     0x00040800 01000000100000000000
   0x0160      MR5                        : 332832     0x00051420 01010001010000100000
   0x0164      MR6                        : 395363     0x00060863 01100000100001100011
