sysA |

2016.12.06.14:11:58 | Datasheet

Overview

All Components
ddr4_controller altera_emif 16.1
Memory Map

| bb_emif_master
ctrl_amm_0
ddr4_controller |
ctrl_amm_0 | 0x00000000

## bb_emif_master

system_generic_component_0 v1.0

ddr4_controller | emif_usr_clk | bb_emif_master
emif_usr_clk
status
status
emif_usr_reset_n
emif_usr_reset_n
|  | ctrl_amm_0 | ddr4_controller
|  | ctrl_amm_0

## Parameters
componentDefinition | <componentDefinition> <boundary> <interfaces> <interface> <name>status</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>local_cal_success</name> <role>local_cal_success</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>local_cal_fail</name> <role>local_cal_fail</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>emif_usr_reset_n</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>emif_usr_reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>emif_usr_clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>emif_usr_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>200000000</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>ctrl_amm_0</name> <type>avalon</type> <isStart>true</isStart> <ports> <port> <name>amm_ready_0</name> <role>waitrequest_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_read_0</name> <role>read</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_write_0</name> <role>write</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_address_0</name> <role>address</role> <direction>Output</direction> <width>27</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_readdata_0</name> <role>readdata</role> <direction>Input</direction> <width>576</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_writedata_0</name> <role>writedata</role> <direction>Output</direction> <width>576</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_burstcount_0</name> <role>burstcount</role> <direction>Output</direction> <width>7</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_byteenable_0</name> <role>byteenable</role> <direction>Output</direction> <width>72</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_readdatavalid_0</name> <role>readdatavalid</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>adaptsTo</key> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>emif_usr_clk</value> </entry> <entry> <key>associatedReset</key> <value>emif_usr_reset_n</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>dBSBigEndian</key> <value>false</value> </entry> <entry> <key>doStreamReads</key> <value>false</value> </entry> <entry> <key>doStreamWrites</key> <value>false</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isAsynchronous</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isReadable</key> <value>false</value> </entry> <entry> <key>isWriteable</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maxAddressWidth</key> <value>32</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>64</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitTime</key> <value>1</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>system_generic_component_0</className> <version>1.0</version> <displayName>system_generic_component_0</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors/> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos/> </systemInfos> </componentDefinition>
generationInfoDefinition | <generationInfoDefinition> <hdlLibraryName>bb_emif_status</hdlLibraryName> <fileSets> <fileSet> <fileSetName>QUARTUS_SYNTH</fileSetName> <fileSetFixedName>bb_emif_status</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>SIM_VERILOG</fileSetName> <fileSetFixedName>bb_emif_status</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>SIM_VHDL</fileSetName> <fileSetFixedName>bb_emif_status</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition>
logicalView |
moduleAssignmentDefinition | <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition>
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## ddr4_controller

altera_emif v16.1

bb_emif_master | ctrl_amm_0 | ddr4_controller
ctrl_amm_0
|  | emif_usr_clk | bb_emif_master
|  | emif_usr_clk
|  | status
|  | status
|  | emif_usr_reset_n
|  | emif_usr_reset_n

## Parameters
componentDefinition | <componentDefinition> <boundary> <interfaces> <interface> <name>ctrl_amm_0</name> <type>avalon</type> <isStart>false</isStart> <ports> <port> <name>amm_ready_0</name> <role>waitrequest_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_read_0</name> <role>read</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_write_0</name> <role>write</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>amm_address_0</name> <role>address</role> <direction>Input</direction> <width>26</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_readdata_0</name> <role>readdata</role> <direction>Output</direction> <width>576</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_writedata_0</name> <role>writedata</role> <direction>Input</direction> <width>576</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_burstcount_0</name> <role>burstcount</role> <direction>Input</direction> <width>7</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_byteenable_0</name> <role>byteenable</role> <direction>Input</direction> <width>72</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>amm_readdatavalid_0</name> <role>readdatavalid</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>embeddedsw.configuration.isFlash</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isMemoryDevice</key> <value>1</value> </entry> <entry> <key>embeddedsw.configuration.isNonVolatileStorage</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isPrintableDevice</key> <value>0</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>addressAlignment</key> <value>DYNAMIC</value> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressSpan</key> <value>4831838208</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>emif_usr_clk</value> </entry> <entry> <key>associatedReset</key> <value>emif_usr_reset_n</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>bridgedAddressOffset</key> <value>0</value> </entry> <entry> <key>bridgesToMaster</key> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>explicitAddressSpan</key> <value>0</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isFlash</key> <value>false</value> </entry> <entry> <key>isMemoryDevice</key> <value>true</value> </entry> <entry> <key>isNonVolatileStorage</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>64</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>minimumUninterruptedRunLength</key> <value>1</value> </entry> <entry> <key>printableDevice</key> <value>false</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitStates</key> <value>1</value> </entry> <entry> <key>readWaitTime</key> <value>1</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>transparentBridge</key> <value>false</value> </entry> <entry> <key>wellBehavedWaitrequest</key> <value>false</value> </entry> <entry> <key>writeLatency</key> <value>0</value> </entry> <entry> <key>writeWaitStates</key> <value>0</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>emif_usr_clk</name> <type>clock</type> <isStart>true</isStart> <ports> <port> <name>emif_usr_clk</name> <role>clk</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedDirectClock</key> </entry> <entry> <key>clockRate</key> <value>200000000</value> </entry> <entry> <key>clockRateKnown</key> <value>true</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>emif_usr_reset_n</name> <type>reset</type> <isStart>true</isStart> <ports> <port> <name>emif_usr_reset_n</name> <role>reset_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedDirectReset</key> </entry> <entry> <key>associatedResetSinks</key> <value>global_reset_n</value> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>global_reset_n</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>global_reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>mem</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>mem_ck</name> <role>mem_ck</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_ck_n</name> <role>mem_ck_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_a</name> <role>mem_a</role> <direction>Output</direction> <width>17</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_act_n</name> <role>mem_act_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_ba</name> <role>mem_ba</role> <direction>Output</direction> <width>2</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_bg</name> <role>mem_bg</role> <direction>Output</direction> <width>2</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_cke</name> <role>mem_cke</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_cs_n</name> <role>mem_cs_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_odt</name> <role>mem_odt</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_reset_n</name> <role>mem_reset_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_par</name> <role>mem_par</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_alert_n</name> <role>mem_alert_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_dqs</name> <role>mem_dqs</role> <direction>Bidir</direction> <width>9</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_dqs_n</name> <role>mem_dqs_n</role> <direction>Bidir</direction> <width>9</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_dq</name> <role>mem_dq</role> <direction>Bidir</direction> <width>72</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>mem_dbi_n</name> <role>mem_dbi_n</role> <direction>Bidir</direction> <width>9</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>oct</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>oct_rzqin</name> <role>oct_rzqin</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>pll_ref_clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>pll_ref_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>status</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>local_cal_success</name> <role>local_cal_success</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>local_cal_fail</name> <role>local_cal_fail</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundary> <originalModuleInfo> <className>altera_emif</className> <version>16.1</version> <displayName>Arria 10 External Memory Interfaces</displayName> </originalModuleInfo> <systemInfoParameterDescriptors> <descriptors> <descriptor> <parameterDefaultValue>50000000</parameterDefaultValue> <parameterName>CAL_DEBUG_CLOCK_FREQUENCY</parameterName> <parameterType>java.lang.Long</parameterType> <systemInfoArgs>cal_debug_clk_clock_sink</systemInfoArgs> <systemInfotype>CLOCK_RATE</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>SYS_INFO_DEVICE</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>SYS_INFO_DEVICE_FAMILY</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE_FAMILY</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>SYS_INFO_DEVICE_SPEEDGRADE</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue></parameterDefaultValue> <parameterName>SYS_INFO_UNIQUE_ID</parameterName> <parameterType>java.lang.String</parameterType> <systemInfotype>UNIQUE_ID</systemInfotype> </descriptor> <descriptor> <parameterDefaultValue>0</parameterDefaultValue> <parameterName>TRAIT_SUPPORTS_VID</parameterName> <parameterType>java.lang.String</parameterType> <systemInfoArgs>SUPPORTS_VID</systemInfoArgs> <systemInfotype>PART_TRAIT</systemInfotype> </descriptor> </descriptors> </systemInfoParameterDescriptors> <systemInfos> <connPtSystemInfos> <entry> <key>ctrl_amm_0</key> <value> <connectionPointName>ctrl_amm_0</connectionPointName> <suppliedSystemInfos> <entry> <key>ADDRESS_MAP</key> <value>&lt;address-map&gt;&lt;slave name='ctrl_amm_0' start='0x0' end='0x120000000' datawidth='576' /&gt;&lt;/address-map&gt;</value> </entry> <entry> <key>ADDRESS_WIDTH</key> <value>33</value> </entry> <entry> <key>MAX_SLAVE_DATA_WIDTH</key> <value>576</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> <entry> <key>emif_usr_clk</key> <value> <connectionPointName>emif_usr_clk</connectionPointName> <suppliedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>200000000</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> </connPtSystemInfos> </systemInfos> </componentDefinition>
generationInfoDefinition | <generationInfoDefinition> <hdlLibraryName>system_emif_0</hdlLibraryName> <fileSets> <fileSet> <fileSetName>system_emif_0</fileSetName> <fileSetFixedName>system_emif_0</fileSetFixedName> <fileSetKind>QUARTUS_SYNTH</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_emif_0</fileSetName> <fileSetFixedName>system_emif_0</fileSetFixedName> <fileSetKind>SIM_VERILOG</fileSetKind> <fileSetFiles/> </fileSet> <fileSet> <fileSetName>system_emif_0</fileSetName> <fileSetFixedName>system_emif_0</fileSetFixedName> <fileSetKind>SIM_VHDL</fileSetKind> <fileSetFiles/> </fileSet> </fileSets> </generationInfoDefinition>
logicalView | ip/system/system_emif_0.ip
moduleAssignmentDefinition | <assignmentDefinition> <assignmentValueMap/> </assignmentDefinition>
CAL_DEBUG_CLOCK_FREQUENCY | 50000000
SYS_INFO_DEVICE | 10AX115R4F40I3SG
SYS_INFO_DEVICE_FAMILY | ARRIA10
SYS_INFO_DEVICE_SPEEDGRADE | 3
SYS_INFO_UNIQUE_ID | sysA_ddr4_controller
TRAIT_SUPPORTS_VID | 0
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX115R4F40I3SG
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

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