system_emif_0 |

2016.12.06.14:11:53 | Datasheet

Overview

All Components
system_emif_0 altera_emif 16.1
system_emif_0_arch altera_emif_arch_nf 16.1
system_emif_0_cal_slave_component altera_emif_cal_slave_nf 16.1
system_emif_0_cal_slave_component_ioaux_master_bridge altera_avalon_mm_bridge 16.1
system_emif_0_cal_slave_component_ioaux_soft_ram altera_avalon_onchip_memory2 16.1
Memory Map

| system_emif_0_arch
cal_master
system_emif_0 |
ctrl_amm_0 |
system_emif_0_arch |
ctrl_amm_0 |
system_emif_0_cal_slave_component |
avl |
system_emif_0_cal_slave_component_ioaux_soft_ram |
s1 | 0x00000000

## system_emif_0

altera_emif v16.1

## Parameters
SYS_INFO_DEVICE_FAMILY | ARRIA10
SYS_INFO_DEVICE | 10AX115R4F40I3SG
SYS_INFO_DEVICE_SPEEDGRADE | 3
FAMILY_ENUM | FAMILY_ARRIA10
TRAIT_SUPPORTS_VID | 0
PROTOCOL_ENUM | PROTOCOL_DDR4
IS_ED_SLAVE | false
INTERNAL_TESTING_MODE | false
CAL_DEBUG_CLOCK_FREQUENCY | 50000000
SYS_INFO_UNIQUE_ID | system_emif_0_system_emif_0
PREV_PROTOCOL_ENUM | PROTOCOL_DDR4
PHY_FPGA_SPEEDGRADE_GUI | I3 (Production) - change device under 'View'->'Device Family'
PHY_TARGET_SPEEDGRADE | I3
PHY_TARGET_IS_ES | false
PHY_TARGET_IS_ES2 | false
PHY_TARGET_IS_ES3 | false
PHY_TARGET_IS_PRODUCTION | true
PHY_CONFIG_ENUM | CONFIG_PHY_AND_HARD_CTRL
PHY_PING_PONG_EN | false
PHY_RATE_ENUM | RATE_QUARTER
PHY_MEM_CLK_FREQ_MHZ | 800.0
PHY_REF_CLK_FREQ_MHZ | 200.0
PHY_REF_CLK_JITTER_PS | 10.0
PHY_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_CALIBRATED_OCT | true
PHY_AC_CALIBRATED_OCT | true
PHY_CK_CALIBRATED_OCT | true
PHY_DATA_CALIBRATED_OCT | true
PHY_RZQ | 240
PHY_HPS_ENABLE_EARLY_RELEASE | false
PHY_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PLL_VCO_CLK_FREQ_MHZ | 800.0
PLL_SPEEDGRADE | 3
PLL_DISALLOW_EXTRA_CLKS | false
PLL_NUM_OF_EXTRA_CLKS | 0
PLL_MAPPED_SYS_INFO_DEVICE_FAMILY | Arria 10
PLL_MAPPED_SYS_INFO_DEVICE | 10AX115R4F40I3SG
PLL_MAPPED_SYS_INFO_DEVICE_SPEEDGRADE | 3
PLL_MAPPED_REFERENCE_CLOCK_FREQUENCY | 200.0
PLL_MAPPED_VCO_FREQUENCY | 800.0 MHz
PLL_MAPPED_EXTERNAL_PLL_MODE | false
PLL_ADD_EXTRA_CLKS | 0
PLL_COMPENSATION_MODE | emif
PLL_USER_NUM_OF_EXTRA_CLKS | 0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 | 200.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 | 200.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_0 | 200.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 | 313.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 | 313
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 | 22.5
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_0 | 312.5
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 | 50
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 | 400.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 | 400.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_1 | 400.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 | 313.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 | 313
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 | 45.1
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_1 | 312.5
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 | 50
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 | 200.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 | 200.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_2 | 200.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 | 313.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 | 313
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 | 22.5
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_2 | 312.5
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 | 50
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 | 160.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 | 160.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_3 | 160.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 | 0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_3 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 | 50
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 | 160.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 | 160.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_4 | 160.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 | 0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_4 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 | 50
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_5 | 100.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_5 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_6 | 100.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_6 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_7 | 100.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_7 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_8 | 100.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_8 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 | 50.0
PHY_DDR3_CONFIG_ENUM | CONFIG_PHY_AND_HARD_CTRL
PHY_DDR3_USER_PING_PONG_EN | false
PHY_DDR3_MEM_CLK_FREQ_MHZ | 800.0
PHY_DDR3_DEFAULT_REF_CLK_FREQ | true
PHY_DDR3_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_DDR3_REF_CLK_JITTER_PS | 10.0
PHY_DDR3_RATE_ENUM | RATE_QUARTER
PHY_DDR3_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_DDR3_IO_VOLTAGE | 1.5
PHY_DDR3_DEFAULT_IO | true
PHY_DDR3_HPS_ENABLE_EARLY_RELEASE | false
PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_DDR3_REF_CLK_FREQ_MHZ | -1.0
PHY_DDR3_PING_PONG_EN | false
PHY_DDR3_USER_AC_IO_STD_ENUM | unset
PHY_DDR3_USER_AC_MODE_ENUM | unset
PHY_DDR3_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR3_USER_CK_IO_STD_ENUM | unset
PHY_DDR3_USER_CK_MODE_ENUM | unset
PHY_DDR3_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR3_USER_DATA_IO_STD_ENUM | unset
PHY_DDR3_USER_DATA_OUT_MODE_ENUM | unset
PHY_DDR3_USER_DATA_IN_MODE_ENUM | unset
PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN | true
PHY_DDR3_USER_STARTING_VREFIN | 70.0
PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_DDR3_USER_RZQ_IO_STD_ENUM | unset
PHY_DDR3_AC_IO_STD_ENUM | unset
PHY_DDR3_AC_MODE_ENUM | unset
PHY_DDR3_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR3_CK_IO_STD_ENUM | unset
PHY_DDR3_CK_MODE_ENUM | unset
PHY_DDR3_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR3_DATA_IO_STD_ENUM | unset
PHY_DDR3_DATA_OUT_MODE_ENUM | unset
PHY_DDR3_DATA_IN_MODE_ENUM | unset
PHY_DDR3_AUTO_STARTING_VREFIN_EN | true
PHY_DDR3_STARTING_VREFIN | 70.0
PHY_DDR3_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_DDR3_RZQ_IO_STD_ENUM | unset
PHY_DDR3_CAL_ADDR0 | 0
PHY_DDR3_CAL_ADDR1 | 8
PHY_DDR3_CAL_ENABLE_NON_DES | false
PHY_DDR4_CONFIG_ENUM | CONFIG_PHY_AND_HARD_CTRL
PHY_DDR4_USER_PING_PONG_EN | false
PHY_DDR4_MEM_CLK_FREQ_MHZ | 800.0
PHY_DDR4_DEFAULT_REF_CLK_FREQ | true
PHY_DDR4_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_DDR4_REF_CLK_JITTER_PS | 10.0
PHY_DDR4_RATE_ENUM | RATE_QUARTER
PHY_DDR4_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_DDR4_IO_VOLTAGE | 1.2
PHY_DDR4_DEFAULT_IO | true
PHY_DDR4_HPS_ENABLE_EARLY_RELEASE | false
PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_DDR4_REF_CLK_FREQ_MHZ | 200.0
PHY_DDR4_PING_PONG_EN | false
PHY_DDR4_USER_AC_IO_STD_ENUM | unset
PHY_DDR4_USER_AC_MODE_ENUM | unset
PHY_DDR4_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR4_USER_CK_IO_STD_ENUM | unset
PHY_DDR4_USER_CK_MODE_ENUM | unset
PHY_DDR4_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR4_USER_DATA_IO_STD_ENUM | unset
PHY_DDR4_USER_DATA_OUT_MODE_ENUM | unset
PHY_DDR4_USER_DATA_IN_MODE_ENUM | unset
PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN | true
PHY_DDR4_USER_STARTING_VREFIN | 70.0
PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_DDR4_USER_RZQ_IO_STD_ENUM | unset
PHY_DDR4_AC_IO_STD_ENUM | IO_STD_SSTL_12
PHY_DDR4_AC_MODE_ENUM | OUT_OCT_40_CAL
PHY_DDR4_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR4_CK_IO_STD_ENUM | IO_STD_SSTL_12
PHY_DDR4_CK_MODE_ENUM | OUT_OCT_40_CAL
PHY_DDR4_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR4_DATA_IO_STD_ENUM | IO_STD_POD_12
PHY_DDR4_DATA_OUT_MODE_ENUM | OUT_OCT_34_CAL
PHY_DDR4_DATA_IN_MODE_ENUM | IN_OCT_120_CAL
PHY_DDR4_AUTO_STARTING_VREFIN_EN | true
PHY_DDR4_STARTING_VREFIN | 61.0
PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM | IO_STD_LVDS
PHY_DDR4_RZQ_IO_STD_ENUM | IO_STD_CMOS_12
PHY_QDR2_CONFIG_ENUM | CONFIG_PHY_AND_SOFT_CTRL
PHY_QDR2_USER_PING_PONG_EN | false
PHY_QDR2_MEM_CLK_FREQ_MHZ | 633.333
PHY_QDR2_DEFAULT_REF_CLK_FREQ | true
PHY_QDR2_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_QDR2_REF_CLK_JITTER_PS | 10.0
PHY_QDR2_RATE_ENUM | RATE_HALF
PHY_QDR2_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_QDR2_IO_VOLTAGE | 1.5
PHY_QDR2_DEFAULT_IO | true
PHY_QDR2_HPS_ENABLE_EARLY_RELEASE | false
PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_QDR2_REF_CLK_FREQ_MHZ | -1.0
PHY_QDR2_PING_PONG_EN | false
PHY_QDR2_USER_AC_IO_STD_ENUM | unset
PHY_QDR2_USER_AC_MODE_ENUM | unset
PHY_QDR2_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR2_USER_CK_IO_STD_ENUM | unset
PHY_QDR2_USER_CK_MODE_ENUM | unset
PHY_QDR2_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR2_USER_DATA_IO_STD_ENUM | unset
PHY_QDR2_USER_DATA_OUT_MODE_ENUM | unset
PHY_QDR2_USER_DATA_IN_MODE_ENUM | unset
PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN | true
PHY_QDR2_USER_STARTING_VREFIN | 70.0
PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_QDR2_USER_RZQ_IO_STD_ENUM | unset
PHY_QDR2_AC_IO_STD_ENUM | unset
PHY_QDR2_AC_MODE_ENUM | unset
PHY_QDR2_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR2_CK_IO_STD_ENUM | unset
PHY_QDR2_CK_MODE_ENUM | unset
PHY_QDR2_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR2_DATA_IO_STD_ENUM | unset
PHY_QDR2_DATA_OUT_MODE_ENUM | unset
PHY_QDR2_DATA_IN_MODE_ENUM | unset
PHY_QDR2_AUTO_STARTING_VREFIN_EN | true
PHY_QDR2_STARTING_VREFIN | 70.0
PHY_QDR2_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_QDR2_RZQ_IO_STD_ENUM | unset
PHY_QDR4_CONFIG_ENUM | CONFIG_PHY_AND_SOFT_CTRL
PHY_QDR4_USER_PING_PONG_EN | false
PHY_QDR4_MEM_CLK_FREQ_MHZ | 1066.667
PHY_QDR4_DEFAULT_REF_CLK_FREQ | true
PHY_QDR4_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_QDR4_REF_CLK_JITTER_PS | 10.0
PHY_QDR4_RATE_ENUM | RATE_QUARTER
PHY_QDR4_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_QDR4_IO_VOLTAGE | 1.2
PHY_QDR4_DEFAULT_IO | true
PHY_QDR4_HPS_ENABLE_EARLY_RELEASE | false
PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_QDR4_REF_CLK_FREQ_MHZ | -1.0
PHY_QDR4_PING_PONG_EN | false
PHY_QDR4_USER_AC_IO_STD_ENUM | unset
PHY_QDR4_USER_AC_MODE_ENUM | unset
PHY_QDR4_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR4_USER_CK_IO_STD_ENUM | unset
PHY_QDR4_USER_CK_MODE_ENUM | unset
PHY_QDR4_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR4_USER_DATA_IO_STD_ENUM | unset
PHY_QDR4_USER_DATA_OUT_MODE_ENUM | unset
PHY_QDR4_USER_DATA_IN_MODE_ENUM | unset
PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN | true
PHY_QDR4_USER_STARTING_VREFIN | 70.0
PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_QDR4_USER_RZQ_IO_STD_ENUM | unset
PHY_QDR4_AC_IO_STD_ENUM | unset
PHY_QDR4_AC_MODE_ENUM | unset
PHY_QDR4_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR4_CK_IO_STD_ENUM | unset
PHY_QDR4_CK_MODE_ENUM | unset
PHY_QDR4_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR4_DATA_IO_STD_ENUM | unset
PHY_QDR4_DATA_OUT_MODE_ENUM | unset
PHY_QDR4_DATA_IN_MODE_ENUM | unset
PHY_QDR4_AUTO_STARTING_VREFIN_EN | true
PHY_QDR4_STARTING_VREFIN | 70.0
PHY_QDR4_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_QDR4_RZQ_IO_STD_ENUM | unset
PHY_RLD2_CONFIG_ENUM | CONFIG_PHY_AND_SOFT_CTRL
PHY_RLD2_USER_PING_PONG_EN | false
PHY_RLD2_MEM_CLK_FREQ_MHZ | 533.333
PHY_RLD2_DEFAULT_REF_CLK_FREQ | true
PHY_RLD2_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_RLD2_REF_CLK_JITTER_PS | 10.0
PHY_RLD2_RATE_ENUM | RATE_HALF
PHY_RLD2_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_RLD2_IO_VOLTAGE | 1.8
PHY_RLD2_DEFAULT_IO | true
PHY_RLD2_HPS_ENABLE_EARLY_RELEASE | false
PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_RLD2_REF_CLK_FREQ_MHZ | -1.0
PHY_RLD2_PING_PONG_EN | false
PHY_RLD2_USER_AC_IO_STD_ENUM | unset
PHY_RLD2_USER_AC_MODE_ENUM | unset
PHY_RLD2_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD2_USER_CK_IO_STD_ENUM | unset
PHY_RLD2_USER_CK_MODE_ENUM | unset
PHY_RLD2_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD2_USER_DATA_IO_STD_ENUM | unset
PHY_RLD2_USER_DATA_OUT_MODE_ENUM | unset
PHY_RLD2_USER_DATA_IN_MODE_ENUM | unset
PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN | true
PHY_RLD2_USER_STARTING_VREFIN | 70.0
PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_RLD2_USER_RZQ_IO_STD_ENUM | unset
PHY_RLD2_AC_IO_STD_ENUM | unset
PHY_RLD2_AC_MODE_ENUM | unset
PHY_RLD2_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD2_CK_IO_STD_ENUM | unset
PHY_RLD2_CK_MODE_ENUM | unset
PHY_RLD2_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD2_DATA_IO_STD_ENUM | unset
PHY_RLD2_DATA_OUT_MODE_ENUM | unset
PHY_RLD2_DATA_IN_MODE_ENUM | unset
PHY_RLD2_AUTO_STARTING_VREFIN_EN | true
PHY_RLD2_STARTING_VREFIN | 70.0
PHY_RLD2_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_RLD2_RZQ_IO_STD_ENUM | unset
PHY_RLD3_CONFIG_ENUM | CONFIG_PHY_ONLY
PHY_RLD3_USER_PING_PONG_EN | false
PHY_RLD3_MEM_CLK_FREQ_MHZ | 1066.667
PHY_RLD3_DEFAULT_REF_CLK_FREQ | true
PHY_RLD3_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_RLD3_REF_CLK_JITTER_PS | 10.0
PHY_RLD3_RATE_ENUM | RATE_QUARTER
PHY_RLD3_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_RLD3_IO_VOLTAGE | 1.2
PHY_RLD3_DEFAULT_IO | true
PHY_RLD3_HPS_ENABLE_EARLY_RELEASE | false
PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_RLD3_REF_CLK_FREQ_MHZ | -1.0
PHY_RLD3_PING_PONG_EN | false
PHY_RLD3_USER_AC_IO_STD_ENUM | unset
PHY_RLD3_USER_AC_MODE_ENUM | unset
PHY_RLD3_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD3_USER_CK_IO_STD_ENUM | unset
PHY_RLD3_USER_CK_MODE_ENUM | unset
PHY_RLD3_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD3_USER_DATA_IO_STD_ENUM | unset
PHY_RLD3_USER_DATA_OUT_MODE_ENUM | unset
PHY_RLD3_USER_DATA_IN_MODE_ENUM | unset
PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN | true
PHY_RLD3_USER_STARTING_VREFIN | 70.0
PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_RLD3_USER_RZQ_IO_STD_ENUM | unset
PHY_RLD3_AC_IO_STD_ENUM | unset
PHY_RLD3_AC_MODE_ENUM | unset
PHY_RLD3_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD3_CK_IO_STD_ENUM | unset
PHY_RLD3_CK_MODE_ENUM | unset
PHY_RLD3_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD3_DATA_IO_STD_ENUM | unset
PHY_RLD3_DATA_OUT_MODE_ENUM | unset
PHY_RLD3_DATA_IN_MODE_ENUM | unset
PHY_RLD3_AUTO_STARTING_VREFIN_EN | true
PHY_RLD3_STARTING_VREFIN | 70.0
PHY_RLD3_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_RLD3_RZQ_IO_STD_ENUM | unset
PHY_LPDDR3_CONFIG_ENUM | CONFIG_PHY_AND_HARD_CTRL
PHY_LPDDR3_USER_PING_PONG_EN | false
PHY_LPDDR3_MEM_CLK_FREQ_MHZ | 800.0
PHY_LPDDR3_DEFAULT_REF_CLK_FREQ | true
PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_LPDDR3_REF_CLK_JITTER_PS | 10.0
PHY_LPDDR3_RATE_ENUM | RATE_QUARTER
PHY_LPDDR3_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_LPDDR3_IO_VOLTAGE | 1.2
PHY_LPDDR3_DEFAULT_IO | true
PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE | false
PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_LPDDR3_REF_CLK_FREQ_MHZ | -1.0
PHY_LPDDR3_PING_PONG_EN | false
PHY_LPDDR3_USER_AC_IO_STD_ENUM | unset
PHY_LPDDR3_USER_AC_MODE_ENUM | unset
PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_LPDDR3_USER_CK_IO_STD_ENUM | unset
PHY_LPDDR3_USER_CK_MODE_ENUM | unset
PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_LPDDR3_USER_DATA_IO_STD_ENUM | unset
PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM | unset
PHY_LPDDR3_USER_DATA_IN_MODE_ENUM | unset
PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN | true
PHY_LPDDR3_USER_STARTING_VREFIN | 70.0
PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_LPDDR3_USER_RZQ_IO_STD_ENUM | unset
PHY_LPDDR3_AC_IO_STD_ENUM | unset
PHY_LPDDR3_AC_MODE_ENUM | unset
PHY_LPDDR3_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_LPDDR3_CK_IO_STD_ENUM | unset
PHY_LPDDR3_CK_MODE_ENUM | unset
PHY_LPDDR3_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_LPDDR3_DATA_IO_STD_ENUM | unset
PHY_LPDDR3_DATA_OUT_MODE_ENUM | unset
PHY_LPDDR3_DATA_IN_MODE_ENUM | unset
PHY_LPDDR3_AUTO_STARTING_VREFIN_EN | true
PHY_LPDDR3_STARTING_VREFIN | 70.0
PHY_LPDDR3_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_LPDDR3_RZQ_IO_STD_ENUM | unset
MEM_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_READ_LATENCY | 18.0
MEM_WRITE_LATENCY | 12
MEM_BURST_LENGTH | 8
MEM_DATA_MASK_EN | true
MEM_HAS_SIM_SUPPORT | true
MEM_NUM_OF_LOGICAL_RANKS | 1
MEM_TTL_DATA_WIDTH | 72
MEM_TTL_NUM_OF_READ_GROUPS | 9
MEM_TTL_NUM_OF_WRITE_GROUPS | 9
MEM_DDR3_FORMAT_ENUM | MEM_FORMAT_UDIMM
MEM_DDR3_DQ_WIDTH | 72
MEM_DDR3_DQ_PER_DQS | 8
MEM_DDR3_DISCRETE_CS_WIDTH | 1
MEM_DDR3_NUM_OF_DIMMS | 1
MEM_DDR3_RANKS_PER_DIMM | 1
MEM_DDR3_CKE_PER_DIMM | 1
MEM_DDR3_CK_WIDTH | 1
MEM_DDR3_ROW_ADDR_WIDTH | 15
MEM_DDR3_COL_ADDR_WIDTH | 10
MEM_DDR3_BANK_ADDR_WIDTH | 3
MEM_DDR3_DM_EN | true
MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN | false
MEM_DDR3_MIRROR_ADDRESSING_EN | true
MEM_DDR3_HIDE_ADV_MR_SETTINGS | true
MEM_DDR3_RDIMM_CONFIG | 0000000000000000
MEM_DDR3_LRDIMM_EXTENDED_CONFIG | 000000000000000000
MEM_DDR3_ALERT_N_PLACEMENT_ENUM | DDR3_ALERT_N_PLACEMENT_AC_LANES
MEM_DDR3_ALERT_N_DQS_GROUP | 0
MEM_DDR3_DQS_WIDTH | 8
MEM_DDR3_DM_WIDTH | 1
MEM_DDR3_CS_WIDTH | 1
MEM_DDR3_CS_PER_DIMM | 1
MEM_DDR3_CKE_WIDTH | 1
MEM_DDR3_ODT_WIDTH | 1
MEM_DDR3_ADDR_WIDTH | 1
MEM_DDR3_RM_WIDTH | 0
MEM_DDR3_AC_PAR_EN | false
MEM_DDR3_NUM_OF_PHYSICAL_RANKS | 1
MEM_DDR3_NUM_OF_LOGICAL_RANKS | 1
MEM_DDR3_TTL_DQS_WIDTH | 8
MEM_DDR3_TTL_DQ_WIDTH | 72
MEM_DDR3_TTL_DM_WIDTH | 1
MEM_DDR3_TTL_CS_WIDTH | 1
MEM_DDR3_TTL_CK_WIDTH | 1
MEM_DDR3_TTL_CKE_WIDTH | 1
MEM_DDR3_TTL_ODT_WIDTH | 1
MEM_DDR3_TTL_BANK_ADDR_WIDTH | 3
MEM_DDR3_TTL_ADDR_WIDTH | 1
MEM_DDR3_TTL_RM_WIDTH | 0
MEM_DDR3_TTL_NUM_OF_DIMMS | 1
MEM_DDR3_TTL_NUM_OF_PHYSICAL_RANKS | 1
MEM_DDR3_TTL_NUM_OF_LOGICAL_RANKS | 1
MEM_DDR3_MR0 | 0
MEM_DDR3_MR1 | 0
MEM_DDR3_MR2 | 0
MEM_DDR3_MR3 | 0
MEM_DDR3_ADDRESS_MIRROR_BITVEC | 0
MEM_DDR3_BL_ENUM | DDR3_BL_BL8
MEM_DDR3_BT_ENUM | DDR3_BT_SEQUENTIAL
MEM_DDR3_ASR_ENUM | DDR3_ASR_MANUAL
MEM_DDR3_SRT_ENUM | DDR3_SRT_NORMAL
MEM_DDR3_PD_ENUM | DDR3_PD_OFF
MEM_DDR3_DRV_STR_ENUM | DDR3_DRV_STR_RZQ_7
MEM_DDR3_DLL_EN | true
MEM_DDR3_RTT_NOM_ENUM | DDR3_RTT_NOM_ODT_DISABLED
MEM_DDR3_RTT_WR_ENUM | DDR3_RTT_WR_RZQ_4
MEM_DDR3_WTCL | 10
MEM_DDR3_ATCL_ENUM | DDR3_ATCL_DISABLED
MEM_DDR3_TCL | 14
MEM_DDR3_USE_DEFAULT_ODT | true
MEM_DDR3_R_ODTN_1X1 | Rank 0
MEM_DDR3_R_ODT0_1X1 | off
MEM_DDR3_W_ODTN_1X1 | Rank 0
MEM_DDR3_W_ODT0_1X1 | on
MEM_DDR3_R_ODTN_2X2 | Rank 0,Rank 1
MEM_DDR3_R_ODT0_2X2 | off,off
MEM_DDR3_R_ODT1_2X2 | off,off
MEM_DDR3_W_ODTN_2X2 | Rank 0,Rank 1
MEM_DDR3_W_ODT0_2X2 | on,off
MEM_DDR3_W_ODT1_2X2 | off,on
MEM_DDR3_R_ODTN_4X2 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_R_ODT0_4X2 | off,off,on,on
MEM_DDR3_R_ODT1_4X2 | on,on,off,off
MEM_DDR3_W_ODTN_4X2 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_W_ODT0_4X2 | off,off,on,on
MEM_DDR3_W_ODT1_4X2 | on,on,off,off
MEM_DDR3_R_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_R_ODT0_4X4 | off,off,off,off
MEM_DDR3_R_ODT1_4X4 | off,off,on,on
MEM_DDR3_R_ODT2_4X4 | off,off,off,off
MEM_DDR3_R_ODT3_4X4 | on,on,off,off
MEM_DDR3_W_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_W_ODT0_4X4 | on,on,off,off
MEM_DDR3_W_ODT1_4X4 | off,off,on,on
MEM_DDR3_W_ODT2_4X4 | off,off,on,on
MEM_DDR3_W_ODT3_4X4 | on,on,off,off
MEM_DDR3_R_DERIVED_ODTN | ,,
MEM_DDR3_R_DERIVED_ODT0 | ,,
MEM_DDR3_R_DERIVED_ODT1 | ,,
MEM_DDR3_R_DERIVED_ODT2 | ,,
MEM_DDR3_R_DERIVED_ODT3 | ,,
MEM_DDR3_W_DERIVED_ODTN | ,,
MEM_DDR3_W_DERIVED_ODT0 | ,,
MEM_DDR3_W_DERIVED_ODT1 | ,,
MEM_DDR3_W_DERIVED_ODT2 | ,,
MEM_DDR3_W_DERIVED_ODT3 | ,,
MEM_DDR3_SEQ_ODT_TABLE_LO | 0
MEM_DDR3_SEQ_ODT_TABLE_HI | 0
MEM_DDR3_CTRL_CFG_READ_ODT_CHIP | 0
MEM_DDR3_CTRL_CFG_WRITE_ODT_CHIP | 0
MEM_DDR3_CTRL_CFG_READ_ODT_RANK | 0
MEM_DDR3_CTRL_CFG_WRITE_ODT_RANK | 0
MEM_DDR3_SPEEDBIN_ENUM | DDR3_SPEEDBIN_2133
MEM_DDR3_TIS_PS | 60
MEM_DDR3_TIS_AC_MV | 135
MEM_DDR3_TIH_PS | 95
MEM_DDR3_TIH_DC_MV | 100
MEM_DDR3_TDS_PS | 53
MEM_DDR3_TDS_AC_MV | 135
MEM_DDR3_TDH_PS | 55
MEM_DDR3_TDH_DC_MV | 100
MEM_DDR3_TDQSQ_PS | 75
MEM_DDR3_TQH_CYC | 0.38
MEM_DDR3_TDQSCK_PS | 180
MEM_DDR3_TDQSS_CYC | 0.27
MEM_DDR3_TQSH_CYC | 0.4
MEM_DDR3_TDSH_CYC | 0.18
MEM_DDR3_TWLS_PS | 125.0
MEM_DDR3_TWLH_PS | 125.0
MEM_DDR3_TDSS_CYC | 0.18
MEM_DDR3_TINIT_US | 500
MEM_DDR3_TMRD_CK_CYC | 4
MEM_DDR3_TRAS_NS | 33.0
MEM_DDR3_TRCD_NS | 13.09
MEM_DDR3_TRP_NS | 13.09
MEM_DDR3_TREFI_US | 7.8
MEM_DDR3_TRFC_NS | 160.0
MEM_DDR3_TWR_NS | 15.0
MEM_DDR3_TWTR_CYC | 8
MEM_DDR3_TFAW_NS | 25.0
MEM_DDR3_TRRD_CYC | 6
MEM_DDR3_TRTP_CYC | 8
MEM_DDR3_TINIT_CK | 499
MEM_DDR3_TDQSCK_DERV_PS | 2
MEM_DDR3_TDQSCKDS | 450
MEM_DDR3_TDQSCKDM | 900
MEM_DDR3_TDQSCKDL | 1200
MEM_DDR3_TRAS_CYC | 36
MEM_DDR3_TRCD_CYC | 14
MEM_DDR3_TRP_CYC | 14
MEM_DDR3_TRFC_CYC | 171
MEM_DDR3_TWR_CYC | 16
MEM_DDR3_TFAW_CYC | 27
MEM_DDR3_TREFI_CYC | 8320
MEM_DDR3_CFG_GEN_SBE | false
MEM_DDR3_CFG_GEN_DBE | false
MEM_DDR4_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_DDR4_DQ_WIDTH | 72
MEM_DDR4_DQ_PER_DQS | 8
MEM_DDR4_DISCRETE_CS_WIDTH | 1
MEM_DDR4_NUM_OF_DIMMS | 1
MEM_DDR4_RANKS_PER_DIMM | 1
MEM_DDR4_CKE_PER_DIMM | 1
MEM_DDR4_CK_WIDTH | 1
MEM_DDR4_ROW_ADDR_WIDTH | 15
MEM_DDR4_COL_ADDR_WIDTH | 10
MEM_DDR4_BANK_ADDR_WIDTH | 2
MEM_DDR4_BANK_GROUP_WIDTH | 2
MEM_DDR4_CHIP_ID_WIDTH | 0
MEM_DDR4_DM_EN | true
MEM_DDR4_ALERT_PAR_EN | true
MEM_DDR4_ALERT_N_PLACEMENT_ENUM | DDR4_ALERT_N_PLACEMENT_AUTO
MEM_DDR4_ALERT_N_DQS_GROUP | 0
MEM_DDR4_ALERT_N_AC_LANE | 0
MEM_DDR4_ALERT_N_AC_PIN | 0
MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN | false
MEM_DDR4_MIRROR_ADDRESSING_EN | true
MEM_DDR4_HIDE_ADV_MR_SETTINGS | true
MEM_DDR4_BL_ENUM | DDR4_BL_BL8
MEM_DDR4_BT_ENUM | DDR4_BT_SEQUENTIAL
MEM_DDR4_TCL | 18
MEM_DDR4_RTT_NOM_ENUM | DDR4_RTT_NOM_RZQ_4
MEM_DDR4_DLL_EN | true
MEM_DDR4_ATCL_ENUM | DDR4_ATCL_DISABLED
MEM_DDR4_DRV_STR_ENUM | DDR4_DRV_STR_RZQ_7
MEM_DDR4_ASR_ENUM | DDR4_ASR_MANUAL_NORMAL
MEM_DDR4_RTT_WR_ENUM | DDR4_RTT_WR_ODT_DISABLED
MEM_DDR4_WTCL | 12
MEM_DDR4_WRITE_CRC | false
MEM_DDR4_GEARDOWN | DDR4_GEARDOWN_HR
MEM_DDR4_PER_DRAM_ADDR | false
MEM_DDR4_TEMP_SENSOR_READOUT | false
MEM_DDR4_FINE_GRANULARITY_REFRESH | DDR4_FINE_REFRESH_FIXED_1X
MEM_DDR4_MPR_READ_FORMAT | DDR4_MPR_READ_FORMAT_SERIAL
MEM_DDR4_MAX_POWERDOWN | false
MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE | DDR4_TEMP_CONTROLLED_RFSH_NORMAL
MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA | false
MEM_DDR4_INTERNAL_VREFDQ_MONITOR | false
MEM_DDR4_CAL_MODE | 0
MEM_DDR4_SELF_RFSH_ABORT | false
MEM_DDR4_READ_PREAMBLE_TRAINING | false
MEM_DDR4_READ_PREAMBLE | 2
MEM_DDR4_WRITE_PREAMBLE | 1
MEM_DDR4_AC_PARITY_LATENCY | DDR4_AC_PARITY_LATENCY_DISABLE
MEM_DDR4_ODT_IN_POWERDOWN | true
MEM_DDR4_RTT_PARK | DDR4_RTT_PARK_ODT_DISABLED
MEM_DDR4_AC_PERSISTENT_ERROR | false
MEM_DDR4_WRITE_DBI | false
MEM_DDR4_READ_DBI | true
MEM_DDR4_DEFAULT_VREFOUT | true
MEM_DDR4_USER_VREFDQ_TRAINING_VALUE | 56.0
MEM_DDR4_USER_VREFDQ_TRAINING_RANGE | DDR4_VREFDQ_TRAINING_RANGE_1
MEM_DDR4_RCD_CA_IBT_ENUM | DDR4_RCD_CA_IBT_100
MEM_DDR4_RCD_CS_IBT_ENUM | DDR4_RCD_CS_IBT_100
MEM_DDR4_RCD_CKE_IBT_ENUM | DDR4_RCD_CKE_IBT_100
MEM_DDR4_RCD_ODT_IBT_ENUM | DDR4_RCD_ODT_IBT_100
MEM_DDR4_DB_RTT_NOM_ENUM | DDR4_DB_RTT_NOM_ODT_DISABLED
MEM_DDR4_DB_RTT_WR_ENUM | DDR4_DB_RTT_WR_RZQ_3
MEM_DDR4_DB_RTT_PARK_ENUM | DDR4_DB_RTT_PARK_ODT_DISABLED
MEM_DDR4_DB_DQ_DRV_ENUM | DDR4_DB_DRV_STR_RZQ_7
MEM_DDR4_SPD_137_RCD_CA_DRV | 101
MEM_DDR4_SPD_138_RCD_CK_DRV | 5
MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 | 29
MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 | 29
MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 | 29
MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 | 29
MEM_DDR4_SPD_144_DB_VREFDQ | 37
MEM_DDR4_SPD_145_DB_MDQ_DRV | 21
MEM_DDR4_SPD_148_DRAM_DRV | 0
MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM | 20
MEM_DDR4_SPD_152_DRAM_RTT_PARK | 39
MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB | 0
MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB | 0
MEM_DDR4_SPD_135_RCD_REV | 0
MEM_DDR4_SPD_139_DB_REV | 0
MEM_DDR4_LRDIMM_ODT_LESS_BS | true
MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM | 240
MEM_DDR4_DQS_WIDTH | 9
MEM_DDR4_CS_WIDTH | 1
MEM_DDR4_CS_PER_DIMM | 1
MEM_DDR4_CKE_WIDTH | 1
MEM_DDR4_ODT_WIDTH | 1
MEM_DDR4_ADDR_WIDTH | 17
MEM_DDR4_RM_WIDTH | 0
MEM_DDR4_NUM_OF_PHYSICAL_RANKS | 1
MEM_DDR4_NUM_OF_LOGICAL_RANKS | 1
MEM_DDR4_VREFDQ_TRAINING_VALUE | 68.0
MEM_DDR4_VREFDQ_TRAINING_RANGE | DDR4_VREFDQ_TRAINING_RANGE_1
MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP | Range 2 - 45% to 77.5%
MEM_DDR4_TTL_DQS_WIDTH | 9
MEM_DDR4_TTL_DQ_WIDTH | 72
MEM_DDR4_TTL_CS_WIDTH | 1
MEM_DDR4_TTL_CK_WIDTH | 1
MEM_DDR4_TTL_CKE_WIDTH | 1
MEM_DDR4_TTL_ODT_WIDTH | 1
MEM_DDR4_TTL_BANK_ADDR_WIDTH | 2
MEM_DDR4_TTL_BANK_GROUP_WIDTH | 2
MEM_DDR4_TTL_CHIP_ID_WIDTH | 0
MEM_DDR4_TTL_ADDR_WIDTH | 17
MEM_DDR4_TTL_RM_WIDTH | 0
MEM_DDR4_TTL_NUM_OF_DIMMS | 1
MEM_DDR4_TTL_NUM_OF_PHYSICAL_RANKS | 1
MEM_DDR4_TTL_NUM_OF_LOGICAL_RANKS | 1
MEM_DDR4_MR0 | 576
MEM_DDR4_MR1 | 65793
MEM_DDR4_MR2 | 131096
MEM_DDR4_MR3 | 197120
MEM_DDR4_MR4 | 264192
MEM_DDR4_MR5 | 332832
MEM_DDR4_MR6 | 395363
MEM_DDR4_RDIMM_CONFIG |
MEM_DDR4_LRDIMM_EXTENDED_CONFIG |
MEM_DDR4_ADDRESS_MIRROR_BITVEC | 0
MEM_DDR4_USE_DEFAULT_ODT | true
MEM_DDR4_R_ODTN_1X1 | Rank 0
MEM_DDR4_R_ODT0_1X1 | off
MEM_DDR4_W_ODTN_1X1 | Rank 0
MEM_DDR4_W_ODT0_1X1 | on
MEM_DDR4_R_ODTN_2X2 | Rank 0,Rank 1
MEM_DDR4_R_ODT0_2X2 | off,off
MEM_DDR4_R_ODT1_2X2 | off,off
MEM_DDR4_W_ODTN_2X2 | Rank 0,Rank 1
MEM_DDR4_W_ODT0_2X2 | on,off
MEM_DDR4_W_ODT1_2X2 | off,on
MEM_DDR4_R_ODTN_4X2 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X2 | off,off,on,on
MEM_DDR4_R_ODT1_4X2 | on,on,off,off
MEM_DDR4_W_ODTN_4X2 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X2 | off,off,on,on
MEM_DDR4_W_ODT1_4X2 | on,on,off,off
MEM_DDR4_R_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X4 | off,off,off,off
MEM_DDR4_R_ODT1_4X4 | off,off,on,on
MEM_DDR4_R_ODT2_4X4 | off,off,off,off
MEM_DDR4_R_ODT3_4X4 | on,on,off,off
MEM_DDR4_W_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X4 | on,on,off,off
MEM_DDR4_W_ODT1_4X4 | off,off,on,on
MEM_DDR4_W_ODT2_4X4 | off,off,on,on
MEM_DDR4_W_ODT3_4X4 | on,on,off,off
MEM_DDR4_R_DERIVED_ODTN | Rank 0,-,-,-
MEM_DDR4_R_DERIVED_ODT0 | (Drive) RZQ/7 (34 Ohm),-,-,-
MEM_DDR4_R_DERIVED_ODT1 | -,-,-,-
MEM_DDR4_R_DERIVED_ODT2 | -,-,-,-
MEM_DDR4_R_DERIVED_ODT3 | -,-,-,-
MEM_DDR4_W_DERIVED_ODTN | Rank 0,-,-,-
MEM_DDR4_W_DERIVED_ODT0 | (Nominal) RZQ/4 (60 Ohm),-,-,-
MEM_DDR4_W_DERIVED_ODT1 | -,-,-,-
MEM_DDR4_W_DERIVED_ODT2 | -,-,-,-
MEM_DDR4_W_DERIVED_ODT3 | -,-,-,-
MEM_DDR4_SEQ_ODT_TABLE_LO | 4
MEM_DDR4_SEQ_ODT_TABLE_HI | 0
MEM_DDR4_CTRL_CFG_READ_ODT_CHIP | 0
MEM_DDR4_CTRL_CFG_WRITE_ODT_CHIP | 1
MEM_DDR4_CTRL_CFG_READ_ODT_RANK | 0
MEM_DDR4_CTRL_CFG_WRITE_ODT_RANK | 1
MEM_DDR4_SPEEDBIN_ENUM | DDR4_SPEEDBIN_2400
MEM_DDR4_TIS_PS | 60
MEM_DDR4_TIS_AC_MV | 100
MEM_DDR4_TIH_PS | 95
MEM_DDR4_TIH_DC_MV | 75
MEM_DDR4_TDIVW_TOTAL_UI | 0.2
MEM_DDR4_VDIVW_TOTAL | 136
MEM_DDR4_TDQSQ_UI | 0.16
MEM_DDR4_TQH_UI | 0.76
MEM_DDR4_TDVWP_UI | 0.72
MEM_DDR4_TDQSCK_PS | 165
MEM_DDR4_TDQSS_CYC | 0.27
MEM_DDR4_TQSH_CYC | 0.38
MEM_DDR4_TDSH_CYC | 0.18
MEM_DDR4_TDSS_CYC | 0.18
MEM_DDR4_TWLS_PS | 108.0
MEM_DDR4_TWLH_PS | 108.0
MEM_DDR4_TINIT_US | 500
MEM_DDR4_TMRD_CK_CYC | 8
MEM_DDR4_TRAS_NS | 32.0
MEM_DDR4_TRCD_NS | 15.0
MEM_DDR4_TRP_NS | 15.0
MEM_DDR4_TREFI_US | 7.8
MEM_DDR4_TRFC_NS | 260.0
MEM_DDR4_TWR_NS | 15.0
MEM_DDR4_TWTR_L_CYC | 9
MEM_DDR4_TWTR_S_CYC | 3
MEM_DDR4_TFAW_NS | 21.0
MEM_DDR4_TRRD_L_CYC | 6
MEM_DDR4_TRRD_S_CYC | 4
MEM_DDR4_TCCD_L_CYC | 6
MEM_DDR4_TCCD_S_CYC | 4
MEM_DDR4_TDIVW_DJ_CYC | 0.1
MEM_DDR4_TDQSQ_PS | 66
MEM_DDR4_TQH_CYC | 0.38
MEM_DDR4_TINIT_CK | 400000
MEM_DDR4_TDQSCK_DERV_PS | 2
MEM_DDR4_TDQSCKDS | 450
MEM_DDR4_TDQSCKDM | 900
MEM_DDR4_TDQSCKDL | 1200
MEM_DDR4_TRAS_CYC | 26
MEM_DDR4_TRCD_CYC | 12
MEM_DDR4_TRP_CYC | 12
MEM_DDR4_TRFC_CYC | 208
MEM_DDR4_TWR_CYC | 12
MEM_DDR4_TRTP_CYC | 6
MEM_DDR4_TFAW_CYC | 17
MEM_DDR4_TREFI_CYC | 6240
MEM_DDR4_WRITE_CMD_LATENCY | 5
MEM_DDR4_CFG_GEN_SBE | false
MEM_DDR4_CFG_GEN_DBE | false
MEM_DDR4_LRDIMM_VREFDQ_VALUE |
MEM_QDR2_WIDTH_EXPANDED | false
MEM_QDR2_DATA_PER_DEVICE | 36
MEM_QDR2_ADDR_WIDTH | 19
MEM_QDR2_BWS_EN | true
MEM_QDR2_BL | 4
MEM_QDR2_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_QDR2_DEVICE_WIDTH | 1
MEM_QDR2_DATA_WIDTH | 36
MEM_QDR2_BWS_N_WIDTH | 4
MEM_QDR2_BWS_N_PER_DEVICE | 4
MEM_QDR2_CQ_WIDTH | 1
MEM_QDR2_K_WIDTH | 1
MEM_QDR2_TWL_CYC | 1
MEM_QDR2_SPEEDBIN_ENUM | QDR2_SPEEDBIN_633
MEM_QDR2_TRL_CYC | 2.5
MEM_QDR2_TSA_NS | 0.23
MEM_QDR2_THA_NS | 0.18
MEM_QDR2_TSD_NS | 0.23
MEM_QDR2_THD_NS | 0.18
MEM_QDR2_TCQD_NS | 0.09
MEM_QDR2_TCQDOH_NS | -0.09
MEM_QDR2_INTERNAL_JITTER_NS | 0.08
MEM_QDR2_TCQH_NS | 0.71
MEM_QDR2_TCCQO_NS | 0.45
MEM_QDR4_WIDTH_EXPANDED | false
MEM_QDR4_DQ_PER_PORT_PER_DEVICE | 36
MEM_QDR4_ADDR_WIDTH | 21
MEM_QDR4_CK_ODT_MODE_ENUM | QDR4_ODT_25_PCT
MEM_QDR4_AC_ODT_MODE_ENUM | QDR4_ODT_25_PCT
MEM_QDR4_DATA_ODT_MODE_ENUM | QDR4_ODT_25_PCT
MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM | QDR4_OUTPUT_DRIVE_25_PCT
MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM | QDR4_OUTPUT_DRIVE_25_PCT
MEM_QDR4_DATA_INV_ENA | true
MEM_QDR4_ADDR_INV_ENA | false
MEM_QDR4_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_QDR4_DEVICE_WIDTH | 1
MEM_QDR4_DEVICE_DEPTH | 1
MEM_QDR4_DQ_PER_RD_GROUP | 18
MEM_QDR4_DQ_PER_WR_GROUP | 18
MEM_QDR4_DQ_WIDTH | 72
MEM_QDR4_QK_WIDTH | 4
MEM_QDR4_DK_WIDTH | 4
MEM_QDR4_DINV_WIDTH | 4
MEM_QDR4_USE_ADDR_PARITY | false
MEM_QDR4_DQ_PER_PORT_WIDTH | 36
MEM_QDR4_QK_PER_PORT_WIDTH | 2
MEM_QDR4_DK_PER_PORT_WIDTH | 2
MEM_QDR4_DINV_PER_PORT_WIDTH | 2
MEM_QDR4_BL | 2
MEM_QDR4_TRL_CYC | 8
MEM_QDR4_TWL_CYC | 5
MEM_QDR4_CR0 | 0
MEM_QDR4_CR1 | 0
MEM_QDR4_CR2 | 0
MEM_QDR4_SPEEDBIN_ENUM | QDR4_SPEEDBIN_2133
MEM_QDR4_TISH_PS | 150
MEM_QDR4_TQKQ_MAX_PS | 75
MEM_QDR4_TQH_CYC | 0.4
MEM_QDR4_TCKDK_MAX_PS | 150
MEM_QDR4_TCKDK_MIN_PS | -150
MEM_QDR4_TCKQK_MAX_PS | 225
MEM_QDR4_TASH_PS | 170
MEM_QDR4_TCSH_PS | 170
MEM_RLD2_WIDTH_EXPANDED | false
MEM_RLD2_DQ_PER_DEVICE | 9
MEM_RLD2_ADDR_WIDTH | 21
MEM_RLD2_BANK_ADDR_WIDTH | 3
MEM_RLD2_DM_EN | true
MEM_RLD2_BL | 4
MEM_RLD2_CONFIG_ENUM | RLD2_CONFIG_TRC_8_TRL_8_TWL_9
MEM_RLD2_DRIVE_IMPEDENCE_ENUM | RLD2_DRIVE_IMPEDENCE_INTERNAL_50
MEM_RLD2_ODT_MODE_ENUM | RLD2_ODT_ON
MEM_RLD2_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_RLD2_DEVICE_WIDTH | 1
MEM_RLD2_DEVICE_DEPTH | 1
MEM_RLD2_DQ_WIDTH | 9
MEM_RLD2_DQ_PER_RD_GROUP | 9
MEM_RLD2_DQ_PER_WR_GROUP | 9
MEM_RLD2_QK_WIDTH | 1
MEM_RLD2_DK_WIDTH | 1
MEM_RLD2_DM_WIDTH | 1
MEM_RLD2_CS_WIDTH | 1
MEM_RLD2_TRC | 8
MEM_RLD2_TRL | 8
MEM_RLD2_TWL | 9
MEM_RLD2_MR | 0
MEM_RLD2_SPEEDBIN_ENUM | RLD2_SPEEDBIN_18
MEM_RLD2_REFRESH_INTERVAL_US | 0.24
MEM_RLD2_TCKH_CYC | 0.45
MEM_RLD2_TQKH_HCYC | 0.9
MEM_RLD2_TAS_NS | 0.3
MEM_RLD2_TAH_NS | 0.3
MEM_RLD2_TDS_NS | 0.17
MEM_RLD2_TDH_NS | 0.17
MEM_RLD2_TQKQ_MAX_NS | 0.12
MEM_RLD2_TQKQ_MIN_NS | -0.12
MEM_RLD2_TCKDK_MAX_NS | 0.3
MEM_RLD2_TCKDK_MIN_NS | -0.3
MEM_RLD2_TCKQK_MAX_NS | 0.2
MEM_RLD3_WIDTH_EXPANDED | false
MEM_RLD3_DEPTH_EXPANDED | false
MEM_RLD3_DQ_PER_DEVICE | 36
MEM_RLD3_ADDR_WIDTH | 20
MEM_RLD3_BANK_ADDR_WIDTH | 4
MEM_RLD3_DM_EN | true
MEM_RLD3_BL | 2
MEM_RLD3_DATA_LATENCY_MODE_ENUM | RLD3_DL_RL16_WL17
MEM_RLD3_T_RC_MODE_ENUM | RLD3_TRC_9
MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM | RLD3_OUTPUT_DRIVE_40
MEM_RLD3_ODT_MODE_ENUM | RLD3_ODT_40
MEM_RLD3_AREF_PROTOCOL_ENUM | RLD3_AREF_BAC
MEM_RLD3_WRITE_PROTOCOL_ENUM | RLD3_WRITE_1BANK
MEM_RLD3_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_RLD3_DEVICE_WIDTH | 1
MEM_RLD3_DEVICE_DEPTH | 1
MEM_RLD3_DQ_WIDTH | 36
MEM_RLD3_DQ_PER_RD_GROUP | 9
MEM_RLD3_DQ_PER_WR_GROUP | 18
MEM_RLD3_QK_WIDTH | 4
MEM_RLD3_DK_WIDTH | 2
MEM_RLD3_DM_WIDTH | 2
MEM_RLD3_CS_WIDTH | 1
MEM_RLD3_MR0 | 0
MEM_RLD3_MR1 | 0
MEM_RLD3_MR2 | 0
MEM_RLD3_SPEEDBIN_ENUM | RLD3_SPEEDBIN_093E
MEM_RLD3_TDS_PS | -30
MEM_RLD3_TDS_AC_MV | 150
MEM_RLD3_TDH_PS | 5
MEM_RLD3_TDH_DC_MV | 100
MEM_RLD3_TQKQ_MAX_PS | 75
MEM_RLD3_TQH_CYC | 0.38
MEM_RLD3_TCKDK_MAX_CYC | 0.27
MEM_RLD3_TCKDK_MIN_CYC | -0.27
MEM_RLD3_TCKQK_MAX_PS | 135
MEM_RLD3_TIS_PS | 85
MEM_RLD3_TIS_AC_MV | 150
MEM_RLD3_TIH_PS | 65
MEM_RLD3_TIH_DC_MV | 100
MEM_LPDDR3_DQ_WIDTH | 32
MEM_LPDDR3_DISCRETE_CS_WIDTH | 1
MEM_LPDDR3_CK_WIDTH | 1
MEM_LPDDR3_DM_EN | true
MEM_LPDDR3_ROW_ADDR_WIDTH | 15
MEM_LPDDR3_COL_ADDR_WIDTH | 10
MEM_LPDDR3_BANK_ADDR_WIDTH | 3
MEM_LPDDR3_DQS_WIDTH | 1
MEM_LPDDR3_DM_WIDTH | 1
MEM_LPDDR3_CS_WIDTH | 1
MEM_LPDDR3_CKE_WIDTH | 1
MEM_LPDDR3_ODT_WIDTH | 1
MEM_LPDDR3_ADDR_WIDTH | 10
MEM_LPDDR3_DQ_PER_DQS | 8
MEM_LPDDR3_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_LPDDR3_MR1 | 0
MEM_LPDDR3_MR2 | 0
MEM_LPDDR3_MR3 | 0
MEM_LPDDR3_MR11 | 0
MEM_LPDDR3_BL | LPDDR3_BL_BL8
MEM_LPDDR3_DATA_LATENCY | LPDDR3_DL_RL12_WL6
MEM_LPDDR3_DRV_STR | LPDDR3_DRV_STR_40D_40U
MEM_LPDDR3_DQODT | LPDDR3_DQODT_DISABLE
MEM_LPDDR3_PDODT | LPDDR3_PDODT_DISABLED
MEM_LPDDR3_WLSELECT | Set A
MEM_LPDDR3_NWR | LPDDR3_NWR_NWR12
MEM_LPDDR3_NUM_OF_LOGICAL_RANKS | 1
MEM_LPDDR3_NUM_OF_PHYSICAL_RANKS | 1
MEM_LPDDR3_USE_DEFAULT_ODT | true
MEM_LPDDR3_R_ODTN_1X1 | Rank 0
MEM_LPDDR3_R_ODT0_1X1 | off
MEM_LPDDR3_W_ODTN_1X1 | Rank 0
MEM_LPDDR3_W_ODT0_1X1 | on
MEM_LPDDR3_R_ODTN_2X2 | Rank 0,Rank 1
MEM_LPDDR3_R_ODT0_2X2 | off,off
MEM_LPDDR3_R_ODT1_2X2 | off,off
MEM_LPDDR3_W_ODTN_2X2 | Rank 0,Rank 1
MEM_LPDDR3_W_ODT0_2X2 | on,on
MEM_LPDDR3_W_ODT1_2X2 | off,off
MEM_LPDDR3_R_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_LPDDR3_R_ODT0_4X4 | off,off,off,off
MEM_LPDDR3_R_ODT1_4X4 | off,off,off,off
MEM_LPDDR3_R_ODT2_4X4 | off,off,off,off
MEM_LPDDR3_R_ODT3_4X4 | off,off,off,off
MEM_LPDDR3_W_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_LPDDR3_W_ODT0_4X4 | on,on,on,on
MEM_LPDDR3_W_ODT1_4X4 | off,off,off,off
MEM_LPDDR3_W_ODT2_4X4 | off,off,off,off
MEM_LPDDR3_W_ODT3_4X4 | off,off,off,off
MEM_LPDDR3_R_DERIVED_ODTN | ,,
MEM_LPDDR3_R_DERIVED_ODT0 | ,,
MEM_LPDDR3_R_DERIVED_ODT1 | ,,
MEM_LPDDR3_R_DERIVED_ODT2 | ,,
MEM_LPDDR3_R_DERIVED_ODT3 | ,,
MEM_LPDDR3_W_DERIVED_ODTN | ,,
MEM_LPDDR3_W_DERIVED_ODT0 | ,,
MEM_LPDDR3_W_DERIVED_ODT1 | ,,
MEM_LPDDR3_W_DERIVED_ODT2 | ,,
MEM_LPDDR3_W_DERIVED_ODT3 | ,,
MEM_LPDDR3_SEQ_ODT_TABLE_LO | 0
MEM_LPDDR3_SEQ_ODT_TABLE_HI | 0
MEM_LPDDR3_CTRL_CFG_READ_ODT_CHIP | 0
MEM_LPDDR3_CTRL_CFG_WRITE_ODT_CHIP | 0
MEM_LPDDR3_CTRL_CFG_READ_ODT_RANK | 0
MEM_LPDDR3_CTRL_CFG_WRITE_ODT_RANK | 0
MEM_LPDDR3_SPEEDBIN_ENUM | LPDDR3_SPEEDBIN_1600
MEM_LPDDR3_TIS_PS | 75
MEM_LPDDR3_TIS_AC_MV | 150
MEM_LPDDR3_TIH_PS | 100
MEM_LPDDR3_TIH_DC_MV | 100
MEM_LPDDR3_TDS_PS | 75
MEM_LPDDR3_TDS_AC_MV | 150
MEM_LPDDR3_TDH_PS | 100
MEM_LPDDR3_TDH_DC_MV | 100
MEM_LPDDR3_TDQSQ_PS | 135
MEM_LPDDR3_TQH_CYC | 0.38
MEM_LPDDR3_TDQSCKDL | 614
MEM_LPDDR3_TDQSS_CYC | 1.25
MEM_LPDDR3_TQSH_CYC | 0.38
MEM_LPDDR3_TDSH_CYC | 0.2
MEM_LPDDR3_TWLS_PS | 175.0
MEM_LPDDR3_TWLH_PS | 175.0
MEM_LPDDR3_TDSS_CYC | 0.2
MEM_LPDDR3_TINIT_US | 500
MEM_LPDDR3_TMRR_CK_CYC | 4
MEM_LPDDR3_TMRW_CK_CYC | 10
MEM_LPDDR3_TRAS_NS | 42.5
MEM_LPDDR3_TRCD_NS | 18.0
MEM_LPDDR3_TRP_NS | 18.0
MEM_LPDDR3_TREFI_US | 3.9
MEM_LPDDR3_TRFC_NS | 210.0
MEM_LPDDR3_TWR_NS | 15.0
MEM_LPDDR3_TWTR_CYC | 6
MEM_LPDDR3_TFAW_NS | 50.0
MEM_LPDDR3_TRRD_CYC | 8
MEM_LPDDR3_TRTP_CYC | 6
MEM_LPDDR3_TINIT_CK | 499
MEM_LPDDR3_TDQSCK_DERV_PS | 2
MEM_LPDDR3_TDQSCKDS | 220
MEM_LPDDR3_TDQSCKDM | 511
MEM_LPDDR3_TDQSCK_PS | 5500
MEM_LPDDR3_TRAS_CYC | 34
MEM_LPDDR3_TRCD_CYC | 17
MEM_LPDDR3_TRP_CYC | 17
MEM_LPDDR3_TRFC_CYC | 168
MEM_LPDDR3_TWR_CYC | 12
MEM_LPDDR3_TFAW_CYC | 40
MEM_LPDDR3_TREFI_CYC | 3120
MEM_LPDDR3_TRL_CYC | 10
MEM_LPDDR3_TWL_CYC | 6
BOARD_DDR3_USE_DEFAULT_SLEW_RATES | true
BOARD_DDR3_USE_DEFAULT_ISI_VALUES | true
BOARD_DDR3_USER_CK_SLEW_RATE | 4.0
BOARD_DDR3_USER_AC_SLEW_RATE | 2.0
BOARD_DDR3_USER_RCLK_SLEW_RATE | 5.0
BOARD_DDR3_USER_WCLK_SLEW_RATE | 4.0
BOARD_DDR3_USER_RDATA_SLEW_RATE | 2.5
BOARD_DDR3_USER_WDATA_SLEW_RATE | 2.0
BOARD_DDR3_USER_AC_ISI_NS | 0.0
BOARD_DDR3_USER_RCLK_ISI_NS | 0.0
BOARD_DDR3_USER_WCLK_ISI_NS | 0.0
BOARD_DDR3_USER_RDATA_ISI_NS | 0.0
BOARD_DDR3_USER_WDATA_ISI_NS | 0.0
BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED | false
BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED | true
BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_DDR3_DQS_TO_CK_SKEW_NS | 0.02
BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS | 0.05
BOARD_DDR3_SKEW_BETWEEN_DQS_NS | 0.02
BOARD_DDR3_AC_TO_CK_SKEW_NS | 0.0
BOARD_DDR3_MAX_CK_DELAY_NS | 0.6
BOARD_DDR3_MAX_DQS_DELAY_NS | 0.6
BOARD_DDR3_TIS_DERATING_PS | 0
BOARD_DDR3_TIH_DERATING_PS | 0
BOARD_DDR3_TDS_DERATING_PS | 0
BOARD_DDR3_TDH_DERATING_PS | 0
BOARD_DDR3_CK_SLEW_RATE | 4.0
BOARD_DDR3_AC_SLEW_RATE | 2.0
BOARD_DDR3_RCLK_SLEW_RATE | 5.0
BOARD_DDR3_WCLK_SLEW_RATE | 4.0
BOARD_DDR3_RDATA_SLEW_RATE | 2.5
BOARD_DDR3_WDATA_SLEW_RATE | 2.0
BOARD_DDR3_AC_ISI_NS | 0.0
BOARD_DDR3_RCLK_ISI_NS | 0.0
BOARD_DDR3_WCLK_ISI_NS | 0.0
BOARD_DDR3_RDATA_ISI_NS | 0.0
BOARD_DDR3_WDATA_ISI_NS | 0.0
BOARD_DDR3_SKEW_WITHIN_DQS_NS | 0.0
BOARD_DDR3_SKEW_WITHIN_AC_NS | 0.0
BOARD_DDR4_USE_DEFAULT_SLEW_RATES | true
BOARD_DDR4_USE_DEFAULT_ISI_VALUES | true
BOARD_DDR4_USER_CK_SLEW_RATE | 4.0
BOARD_DDR4_USER_AC_SLEW_RATE | 2.0
BOARD_DDR4_USER_RCLK_SLEW_RATE | 8.0
BOARD_DDR4_USER_WCLK_SLEW_RATE | 4.0
BOARD_DDR4_USER_RDATA_SLEW_RATE | 4.0
BOARD_DDR4_USER_WDATA_SLEW_RATE | 2.0
BOARD_DDR4_USER_AC_ISI_NS | 0.0
BOARD_DDR4_USER_RCLK_ISI_NS | 0.0
BOARD_DDR4_USER_WCLK_ISI_NS | 0.0
BOARD_DDR4_USER_RDATA_ISI_NS | 0.0
BOARD_DDR4_USER_WDATA_ISI_NS | 0.0
BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED | true
BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED | false
BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_DDR4_DQS_TO_CK_SKEW_NS | 0.02
BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS | 0.05
BOARD_DDR4_SKEW_BETWEEN_DQS_NS | 0.02
BOARD_DDR4_AC_TO_CK_SKEW_NS | 0.0
BOARD_DDR4_MAX_CK_DELAY_NS | 0.6
BOARD_DDR4_MAX_DQS_DELAY_NS | 0.6
BOARD_DDR4_TIS_DERATING_PS | 0
BOARD_DDR4_TIH_DERATING_PS | 0
BOARD_DDR4_CK_SLEW_RATE | 4.0
BOARD_DDR4_AC_SLEW_RATE | 2.0
BOARD_DDR4_RCLK_SLEW_RATE | 8.0
BOARD_DDR4_WCLK_SLEW_RATE | 4.0
BOARD_DDR4_RDATA_SLEW_RATE | 4.0
BOARD_DDR4_WDATA_SLEW_RATE | 2.0
BOARD_DDR4_AC_ISI_NS | 0.15
BOARD_DDR4_RCLK_ISI_NS | 0.15
BOARD_DDR4_WCLK_ISI_NS | 0.038
BOARD_DDR4_RDATA_ISI_NS | 0.075
BOARD_DDR4_WDATA_ISI_NS | 0.09
BOARD_DDR4_SKEW_WITHIN_DQS_NS | 0.02
BOARD_DDR4_SKEW_WITHIN_AC_NS | 0.18
BOARD_QDR2_USE_DEFAULT_SLEW_RATES | true
BOARD_QDR2_USE_DEFAULT_ISI_VALUES | true
BOARD_QDR2_USER_K_SLEW_RATE | 4.0
BOARD_QDR2_USER_AC_SLEW_RATE | 2.0
BOARD_QDR2_USER_RCLK_SLEW_RATE | 4.0
BOARD_QDR2_USER_RDATA_SLEW_RATE | 2.0
BOARD_QDR2_USER_WDATA_SLEW_RATE | 2.0
BOARD_QDR2_USER_AC_ISI_NS | 0.0
BOARD_QDR2_USER_RCLK_ISI_NS | 0.0
BOARD_QDR2_USER_WCLK_ISI_NS | 0.0
BOARD_QDR2_USER_RDATA_ISI_NS | 0.0
BOARD_QDR2_USER_WDATA_ISI_NS | 0.0
BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED | false
BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED | false
BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED | true
BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS | 0.02
BOARD_QDR2_BRD_SKEW_WITHIN_D_NS | 0.02
BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS | 0.02
BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS | 0.02
BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_QDR2_AC_TO_K_SKEW_NS | 0.0
BOARD_QDR2_MAX_K_DELAY_NS | 0.6
BOARD_QDR2_K_SLEW_RATE | 4.0
BOARD_QDR2_AC_SLEW_RATE | 2.0
BOARD_QDR2_RCLK_SLEW_RATE | 4.0
BOARD_QDR2_WCLK_SLEW_RATE | 4.0
BOARD_QDR2_RDATA_SLEW_RATE | 2.0
BOARD_QDR2_WDATA_SLEW_RATE | 2.0
BOARD_QDR2_AC_ISI_NS | 0.0
BOARD_QDR2_RCLK_ISI_NS | 0.0
BOARD_QDR2_WCLK_ISI_NS | 0.0
BOARD_QDR2_RDATA_ISI_NS | 0.0
BOARD_QDR2_WDATA_ISI_NS | 0.0
BOARD_QDR2_SKEW_WITHIN_Q_NS | 0.0
BOARD_QDR2_SKEW_WITHIN_D_NS | 0.0
BOARD_QDR2_SKEW_WITHIN_AC_NS | 0.0
BOARD_QDR4_USE_DEFAULT_SLEW_RATES | true
BOARD_QDR4_USE_DEFAULT_ISI_VALUES | true
BOARD_QDR4_USER_CK_SLEW_RATE | 4.0
BOARD_QDR4_USER_AC_SLEW_RATE | 2.0
BOARD_QDR4_USER_RCLK_SLEW_RATE | 5.0
BOARD_QDR4_USER_WCLK_SLEW_RATE | 4.0
BOARD_QDR4_USER_RDATA_SLEW_RATE | 2.5
BOARD_QDR4_USER_WDATA_SLEW_RATE | 2.0
BOARD_QDR4_USER_AC_ISI_NS | 0.0
BOARD_QDR4_USER_RCLK_ISI_NS | 0.0
BOARD_QDR4_USER_WCLK_ISI_NS | 0.0
BOARD_QDR4_USER_RDATA_ISI_NS | 0.0
BOARD_QDR4_USER_WDATA_ISI_NS | 0.0
BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED | true
BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS | 0.02
BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS | 0.02
BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED | true
BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_QDR4_DK_TO_CK_SKEW_NS | -0.02
BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS | 0.05
BOARD_QDR4_SKEW_BETWEEN_DK_NS | 0.02
BOARD_QDR4_AC_TO_CK_SKEW_NS | 0.0
BOARD_QDR4_MAX_CK_DELAY_NS | 0.6
BOARD_QDR4_MAX_DK_DELAY_NS | 0.6
BOARD_QDR4_CK_SLEW_RATE | 4.0
BOARD_QDR4_AC_SLEW_RATE | 2.0
BOARD_QDR4_RCLK_SLEW_RATE | 5.0
BOARD_QDR4_WCLK_SLEW_RATE | 4.0
BOARD_QDR4_RDATA_SLEW_RATE | 2.5
BOARD_QDR4_WDATA_SLEW_RATE | 2.0
BOARD_QDR4_AC_ISI_NS | 0.0
BOARD_QDR4_RCLK_ISI_NS | 0.0
BOARD_QDR4_WCLK_ISI_NS | 0.0
BOARD_QDR4_RDATA_ISI_NS | 0.0
BOARD_QDR4_WDATA_ISI_NS | 0.0
BOARD_QDR4_SKEW_WITHIN_QK_NS | 0.0
BOARD_QDR4_SKEW_WITHIN_AC_NS | 0.0
BOARD_RLD3_USE_DEFAULT_SLEW_RATES | true
BOARD_RLD3_USE_DEFAULT_ISI_VALUES | true
BOARD_RLD3_USER_CK_SLEW_RATE | 4.0
BOARD_RLD3_USER_AC_SLEW_RATE | 2.0
BOARD_RLD3_USER_RCLK_SLEW_RATE | 7.0
BOARD_RLD3_USER_WCLK_SLEW_RATE | 4.0
BOARD_RLD3_USER_RDATA_SLEW_RATE | 3.5
BOARD_RLD3_USER_WDATA_SLEW_RATE | 2.0
BOARD_RLD3_USER_AC_ISI_NS | 0.0
BOARD_RLD3_USER_RCLK_ISI_NS | 0.0
BOARD_RLD3_USER_WCLK_ISI_NS | 0.0
BOARD_RLD3_USER_RDATA_ISI_NS | 0.0
BOARD_RLD3_USER_WDATA_ISI_NS | 0.0
BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED | false
BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS | 0.02
BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS | 0.02
BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED | true
BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_RLD3_DK_TO_CK_SKEW_NS | -0.02
BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS | 0.05
BOARD_RLD3_SKEW_BETWEEN_DK_NS | 0.02
BOARD_RLD3_AC_TO_CK_SKEW_NS | 0.0
BOARD_RLD3_MAX_CK_DELAY_NS | 0.6
BOARD_RLD3_MAX_DK_DELAY_NS | 0.6
BOARD_RLD3_TIS_DERATING_PS | 0
BOARD_RLD3_TIH_DERATING_PS | 0
BOARD_RLD3_TDS_DERATING_PS | 0
BOARD_RLD3_TDH_DERATING_PS | 0
BOARD_RLD3_CK_SLEW_RATE | 4.0
BOARD_RLD3_AC_SLEW_RATE | 2.0
BOARD_RLD3_RCLK_SLEW_RATE | 7.0
BOARD_RLD3_WCLK_SLEW_RATE | 4.0
BOARD_RLD3_RDATA_SLEW_RATE | 3.5
BOARD_RLD3_WDATA_SLEW_RATE | 2.0
BOARD_RLD3_AC_ISI_NS | 0.0
BOARD_RLD3_RCLK_ISI_NS | 0.0
BOARD_RLD3_WCLK_ISI_NS | 0.0
BOARD_RLD3_RDATA_ISI_NS | 0.0
BOARD_RLD3_WDATA_ISI_NS | 0.0
BOARD_RLD3_SKEW_WITHIN_QK_NS | 0.0
BOARD_RLD3_SKEW_WITHIN_AC_NS | 0.0
BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES | true
BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES | true
BOARD_LPDDR3_USER_CK_SLEW_RATE | 4.0
BOARD_LPDDR3_USER_AC_SLEW_RATE | 2.0
BOARD_LPDDR3_USER_RCLK_SLEW_RATE | 4.0
BOARD_LPDDR3_USER_WCLK_SLEW_RATE | 4.0
BOARD_LPDDR3_USER_RDATA_SLEW_RATE | 2.0
BOARD_LPDDR3_USER_WDATA_SLEW_RATE | 2.0
BOARD_LPDDR3_USER_AC_ISI_NS | 0.0
BOARD_LPDDR3_USER_RCLK_ISI_NS | 0.0
BOARD_LPDDR3_USER_WCLK_ISI_NS | 0.0
BOARD_LPDDR3_USER_RDATA_ISI_NS | 0.0
BOARD_LPDDR3_USER_WDATA_ISI_NS | 0.0
BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED | false
BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED | true
BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_LPDDR3_DQS_TO_CK_SKEW_NS | 0.02
BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS | 0.05
BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS | 0.02
BOARD_LPDDR3_AC_TO_CK_SKEW_NS | 0.0
BOARD_LPDDR3_MAX_CK_DELAY_NS | 0.6
BOARD_LPDDR3_MAX_DQS_DELAY_NS | 0.6
BOARD_LPDDR3_TIS_DERATING_PS | 0
BOARD_LPDDR3_TIH_DERATING_PS | 0
BOARD_LPDDR3_TDS_DERATING_PS | 0
BOARD_LPDDR3_TDH_DERATING_PS | 0
BOARD_LPDDR3_CK_SLEW_RATE | 4.0
BOARD_LPDDR3_AC_SLEW_RATE | 2.0
BOARD_LPDDR3_RCLK_SLEW_RATE | 4.0
BOARD_LPDDR3_WCLK_SLEW_RATE | 4.0
BOARD_LPDDR3_RDATA_SLEW_RATE | 2.0
BOARD_LPDDR3_WDATA_SLEW_RATE | 2.0
BOARD_LPDDR3_AC_ISI_NS | 0.0
BOARD_LPDDR3_RCLK_ISI_NS | 0.0
BOARD_LPDDR3_WCLK_ISI_NS | 0.0
BOARD_LPDDR3_RDATA_ISI_NS | 0.0
BOARD_LPDDR3_WDATA_ISI_NS | 0.0
BOARD_LPDDR3_SKEW_WITHIN_DQS_NS | 0.0
BOARD_LPDDR3_SKEW_WITHIN_AC_NS | 0.0
CTRL_ECC_EN | false
CTRL_MMR_EN | false
CTRL_AUTO_PRECHARGE_EN | false
CTRL_USER_PRIORITY_EN | false
CTRL_DDR3_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_DDR3_SELF_REFRESH_EN | false
CTRL_DDR3_AUTO_POWER_DOWN_EN | false
CTRL_DDR3_AUTO_POWER_DOWN_CYCS | 32
CTRL_DDR3_USER_REFRESH_EN | false
CTRL_DDR3_USER_PRIORITY_EN | false
CTRL_DDR3_AUTO_PRECHARGE_EN | false
CTRL_DDR3_ADDR_ORDER_ENUM | DDR3_CTRL_ADDR_ORDER_CS_R_B_C
CTRL_DDR3_ECC_EN | false
CTRL_DDR3_ECC_AUTO_CORRECTION_EN | false
CTRL_DDR3_REORDER_EN | true
CTRL_DDR3_STARVE_LIMIT | 10
CTRL_DDR3_MMR_EN | false
CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS | 0
CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS | 0
CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR4_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_DDR4_SELF_REFRESH_EN | false
CTRL_DDR4_AUTO_POWER_DOWN_EN | false
CTRL_DDR4_AUTO_POWER_DOWN_CYCS | 32
CTRL_DDR4_USER_REFRESH_EN | false
CTRL_DDR4_USER_PRIORITY_EN | false
CTRL_DDR4_AUTO_PRECHARGE_EN | false
CTRL_DDR4_ADDR_ORDER_ENUM | DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG
CTRL_DDR4_ECC_EN | false
CTRL_DDR4_ECC_AUTO_CORRECTION_EN | false
CTRL_DDR4_REORDER_EN | true
CTRL_DDR4_STARVE_LIMIT | 10
CTRL_DDR4_MMR_EN | false
CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS | 0
CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS | 0
CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
CTRL_QDR2_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_QDR2_AVL_MAX_BURST_COUNT | 4
CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS | false
CTRL_QDR2_AVL_SYMBOL_WIDTH | 9
CTRL_QDR4_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_QDR4_AVL_MAX_BURST_COUNT | 4
CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS | false
CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC | 0
CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC | 0
CTRL_QDR4_AVL_SYMBOL_WIDTH | 9
CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC | 4
CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC | 11
CTRL_RLD2_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_RLD3_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_RLD3_ADDR_ORDER_ENUM | RLD3_CTRL_ADDR_ORDER_CS_R_B_C
CTRL_LPDDR3_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_LPDDR3_SELF_REFRESH_EN | false
CTRL_LPDDR3_AUTO_POWER_DOWN_EN | false
CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS | 32
CTRL_LPDDR3_USER_REFRESH_EN | false
CTRL_LPDDR3_USER_PRIORITY_EN | false
CTRL_LPDDR3_AUTO_PRECHARGE_EN | false
CTRL_LPDDR3_ADDR_ORDER_ENUM | LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C
CTRL_LPDDR3_REORDER_EN | true
CTRL_LPDDR3_STARVE_LIMIT | 10
CTRL_LPDDR3_MMR_EN | false
CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS | 0
CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS | 0
CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
DIAG_SIM_REGTEST_MODE | false
DIAG_TIMING_REGTEST_MODE | false
DIAG_SYNTH_FOR_SIM | false
DIAG_FAST_SIM_OVERRIDE | FAST_SIM_OVERRIDE_DEFAULT
DIAG_VERBOSE_IOAUX | false
DIAG_ECLIPSE_DEBUG | false
DIAG_EXPORT_VJI | false
DIAG_ENABLE_JTAG_UART | false
DIAG_ENABLE_JTAG_UART_HEX | false
DIAG_ENABLE_HPS_EMIF_DEBUG | false
DIAG_SOFT_NIOS_MODE | SOFT_NIOS_MODE_DISABLED
DIAG_SOFT_NIOS_CLOCK_FREQUENCY | 100
DIAG_USE_RS232_UART | false
DIAG_RS232_UART_BAUDRATE | 57600
DIAG_EX_DESIGN_ADD_TEST_EMIFS |
DIAG_EX_DESIGN_SEPARATE_RESETS | false
DIAG_EXPOSE_DFT_SIGNALS | false
DIAG_EXTRA_CONFIGS |
DIAG_USE_BOARD_DELAY_MODEL | false
DIAG_BOARD_DELAY_CONFIG_STR |
DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE | false
DIAG_TG_AVL_2_NUM_CFG_INTERFACES | 0
SHORT_QSYS_INTERFACE_NAMES | true
DIAG_EXT_DOCS | false
DIAG_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_EXPORT_SEQ_AVALON_MASTER | false
DIAG_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_EX_DESIGN_SEPARATE_RZQS | false
DIAG_EX_DESIGN_ISSP_EN | true
DIAG_INTERFACE_ID | 0
DIAG_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_FAST_SIM | true
DIAG_USE_TG_AVL_2 | false
DIAG_USE_ABSTRACT_PHY | false
DIAG_TG_DATA_PATTERN_LENGTH | 8
DIAG_TG_BE_PATTERN_LENGTH | 8
DIAG_BYPASS_DEFAULT_PATTERN | false
DIAG_BYPASS_USER_STAGE | true
DIAG_BYPASS_REPEAT_STAGE | true
DIAG_BYPASS_STRESS_STAGE | true
DIAG_ENABLE_SOFT_M20K | true
DIAG_DDR3_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER | false
DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS | false
DIAG_DDR3_EX_DESIGN_ISSP_EN | true
DIAG_DDR3_INTERFACE_ID | 0
DIAG_DDR3_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_DDR3_USE_TG_AVL_2 | false
DIAG_DDR3_ABSTRACT_PHY | false
DIAG_DDR3_BYPASS_DEFAULT_PATTERN | false
DIAG_DDR3_BYPASS_USER_STAGE | true
DIAG_DDR3_BYPASS_REPEAT_STAGE | true
DIAG_DDR3_BYPASS_STRESS_STAGE | true
DIAG_DDR3_TG_DATA_PATTERN_LENGTH | 8
DIAG_DDR3_TG_BE_PATTERN_LENGTH | 8
DIAG_DDR3_SEPARATE_READ_WRITE_ITFS | false
DIAG_DDR3_CA_LEVEL_EN | false
DIAG_DDR3_CAL_ADDR0 | 0
DIAG_DDR3_CAL_ADDR1 | 8
DIAG_DDR3_CAL_ENABLE_NON_DES | false
DIAG_DDR3_CAL_FULL_CAL_ON_RESET | true
DIAG_DDR4_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER | false
DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS | false
DIAG_DDR4_EX_DESIGN_ISSP_EN | true
DIAG_DDR4_INTERFACE_ID | 0
DIAG_DDR4_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_DDR4_USE_TG_AVL_2 | false
DIAG_DDR4_ABSTRACT_PHY | false
DIAG_DDR4_BYPASS_DEFAULT_PATTERN | false
DIAG_DDR4_BYPASS_USER_STAGE | true
DIAG_DDR4_BYPASS_REPEAT_STAGE | true
DIAG_DDR4_BYPASS_STRESS_STAGE | true
DIAG_DDR4_TG_DATA_PATTERN_LENGTH | 8
DIAG_DDR4_TG_BE_PATTERN_LENGTH | 8
DIAG_DDR4_SEPARATE_READ_WRITE_ITFS | false
DIAG_DDR4_SKIP_CA_LEVEL | false
DIAG_DDR4_SKIP_CA_DESKEW | false
DIAG_DDR4_SKIP_VREF_CAL | false
DIAG_DDR4_CAL_ADDR0 | 0
DIAG_DDR4_CAL_ADDR1 | 8
DIAG_DDR4_CAL_ENABLE_NON_DES | false
DIAG_DDR4_CAL_FULL_CAL_ON_RESET | true
DIAG_QDR2_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER | false
DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS | false
DIAG_QDR2_EX_DESIGN_ISSP_EN | true
DIAG_QDR2_INTERFACE_ID | 0
DIAG_QDR2_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_QDR2_USE_TG_AVL_2 | false
DIAG_QDR2_ABSTRACT_PHY | false
DIAG_QDR2_BYPASS_DEFAULT_PATTERN | false
DIAG_QDR2_BYPASS_USER_STAGE | true
DIAG_QDR2_BYPASS_REPEAT_STAGE | true
DIAG_QDR2_BYPASS_STRESS_STAGE | true
DIAG_QDR2_TG_DATA_PATTERN_LENGTH | 8
DIAG_QDR2_TG_BE_PATTERN_LENGTH | 8
DIAG_QDR2_SEPARATE_READ_WRITE_ITFS | false
DIAG_QDR4_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER | false
DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS | false
DIAG_QDR4_EX_DESIGN_ISSP_EN | true
DIAG_QDR4_INTERFACE_ID | 0
DIAG_QDR4_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_QDR4_USE_TG_AVL_2 | false
DIAG_QDR4_ABSTRACT_PHY | false
DIAG_QDR4_BYPASS_DEFAULT_PATTERN | false
DIAG_QDR4_BYPASS_USER_STAGE | true
DIAG_QDR4_BYPASS_REPEAT_STAGE | true
DIAG_QDR4_BYPASS_STRESS_STAGE | true
DIAG_QDR4_TG_DATA_PATTERN_LENGTH | 8
DIAG_QDR4_TG_BE_PATTERN_LENGTH | 8
DIAG_QDR4_SEPARATE_READ_WRITE_ITFS | false
DIAG_QDR4_SKIP_VREF_CAL | false
DIAG_RLD2_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER | false
DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS | false
DIAG_RLD2_EX_DESIGN_ISSP_EN | true
DIAG_RLD2_INTERFACE_ID | 0
DIAG_RLD2_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_RLD2_USE_TG_AVL_2 | false
DIAG_RLD2_ABSTRACT_PHY | false
DIAG_RLD2_BYPASS_DEFAULT_PATTERN | false
DIAG_RLD2_BYPASS_USER_STAGE | true
DIAG_RLD2_BYPASS_REPEAT_STAGE | true
DIAG_RLD2_BYPASS_STRESS_STAGE | true
DIAG_RLD2_TG_DATA_PATTERN_LENGTH | 8
DIAG_RLD2_TG_BE_PATTERN_LENGTH | 8
DIAG_RLD2_SEPARATE_READ_WRITE_ITFS | false
DIAG_RLD3_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER | false
DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS | false
DIAG_RLD3_EX_DESIGN_ISSP_EN | true
DIAG_RLD3_INTERFACE_ID | 0
DIAG_RLD3_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_RLD3_USE_TG_AVL_2 | false
DIAG_RLD3_ABSTRACT_PHY | false
DIAG_RLD3_BYPASS_DEFAULT_PATTERN | false
DIAG_RLD3_BYPASS_USER_STAGE | true
DIAG_RLD3_BYPASS_REPEAT_STAGE | true
DIAG_RLD3_BYPASS_STRESS_STAGE | true
DIAG_RLD3_TG_DATA_PATTERN_LENGTH | 8
DIAG_RLD3_TG_BE_PATTERN_LENGTH | 8
DIAG_RLD3_SEPARATE_READ_WRITE_ITFS | false
DIAG_LPDDR3_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER | false
DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS | false
DIAG_LPDDR3_EX_DESIGN_ISSP_EN | true
DIAG_LPDDR3_INTERFACE_ID | 0
DIAG_LPDDR3_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_LPDDR3_USE_TG_AVL_2 | false
DIAG_LPDDR3_ABSTRACT_PHY | false
DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN | false
DIAG_LPDDR3_BYPASS_USER_STAGE | true
DIAG_LPDDR3_BYPASS_REPEAT_STAGE | true
DIAG_LPDDR3_BYPASS_STRESS_STAGE | true
DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH | 8
DIAG_LPDDR3_TG_BE_PATTERN_LENGTH | 8
DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS | false
DIAG_LPDDR3_SKIP_CA_LEVEL | false
DIAG_LPDDR3_SKIP_CA_DESKEW | false
EX_DESIGN_GUI_GEN_SIM | true
EX_DESIGN_GUI_GEN_SYNTH | true
EX_DESIGN_GUI_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR3_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_DDR3_GEN_SIM | false
EX_DESIGN_GUI_DDR3_GEN_SYNTH | true
EX_DESIGN_GUI_DDR3_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR3_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR4_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_DDR4_GEN_SIM | false
EX_DESIGN_GUI_DDR4_GEN_SYNTH | true
EX_DESIGN_GUI_DDR4_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR4_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR2_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_QDR2_GEN_SIM | true
EX_DESIGN_GUI_QDR2_GEN_SYNTH | true
EX_DESIGN_GUI_QDR2_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR2_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR4_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_QDR4_GEN_SIM | true
EX_DESIGN_GUI_QDR4_GEN_SYNTH | true
EX_DESIGN_GUI_QDR4_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR4_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD2_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_RLD2_GEN_SIM | true
EX_DESIGN_GUI_RLD2_GEN_SYNTH | true
EX_DESIGN_GUI_RLD2_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD2_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD3_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_RLD3_GEN_SIM | true
EX_DESIGN_GUI_RLD3_GEN_SYNTH | true
EX_DESIGN_GUI_RLD3_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD3_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_LPDDR3_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_LPDDR3_GEN_SIM | true
EX_DESIGN_GUI_LPDDR3_GEN_SYNTH | true
EX_DESIGN_GUI_LPDDR3_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_LPDDR3_PREV_PRESET | TARGET_DEV_KIT_NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## system_emif_0_arch

altera_emif_arch_nf v16.1

|  | system_emif_0_arch | cal_slave_clk | system_emif_0_cal_slave_component_clk_bridge
|  | in_clk
|  | cal_slave_reset_n | system_emif_0_cal_slave_component_rst_bridge
|  | in_reset
|  | cal_master | system_emif_0_cal_slave_component_ioaux_master_bridge
|  | s0

## Parameters
SYS_INFO_DEVICE_FAMILY | Arria 10
SYS_INFO_DEVICE | 10AX115R4F40I3SG
SYS_INFO_DEVICE_SPEEDGRADE | 3
FAMILY_ENUM | FAMILY_ARRIA10
TRAIT_SUPPORTS_VID | 0
PROTOCOL_ENUM | PROTOCOL_DDR4
IS_ED_SLAVE | false
INTERNAL_TESTING_MODE | false
CAL_DEBUG_CLOCK_FREQUENCY | 50000000
SYS_INFO_UNIQUE_ID | system_emif_0_system_emif_0
PREV_PROTOCOL_ENUM | PROTOCOL_DDR4
PHY_FPGA_SPEEDGRADE_GUI | I3 (Production) - change device under 'View'->'Device Family'
PHY_TARGET_SPEEDGRADE | I3
PHY_TARGET_IS_ES | false
PHY_TARGET_IS_ES2 | false
PHY_TARGET_IS_ES3 | false
PHY_TARGET_IS_PRODUCTION | true
PHY_CONFIG_ENUM | CONFIG_PHY_AND_HARD_CTRL
PHY_PING_PONG_EN | false
PHY_RATE_ENUM | RATE_QUARTER
PHY_MEM_CLK_FREQ_MHZ | 800.0
PHY_REF_CLK_FREQ_MHZ | 200.0
PHY_REF_CLK_JITTER_PS | 10.0
PHY_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_CALIBRATED_OCT | true
PHY_AC_CALIBRATED_OCT | true
PHY_CK_CALIBRATED_OCT | true
PHY_DATA_CALIBRATED_OCT | true
PHY_RZQ | 240
PHY_HPS_ENABLE_EARLY_RELEASE | false
PHY_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PLL_VCO_CLK_FREQ_MHZ | 800.0
PLL_SPEEDGRADE | 3
PLL_DISALLOW_EXTRA_CLKS | false
PLL_NUM_OF_EXTRA_CLKS | 0
PLL_MAPPED_SYS_INFO_DEVICE_FAMILY | Arria 10
PLL_MAPPED_SYS_INFO_DEVICE | 10AX115R4F40I3SG
PLL_MAPPED_SYS_INFO_DEVICE_SPEEDGRADE | 3
PLL_MAPPED_REFERENCE_CLOCK_FREQUENCY | 200.0
PLL_MAPPED_VCO_FREQUENCY | 800.0 MHz
PLL_MAPPED_EXTERNAL_PLL_MODE | false
PLL_ADD_EXTRA_CLKS | 0
PLL_COMPENSATION_MODE | emif
PLL_USER_NUM_OF_EXTRA_CLKS | 0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 | 200.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 | 200.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_0 | 200.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 | 313.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 | 313
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 | 22.5
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_0 | 312.5
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 | 50
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 | 400.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 | 400.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_1 | 400.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 | 313.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 | 313
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 | 45.1
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_1 | 312.5
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 | 50
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 | 200.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 | 200.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_2 | 200.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 | 313.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 | 313
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 | 22.5
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_2 | 312.5
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 | 50
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 | 160.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 | 160.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_3 | 160.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 | 0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_3 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 | 50
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 | 160.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 | 160.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_4 | 160.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 | 0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_4 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 | 50
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_5 | 100.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_5 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_6 | 100.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_6 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_7 | 100.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_7 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 | 50.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 | 100.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_8 | 100.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 | 0
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 | 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_8 | 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 | 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 | 50.0
PHY_DDR3_CONFIG_ENUM | CONFIG_PHY_AND_HARD_CTRL
PHY_DDR3_USER_PING_PONG_EN | false
PHY_DDR3_MEM_CLK_FREQ_MHZ | 800.0
PHY_DDR3_DEFAULT_REF_CLK_FREQ | true
PHY_DDR3_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_DDR3_REF_CLK_JITTER_PS | 10.0
PHY_DDR3_RATE_ENUM | RATE_QUARTER
PHY_DDR3_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_DDR3_IO_VOLTAGE | 1.5
PHY_DDR3_DEFAULT_IO | true
PHY_DDR3_HPS_ENABLE_EARLY_RELEASE | false
PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_DDR3_REF_CLK_FREQ_MHZ | -1.0
PHY_DDR3_PING_PONG_EN | false
PHY_DDR3_USER_AC_IO_STD_ENUM | unset
PHY_DDR3_USER_AC_MODE_ENUM | unset
PHY_DDR3_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR3_USER_CK_IO_STD_ENUM | unset
PHY_DDR3_USER_CK_MODE_ENUM | unset
PHY_DDR3_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR3_USER_DATA_IO_STD_ENUM | unset
PHY_DDR3_USER_DATA_OUT_MODE_ENUM | unset
PHY_DDR3_USER_DATA_IN_MODE_ENUM | unset
PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN | true
PHY_DDR3_USER_STARTING_VREFIN | 70.0
PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_DDR3_USER_RZQ_IO_STD_ENUM | unset
PHY_DDR3_AC_IO_STD_ENUM | unset
PHY_DDR3_AC_MODE_ENUM | unset
PHY_DDR3_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR3_CK_IO_STD_ENUM | unset
PHY_DDR3_CK_MODE_ENUM | unset
PHY_DDR3_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR3_DATA_IO_STD_ENUM | unset
PHY_DDR3_DATA_OUT_MODE_ENUM | unset
PHY_DDR3_DATA_IN_MODE_ENUM | unset
PHY_DDR3_AUTO_STARTING_VREFIN_EN | true
PHY_DDR3_STARTING_VREFIN | 70.0
PHY_DDR3_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_DDR3_RZQ_IO_STD_ENUM | unset
PHY_DDR3_CAL_ADDR0 | 0
PHY_DDR3_CAL_ADDR1 | 8
PHY_DDR3_CAL_ENABLE_NON_DES | false
PHY_DDR4_CONFIG_ENUM | CONFIG_PHY_AND_HARD_CTRL
PHY_DDR4_USER_PING_PONG_EN | false
PHY_DDR4_MEM_CLK_FREQ_MHZ | 800.0
PHY_DDR4_DEFAULT_REF_CLK_FREQ | true
PHY_DDR4_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_DDR4_REF_CLK_JITTER_PS | 10.0
PHY_DDR4_RATE_ENUM | RATE_QUARTER
PHY_DDR4_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_DDR4_IO_VOLTAGE | 1.2
PHY_DDR4_DEFAULT_IO | true
PHY_DDR4_HPS_ENABLE_EARLY_RELEASE | false
PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_DDR4_REF_CLK_FREQ_MHZ | 200.0
PHY_DDR4_PING_PONG_EN | false
PHY_DDR4_USER_AC_IO_STD_ENUM | unset
PHY_DDR4_USER_AC_MODE_ENUM | unset
PHY_DDR4_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR4_USER_CK_IO_STD_ENUM | unset
PHY_DDR4_USER_CK_MODE_ENUM | unset
PHY_DDR4_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR4_USER_DATA_IO_STD_ENUM | unset
PHY_DDR4_USER_DATA_OUT_MODE_ENUM | unset
PHY_DDR4_USER_DATA_IN_MODE_ENUM | unset
PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN | true
PHY_DDR4_USER_STARTING_VREFIN | 70.0
PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_DDR4_USER_RZQ_IO_STD_ENUM | unset
PHY_DDR4_AC_IO_STD_ENUM | IO_STD_SSTL_12
PHY_DDR4_AC_MODE_ENUM | OUT_OCT_40_CAL
PHY_DDR4_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR4_CK_IO_STD_ENUM | IO_STD_SSTL_12
PHY_DDR4_CK_MODE_ENUM | OUT_OCT_40_CAL
PHY_DDR4_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_DDR4_DATA_IO_STD_ENUM | IO_STD_POD_12
PHY_DDR4_DATA_OUT_MODE_ENUM | OUT_OCT_34_CAL
PHY_DDR4_DATA_IN_MODE_ENUM | IN_OCT_120_CAL
PHY_DDR4_AUTO_STARTING_VREFIN_EN | true
PHY_DDR4_STARTING_VREFIN | 61.0
PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM | IO_STD_LVDS
PHY_DDR4_RZQ_IO_STD_ENUM | IO_STD_CMOS_12
PHY_QDR2_CONFIG_ENUM | CONFIG_PHY_AND_SOFT_CTRL
PHY_QDR2_USER_PING_PONG_EN | false
PHY_QDR2_MEM_CLK_FREQ_MHZ | 633.333
PHY_QDR2_DEFAULT_REF_CLK_FREQ | true
PHY_QDR2_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_QDR2_REF_CLK_JITTER_PS | 10.0
PHY_QDR2_RATE_ENUM | RATE_HALF
PHY_QDR2_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_QDR2_IO_VOLTAGE | 1.5
PHY_QDR2_DEFAULT_IO | true
PHY_QDR2_HPS_ENABLE_EARLY_RELEASE | false
PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_QDR2_REF_CLK_FREQ_MHZ | -1.0
PHY_QDR2_PING_PONG_EN | false
PHY_QDR2_USER_AC_IO_STD_ENUM | unset
PHY_QDR2_USER_AC_MODE_ENUM | unset
PHY_QDR2_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR2_USER_CK_IO_STD_ENUM | unset
PHY_QDR2_USER_CK_MODE_ENUM | unset
PHY_QDR2_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR2_USER_DATA_IO_STD_ENUM | unset
PHY_QDR2_USER_DATA_OUT_MODE_ENUM | unset
PHY_QDR2_USER_DATA_IN_MODE_ENUM | unset
PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN | true
PHY_QDR2_USER_STARTING_VREFIN | 70.0
PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_QDR2_USER_RZQ_IO_STD_ENUM | unset
PHY_QDR2_AC_IO_STD_ENUM | unset
PHY_QDR2_AC_MODE_ENUM | unset
PHY_QDR2_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR2_CK_IO_STD_ENUM | unset
PHY_QDR2_CK_MODE_ENUM | unset
PHY_QDR2_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR2_DATA_IO_STD_ENUM | unset
PHY_QDR2_DATA_OUT_MODE_ENUM | unset
PHY_QDR2_DATA_IN_MODE_ENUM | unset
PHY_QDR2_AUTO_STARTING_VREFIN_EN | true
PHY_QDR2_STARTING_VREFIN | 70.0
PHY_QDR2_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_QDR2_RZQ_IO_STD_ENUM | unset
PHY_QDR4_CONFIG_ENUM | CONFIG_PHY_AND_SOFT_CTRL
PHY_QDR4_USER_PING_PONG_EN | false
PHY_QDR4_MEM_CLK_FREQ_MHZ | 1066.667
PHY_QDR4_DEFAULT_REF_CLK_FREQ | true
PHY_QDR4_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_QDR4_REF_CLK_JITTER_PS | 10.0
PHY_QDR4_RATE_ENUM | RATE_QUARTER
PHY_QDR4_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_QDR4_IO_VOLTAGE | 1.2
PHY_QDR4_DEFAULT_IO | true
PHY_QDR4_HPS_ENABLE_EARLY_RELEASE | false
PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_QDR4_REF_CLK_FREQ_MHZ | -1.0
PHY_QDR4_PING_PONG_EN | false
PHY_QDR4_USER_AC_IO_STD_ENUM | unset
PHY_QDR4_USER_AC_MODE_ENUM | unset
PHY_QDR4_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR4_USER_CK_IO_STD_ENUM | unset
PHY_QDR4_USER_CK_MODE_ENUM | unset
PHY_QDR4_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR4_USER_DATA_IO_STD_ENUM | unset
PHY_QDR4_USER_DATA_OUT_MODE_ENUM | unset
PHY_QDR4_USER_DATA_IN_MODE_ENUM | unset
PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN | true
PHY_QDR4_USER_STARTING_VREFIN | 70.0
PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_QDR4_USER_RZQ_IO_STD_ENUM | unset
PHY_QDR4_AC_IO_STD_ENUM | unset
PHY_QDR4_AC_MODE_ENUM | unset
PHY_QDR4_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR4_CK_IO_STD_ENUM | unset
PHY_QDR4_CK_MODE_ENUM | unset
PHY_QDR4_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_QDR4_DATA_IO_STD_ENUM | unset
PHY_QDR4_DATA_OUT_MODE_ENUM | unset
PHY_QDR4_DATA_IN_MODE_ENUM | unset
PHY_QDR4_AUTO_STARTING_VREFIN_EN | true
PHY_QDR4_STARTING_VREFIN | 70.0
PHY_QDR4_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_QDR4_RZQ_IO_STD_ENUM | unset
PHY_RLD2_CONFIG_ENUM | CONFIG_PHY_AND_SOFT_CTRL
PHY_RLD2_USER_PING_PONG_EN | false
PHY_RLD2_MEM_CLK_FREQ_MHZ | 533.333
PHY_RLD2_DEFAULT_REF_CLK_FREQ | true
PHY_RLD2_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_RLD2_REF_CLK_JITTER_PS | 10.0
PHY_RLD2_RATE_ENUM | RATE_HALF
PHY_RLD2_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_RLD2_IO_VOLTAGE | 1.8
PHY_RLD2_DEFAULT_IO | true
PHY_RLD2_HPS_ENABLE_EARLY_RELEASE | false
PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_RLD2_REF_CLK_FREQ_MHZ | -1.0
PHY_RLD2_PING_PONG_EN | false
PHY_RLD2_USER_AC_IO_STD_ENUM | unset
PHY_RLD2_USER_AC_MODE_ENUM | unset
PHY_RLD2_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD2_USER_CK_IO_STD_ENUM | unset
PHY_RLD2_USER_CK_MODE_ENUM | unset
PHY_RLD2_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD2_USER_DATA_IO_STD_ENUM | unset
PHY_RLD2_USER_DATA_OUT_MODE_ENUM | unset
PHY_RLD2_USER_DATA_IN_MODE_ENUM | unset
PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN | true
PHY_RLD2_USER_STARTING_VREFIN | 70.0
PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_RLD2_USER_RZQ_IO_STD_ENUM | unset
PHY_RLD2_AC_IO_STD_ENUM | unset
PHY_RLD2_AC_MODE_ENUM | unset
PHY_RLD2_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD2_CK_IO_STD_ENUM | unset
PHY_RLD2_CK_MODE_ENUM | unset
PHY_RLD2_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD2_DATA_IO_STD_ENUM | unset
PHY_RLD2_DATA_OUT_MODE_ENUM | unset
PHY_RLD2_DATA_IN_MODE_ENUM | unset
PHY_RLD2_AUTO_STARTING_VREFIN_EN | true
PHY_RLD2_STARTING_VREFIN | 70.0
PHY_RLD2_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_RLD2_RZQ_IO_STD_ENUM | unset
PHY_RLD3_CONFIG_ENUM | CONFIG_PHY_ONLY
PHY_RLD3_USER_PING_PONG_EN | false
PHY_RLD3_MEM_CLK_FREQ_MHZ | 1066.667
PHY_RLD3_DEFAULT_REF_CLK_FREQ | true
PHY_RLD3_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_RLD3_REF_CLK_JITTER_PS | 10.0
PHY_RLD3_RATE_ENUM | RATE_QUARTER
PHY_RLD3_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_RLD3_IO_VOLTAGE | 1.2
PHY_RLD3_DEFAULT_IO | true
PHY_RLD3_HPS_ENABLE_EARLY_RELEASE | false
PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_RLD3_REF_CLK_FREQ_MHZ | -1.0
PHY_RLD3_PING_PONG_EN | false
PHY_RLD3_USER_AC_IO_STD_ENUM | unset
PHY_RLD3_USER_AC_MODE_ENUM | unset
PHY_RLD3_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD3_USER_CK_IO_STD_ENUM | unset
PHY_RLD3_USER_CK_MODE_ENUM | unset
PHY_RLD3_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD3_USER_DATA_IO_STD_ENUM | unset
PHY_RLD3_USER_DATA_OUT_MODE_ENUM | unset
PHY_RLD3_USER_DATA_IN_MODE_ENUM | unset
PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN | true
PHY_RLD3_USER_STARTING_VREFIN | 70.0
PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_RLD3_USER_RZQ_IO_STD_ENUM | unset
PHY_RLD3_AC_IO_STD_ENUM | unset
PHY_RLD3_AC_MODE_ENUM | unset
PHY_RLD3_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD3_CK_IO_STD_ENUM | unset
PHY_RLD3_CK_MODE_ENUM | unset
PHY_RLD3_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_RLD3_DATA_IO_STD_ENUM | unset
PHY_RLD3_DATA_OUT_MODE_ENUM | unset
PHY_RLD3_DATA_IN_MODE_ENUM | unset
PHY_RLD3_AUTO_STARTING_VREFIN_EN | true
PHY_RLD3_STARTING_VREFIN | 70.0
PHY_RLD3_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_RLD3_RZQ_IO_STD_ENUM | unset
PHY_LPDDR3_CONFIG_ENUM | CONFIG_PHY_AND_HARD_CTRL
PHY_LPDDR3_USER_PING_PONG_EN | false
PHY_LPDDR3_MEM_CLK_FREQ_MHZ | 800.0
PHY_LPDDR3_DEFAULT_REF_CLK_FREQ | true
PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ | -1.0
PHY_LPDDR3_REF_CLK_JITTER_PS | 10.0
PHY_LPDDR3_RATE_ENUM | RATE_QUARTER
PHY_LPDDR3_CORE_CLKS_SHARING_ENUM | CORE_CLKS_SHARING_DISABLED
PHY_LPDDR3_IO_VOLTAGE | 1.2
PHY_LPDDR3_DEFAULT_IO | true
PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE | false
PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM | PERIODIC_OCT_RECAL_AUTO
PHY_LPDDR3_REF_CLK_FREQ_MHZ | -1.0
PHY_LPDDR3_PING_PONG_EN | false
PHY_LPDDR3_USER_AC_IO_STD_ENUM | unset
PHY_LPDDR3_USER_AC_MODE_ENUM | unset
PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_LPDDR3_USER_CK_IO_STD_ENUM | unset
PHY_LPDDR3_USER_CK_MODE_ENUM | unset
PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_LPDDR3_USER_DATA_IO_STD_ENUM | unset
PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM | unset
PHY_LPDDR3_USER_DATA_IN_MODE_ENUM | unset
PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN | true
PHY_LPDDR3_USER_STARTING_VREFIN | 70.0
PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_LPDDR3_USER_RZQ_IO_STD_ENUM | unset
PHY_LPDDR3_AC_IO_STD_ENUM | unset
PHY_LPDDR3_AC_MODE_ENUM | unset
PHY_LPDDR3_AC_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_LPDDR3_CK_IO_STD_ENUM | unset
PHY_LPDDR3_CK_MODE_ENUM | unset
PHY_LPDDR3_CK_SLEW_RATE_ENUM | SLEW_RATE_FAST
PHY_LPDDR3_DATA_IO_STD_ENUM | unset
PHY_LPDDR3_DATA_OUT_MODE_ENUM | unset
PHY_LPDDR3_DATA_IN_MODE_ENUM | unset
PHY_LPDDR3_AUTO_STARTING_VREFIN_EN | true
PHY_LPDDR3_STARTING_VREFIN | 70.0
PHY_LPDDR3_PLL_REF_CLK_IO_STD_ENUM | unset
PHY_LPDDR3_RZQ_IO_STD_ENUM | unset
MEM_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_READ_LATENCY | 18.0
MEM_WRITE_LATENCY | 12
MEM_BURST_LENGTH | 8
MEM_DATA_MASK_EN | true
MEM_HAS_SIM_SUPPORT | true
MEM_NUM_OF_LOGICAL_RANKS | 1
MEM_TTL_DATA_WIDTH | 72
MEM_TTL_NUM_OF_READ_GROUPS | 9
MEM_TTL_NUM_OF_WRITE_GROUPS | 9
MEM_DDR3_FORMAT_ENUM | MEM_FORMAT_UDIMM
MEM_DDR3_DQ_WIDTH | 72
MEM_DDR3_DQ_PER_DQS | 8
MEM_DDR3_DISCRETE_CS_WIDTH | 1
MEM_DDR3_NUM_OF_DIMMS | 1
MEM_DDR3_RANKS_PER_DIMM | 1
MEM_DDR3_CKE_PER_DIMM | 1
MEM_DDR3_CK_WIDTH | 1
MEM_DDR3_ROW_ADDR_WIDTH | 15
MEM_DDR3_COL_ADDR_WIDTH | 10
MEM_DDR3_BANK_ADDR_WIDTH | 3
MEM_DDR3_DM_EN | true
MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN | false
MEM_DDR3_MIRROR_ADDRESSING_EN | true
MEM_DDR3_HIDE_ADV_MR_SETTINGS | true
MEM_DDR3_RDIMM_CONFIG | 0000000000000000
MEM_DDR3_LRDIMM_EXTENDED_CONFIG | 000000000000000000
MEM_DDR3_ALERT_N_PLACEMENT_ENUM | DDR3_ALERT_N_PLACEMENT_AC_LANES
MEM_DDR3_ALERT_N_DQS_GROUP | 0
MEM_DDR3_DQS_WIDTH | 8
MEM_DDR3_DM_WIDTH | 1
MEM_DDR3_CS_WIDTH | 1
MEM_DDR3_CS_PER_DIMM | 1
MEM_DDR3_CKE_WIDTH | 1
MEM_DDR3_ODT_WIDTH | 1
MEM_DDR3_ADDR_WIDTH | 1
MEM_DDR3_RM_WIDTH | 0
MEM_DDR3_AC_PAR_EN | false
MEM_DDR3_NUM_OF_PHYSICAL_RANKS | 1
MEM_DDR3_NUM_OF_LOGICAL_RANKS | 1
MEM_DDR3_TTL_DQS_WIDTH | 8
MEM_DDR3_TTL_DQ_WIDTH | 72
MEM_DDR3_TTL_DM_WIDTH | 1
MEM_DDR3_TTL_CS_WIDTH | 1
MEM_DDR3_TTL_CK_WIDTH | 1
MEM_DDR3_TTL_CKE_WIDTH | 1
MEM_DDR3_TTL_ODT_WIDTH | 1
MEM_DDR3_TTL_BANK_ADDR_WIDTH | 3
MEM_DDR3_TTL_ADDR_WIDTH | 1
MEM_DDR3_TTL_RM_WIDTH | 0
MEM_DDR3_TTL_NUM_OF_DIMMS | 1
MEM_DDR3_TTL_NUM_OF_PHYSICAL_RANKS | 1
MEM_DDR3_TTL_NUM_OF_LOGICAL_RANKS | 1
MEM_DDR3_MR0 | 0
MEM_DDR3_MR1 | 0
MEM_DDR3_MR2 | 0
MEM_DDR3_MR3 | 0
MEM_DDR3_ADDRESS_MIRROR_BITVEC | 0
MEM_DDR3_BL_ENUM | DDR3_BL_BL8
MEM_DDR3_BT_ENUM | DDR3_BT_SEQUENTIAL
MEM_DDR3_ASR_ENUM | DDR3_ASR_MANUAL
MEM_DDR3_SRT_ENUM | DDR3_SRT_NORMAL
MEM_DDR3_PD_ENUM | DDR3_PD_OFF
MEM_DDR3_DRV_STR_ENUM | DDR3_DRV_STR_RZQ_7
MEM_DDR3_DLL_EN | true
MEM_DDR3_RTT_NOM_ENUM | DDR3_RTT_NOM_ODT_DISABLED
MEM_DDR3_RTT_WR_ENUM | DDR3_RTT_WR_RZQ_4
MEM_DDR3_WTCL | 10
MEM_DDR3_ATCL_ENUM | DDR3_ATCL_DISABLED
MEM_DDR3_TCL | 14
MEM_DDR3_USE_DEFAULT_ODT | true
MEM_DDR3_R_ODTN_1X1 | Rank 0
MEM_DDR3_R_ODT0_1X1 | off
MEM_DDR3_W_ODTN_1X1 | Rank 0
MEM_DDR3_W_ODT0_1X1 | on
MEM_DDR3_R_ODTN_2X2 | Rank 0,Rank 1
MEM_DDR3_R_ODT0_2X2 | off,off
MEM_DDR3_R_ODT1_2X2 | off,off
MEM_DDR3_W_ODTN_2X2 | Rank 0,Rank 1
MEM_DDR3_W_ODT0_2X2 | on,off
MEM_DDR3_W_ODT1_2X2 | off,on
MEM_DDR3_R_ODTN_4X2 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_R_ODT0_4X2 | off,off,on,on
MEM_DDR3_R_ODT1_4X2 | on,on,off,off
MEM_DDR3_W_ODTN_4X2 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_W_ODT0_4X2 | off,off,on,on
MEM_DDR3_W_ODT1_4X2 | on,on,off,off
MEM_DDR3_R_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_R_ODT0_4X4 | off,off,off,off
MEM_DDR3_R_ODT1_4X4 | off,off,on,on
MEM_DDR3_R_ODT2_4X4 | off,off,off,off
MEM_DDR3_R_ODT3_4X4 | on,on,off,off
MEM_DDR3_W_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_W_ODT0_4X4 | on,on,off,off
MEM_DDR3_W_ODT1_4X4 | off,off,on,on
MEM_DDR3_W_ODT2_4X4 | off,off,on,on
MEM_DDR3_W_ODT3_4X4 | on,on,off,off
MEM_DDR3_R_DERIVED_ODTN | ,
MEM_DDR3_R_DERIVED_ODT0 | ,
MEM_DDR3_R_DERIVED_ODT1 | ,
MEM_DDR3_R_DERIVED_ODT2 | ,
MEM_DDR3_R_DERIVED_ODT3 | ,
MEM_DDR3_W_DERIVED_ODTN | ,
MEM_DDR3_W_DERIVED_ODT0 | ,
MEM_DDR3_W_DERIVED_ODT1 | ,
MEM_DDR3_W_DERIVED_ODT2 | ,
MEM_DDR3_W_DERIVED_ODT3 | ,
MEM_DDR3_SEQ_ODT_TABLE_LO | 0
MEM_DDR3_SEQ_ODT_TABLE_HI | 0
MEM_DDR3_CTRL_CFG_READ_ODT_CHIP | 0
MEM_DDR3_CTRL_CFG_WRITE_ODT_CHIP | 0
MEM_DDR3_CTRL_CFG_READ_ODT_RANK | 0
MEM_DDR3_CTRL_CFG_WRITE_ODT_RANK | 0
MEM_DDR3_SPEEDBIN_ENUM | DDR3_SPEEDBIN_2133
MEM_DDR3_TIS_PS | 60
MEM_DDR3_TIS_AC_MV | 135
MEM_DDR3_TIH_PS | 95
MEM_DDR3_TIH_DC_MV | 100
MEM_DDR3_TDS_PS | 53
MEM_DDR3_TDS_AC_MV | 135
MEM_DDR3_TDH_PS | 55
MEM_DDR3_TDH_DC_MV | 100
MEM_DDR3_TDQSQ_PS | 75
MEM_DDR3_TQH_CYC | 0.38
MEM_DDR3_TDQSCK_PS | 180
MEM_DDR3_TDQSS_CYC | 0.27
MEM_DDR3_TQSH_CYC | 0.4
MEM_DDR3_TDSH_CYC | 0.18
MEM_DDR3_TWLS_PS | 125.0
MEM_DDR3_TWLH_PS | 125.0
MEM_DDR3_TDSS_CYC | 0.18
MEM_DDR3_TINIT_US | 500
MEM_DDR3_TMRD_CK_CYC | 4
MEM_DDR3_TRAS_NS | 33.0
MEM_DDR3_TRCD_NS | 13.09
MEM_DDR3_TRP_NS | 13.09
MEM_DDR3_TREFI_US | 7.8
MEM_DDR3_TRFC_NS | 160.0
MEM_DDR3_TWR_NS | 15.0
MEM_DDR3_TWTR_CYC | 8
MEM_DDR3_TFAW_NS | 25.0
MEM_DDR3_TRRD_CYC | 6
MEM_DDR3_TRTP_CYC | 8
MEM_DDR3_TINIT_CK | 499
MEM_DDR3_TDQSCK_DERV_PS | 2
MEM_DDR3_TDQSCKDS | 450
MEM_DDR3_TDQSCKDM | 900
MEM_DDR3_TDQSCKDL | 1200
MEM_DDR3_TRAS_CYC | 36
MEM_DDR3_TRCD_CYC | 14
MEM_DDR3_TRP_CYC | 14
MEM_DDR3_TRFC_CYC | 171
MEM_DDR3_TWR_CYC | 16
MEM_DDR3_TFAW_CYC | 27
MEM_DDR3_TREFI_CYC | 8320
MEM_DDR3_CFG_GEN_SBE | false
MEM_DDR3_CFG_GEN_DBE | false
MEM_DDR4_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_DDR4_DQ_WIDTH | 72
MEM_DDR4_DQ_PER_DQS | 8
MEM_DDR4_DISCRETE_CS_WIDTH | 1
MEM_DDR4_NUM_OF_DIMMS | 1
MEM_DDR4_RANKS_PER_DIMM | 1
MEM_DDR4_CKE_PER_DIMM | 1
MEM_DDR4_CK_WIDTH | 1
MEM_DDR4_ROW_ADDR_WIDTH | 15
MEM_DDR4_COL_ADDR_WIDTH | 10
MEM_DDR4_BANK_ADDR_WIDTH | 2
MEM_DDR4_BANK_GROUP_WIDTH | 2
MEM_DDR4_CHIP_ID_WIDTH | 0
MEM_DDR4_DM_EN | true
MEM_DDR4_ALERT_PAR_EN | true
MEM_DDR4_ALERT_N_PLACEMENT_ENUM | DDR4_ALERT_N_PLACEMENT_AUTO
MEM_DDR4_ALERT_N_DQS_GROUP | 0
MEM_DDR4_ALERT_N_AC_LANE | 0
MEM_DDR4_ALERT_N_AC_PIN | 0
MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN | false
MEM_DDR4_MIRROR_ADDRESSING_EN | true
MEM_DDR4_HIDE_ADV_MR_SETTINGS | true
MEM_DDR4_BL_ENUM | DDR4_BL_BL8
MEM_DDR4_BT_ENUM | DDR4_BT_SEQUENTIAL
MEM_DDR4_TCL | 18
MEM_DDR4_RTT_NOM_ENUM | DDR4_RTT_NOM_RZQ_4
MEM_DDR4_DLL_EN | true
MEM_DDR4_ATCL_ENUM | DDR4_ATCL_DISABLED
MEM_DDR4_DRV_STR_ENUM | DDR4_DRV_STR_RZQ_7
MEM_DDR4_ASR_ENUM | DDR4_ASR_MANUAL_NORMAL
MEM_DDR4_RTT_WR_ENUM | DDR4_RTT_WR_ODT_DISABLED
MEM_DDR4_WTCL | 12
MEM_DDR4_WRITE_CRC | false
MEM_DDR4_GEARDOWN | DDR4_GEARDOWN_HR
MEM_DDR4_PER_DRAM_ADDR | false
MEM_DDR4_TEMP_SENSOR_READOUT | false
MEM_DDR4_FINE_GRANULARITY_REFRESH | DDR4_FINE_REFRESH_FIXED_1X
MEM_DDR4_MPR_READ_FORMAT | DDR4_MPR_READ_FORMAT_SERIAL
MEM_DDR4_MAX_POWERDOWN | false
MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE | DDR4_TEMP_CONTROLLED_RFSH_NORMAL
MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA | false
MEM_DDR4_INTERNAL_VREFDQ_MONITOR | false
MEM_DDR4_CAL_MODE | 0
MEM_DDR4_SELF_RFSH_ABORT | false
MEM_DDR4_READ_PREAMBLE_TRAINING | false
MEM_DDR4_READ_PREAMBLE | 2
MEM_DDR4_WRITE_PREAMBLE | 1
MEM_DDR4_AC_PARITY_LATENCY | DDR4_AC_PARITY_LATENCY_DISABLE
MEM_DDR4_ODT_IN_POWERDOWN | true
MEM_DDR4_RTT_PARK | DDR4_RTT_PARK_ODT_DISABLED
MEM_DDR4_AC_PERSISTENT_ERROR | false
MEM_DDR4_WRITE_DBI | false
MEM_DDR4_READ_DBI | true
MEM_DDR4_DEFAULT_VREFOUT | true
MEM_DDR4_USER_VREFDQ_TRAINING_VALUE | 56.0
MEM_DDR4_USER_VREFDQ_TRAINING_RANGE | DDR4_VREFDQ_TRAINING_RANGE_1
MEM_DDR4_RCD_CA_IBT_ENUM | DDR4_RCD_CA_IBT_100
MEM_DDR4_RCD_CS_IBT_ENUM | DDR4_RCD_CS_IBT_100
MEM_DDR4_RCD_CKE_IBT_ENUM | DDR4_RCD_CKE_IBT_100
MEM_DDR4_RCD_ODT_IBT_ENUM | DDR4_RCD_ODT_IBT_100
MEM_DDR4_DB_RTT_NOM_ENUM | DDR4_DB_RTT_NOM_ODT_DISABLED
MEM_DDR4_DB_RTT_WR_ENUM | DDR4_DB_RTT_WR_RZQ_3
MEM_DDR4_DB_RTT_PARK_ENUM | DDR4_DB_RTT_PARK_ODT_DISABLED
MEM_DDR4_DB_DQ_DRV_ENUM | DDR4_DB_DRV_STR_RZQ_7
MEM_DDR4_SPD_137_RCD_CA_DRV | 101
MEM_DDR4_SPD_138_RCD_CK_DRV | 5
MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 | 29
MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 | 29
MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 | 29
MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 | 29
MEM_DDR4_SPD_144_DB_VREFDQ | 37
MEM_DDR4_SPD_145_DB_MDQ_DRV | 21
MEM_DDR4_SPD_148_DRAM_DRV | 0
MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM | 20
MEM_DDR4_SPD_152_DRAM_RTT_PARK | 39
MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB | 0
MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB | 0
MEM_DDR4_SPD_135_RCD_REV | 0
MEM_DDR4_SPD_139_DB_REV | 0
MEM_DDR4_LRDIMM_ODT_LESS_BS | true
MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM | 240
MEM_DDR4_DQS_WIDTH | 9
MEM_DDR4_CS_WIDTH | 1
MEM_DDR4_CS_PER_DIMM | 1
MEM_DDR4_CKE_WIDTH | 1
MEM_DDR4_ODT_WIDTH | 1
MEM_DDR4_ADDR_WIDTH | 17
MEM_DDR4_RM_WIDTH | 0
MEM_DDR4_NUM_OF_PHYSICAL_RANKS | 1
MEM_DDR4_NUM_OF_LOGICAL_RANKS | 1
MEM_DDR4_VREFDQ_TRAINING_VALUE | 68.0
MEM_DDR4_VREFDQ_TRAINING_RANGE | DDR4_VREFDQ_TRAINING_RANGE_1
MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP | Range 2 - 45% to 77.5%
MEM_DDR4_TTL_DQS_WIDTH | 9
MEM_DDR4_TTL_DQ_WIDTH | 72
MEM_DDR4_TTL_CS_WIDTH | 1
MEM_DDR4_TTL_CK_WIDTH | 1
MEM_DDR4_TTL_CKE_WIDTH | 1
MEM_DDR4_TTL_ODT_WIDTH | 1
MEM_DDR4_TTL_BANK_ADDR_WIDTH | 2
MEM_DDR4_TTL_BANK_GROUP_WIDTH | 2
MEM_DDR4_TTL_CHIP_ID_WIDTH | 0
MEM_DDR4_TTL_ADDR_WIDTH | 17
MEM_DDR4_TTL_RM_WIDTH | 0
MEM_DDR4_TTL_NUM_OF_DIMMS | 1
MEM_DDR4_TTL_NUM_OF_PHYSICAL_RANKS | 1
MEM_DDR4_TTL_NUM_OF_LOGICAL_RANKS | 1
MEM_DDR4_MR0 | 576
MEM_DDR4_MR1 | 65793
MEM_DDR4_MR2 | 131096
MEM_DDR4_MR3 | 197120
MEM_DDR4_MR4 | 264192
MEM_DDR4_MR5 | 332832
MEM_DDR4_MR6 | 395363
MEM_DDR4_RDIMM_CONFIG |
MEM_DDR4_LRDIMM_EXTENDED_CONFIG |
MEM_DDR4_ADDRESS_MIRROR_BITVEC | 0
MEM_DDR4_USE_DEFAULT_ODT | true
MEM_DDR4_R_ODTN_1X1 | Rank 0
MEM_DDR4_R_ODT0_1X1 | off
MEM_DDR4_W_ODTN_1X1 | Rank 0
MEM_DDR4_W_ODT0_1X1 | on
MEM_DDR4_R_ODTN_2X2 | Rank 0,Rank 1
MEM_DDR4_R_ODT0_2X2 | off,off
MEM_DDR4_R_ODT1_2X2 | off,off
MEM_DDR4_W_ODTN_2X2 | Rank 0,Rank 1
MEM_DDR4_W_ODT0_2X2 | on,off
MEM_DDR4_W_ODT1_2X2 | off,on
MEM_DDR4_R_ODTN_4X2 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X2 | off,off,on,on
MEM_DDR4_R_ODT1_4X2 | on,on,off,off
MEM_DDR4_W_ODTN_4X2 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X2 | off,off,on,on
MEM_DDR4_W_ODT1_4X2 | on,on,off,off
MEM_DDR4_R_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X4 | off,off,off,off
MEM_DDR4_R_ODT1_4X4 | off,off,on,on
MEM_DDR4_R_ODT2_4X4 | off,off,off,off
MEM_DDR4_R_ODT3_4X4 | on,on,off,off
MEM_DDR4_W_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X4 | on,on,off,off
MEM_DDR4_W_ODT1_4X4 | off,off,on,on
MEM_DDR4_W_ODT2_4X4 | off,off,on,on
MEM_DDR4_W_ODT3_4X4 | on,on,off,off
MEM_DDR4_R_DERIVED_ODTN | Rank 0,-,-,-
MEM_DDR4_R_DERIVED_ODT0 | (Drive) RZQ/7 (34 Ohm),-,-,-
MEM_DDR4_R_DERIVED_ODT1 | -,-,-,-
MEM_DDR4_R_DERIVED_ODT2 | -,-,-,-
MEM_DDR4_R_DERIVED_ODT3 | -,-,-,-
MEM_DDR4_W_DERIVED_ODTN | Rank 0,-,-,-
MEM_DDR4_W_DERIVED_ODT0 | (Nominal) RZQ/4 (60 Ohm),-,-,-
MEM_DDR4_W_DERIVED_ODT1 | -,-,-,-
MEM_DDR4_W_DERIVED_ODT2 | -,-,-,-
MEM_DDR4_W_DERIVED_ODT3 | -,-,-,-
MEM_DDR4_SEQ_ODT_TABLE_LO | 4
MEM_DDR4_SEQ_ODT_TABLE_HI | 0
MEM_DDR4_CTRL_CFG_READ_ODT_CHIP | 0
MEM_DDR4_CTRL_CFG_WRITE_ODT_CHIP | 1
MEM_DDR4_CTRL_CFG_READ_ODT_RANK | 0
MEM_DDR4_CTRL_CFG_WRITE_ODT_RANK | 1
MEM_DDR4_SPEEDBIN_ENUM | DDR4_SPEEDBIN_2400
MEM_DDR4_TIS_PS | 60
MEM_DDR4_TIS_AC_MV | 100
MEM_DDR4_TIH_PS | 95
MEM_DDR4_TIH_DC_MV | 75
MEM_DDR4_TDIVW_TOTAL_UI | 0.2
MEM_DDR4_VDIVW_TOTAL | 136
MEM_DDR4_TDQSQ_UI | 0.16
MEM_DDR4_TQH_UI | 0.76
MEM_DDR4_TDVWP_UI | 0.72
MEM_DDR4_TDQSCK_PS | 165
MEM_DDR4_TDQSS_CYC | 0.27
MEM_DDR4_TQSH_CYC | 0.38
MEM_DDR4_TDSH_CYC | 0.18
MEM_DDR4_TDSS_CYC | 0.18
MEM_DDR4_TWLS_PS | 108.0
MEM_DDR4_TWLH_PS | 108.0
MEM_DDR4_TINIT_US | 500
MEM_DDR4_TMRD_CK_CYC | 8
MEM_DDR4_TRAS_NS | 32.0
MEM_DDR4_TRCD_NS | 15.0
MEM_DDR4_TRP_NS | 15.0
MEM_DDR4_TREFI_US | 7.8
MEM_DDR4_TRFC_NS | 260.0
MEM_DDR4_TWR_NS | 15.0
MEM_DDR4_TWTR_L_CYC | 9
MEM_DDR4_TWTR_S_CYC | 3
MEM_DDR4_TFAW_NS | 21.0
MEM_DDR4_TRRD_L_CYC | 6
MEM_DDR4_TRRD_S_CYC | 4
MEM_DDR4_TCCD_L_CYC | 6
MEM_DDR4_TCCD_S_CYC | 4
MEM_DDR4_TDIVW_DJ_CYC | 0.1
MEM_DDR4_TDQSQ_PS | 66
MEM_DDR4_TQH_CYC | 0.38
MEM_DDR4_TINIT_CK | 400000
MEM_DDR4_TDQSCK_DERV_PS | 2
MEM_DDR4_TDQSCKDS | 450
MEM_DDR4_TDQSCKDM | 900
MEM_DDR4_TDQSCKDL | 1200
MEM_DDR4_TRAS_CYC | 26
MEM_DDR4_TRCD_CYC | 12
MEM_DDR4_TRP_CYC | 12
MEM_DDR4_TRFC_CYC | 208
MEM_DDR4_TWR_CYC | 12
MEM_DDR4_TRTP_CYC | 6
MEM_DDR4_TFAW_CYC | 17
MEM_DDR4_TREFI_CYC | 6240
MEM_DDR4_WRITE_CMD_LATENCY | 5
MEM_DDR4_CFG_GEN_SBE | false
MEM_DDR4_CFG_GEN_DBE | false
MEM_DDR4_LRDIMM_VREFDQ_VALUE |
MEM_QDR2_WIDTH_EXPANDED | false
MEM_QDR2_DATA_PER_DEVICE | 36
MEM_QDR2_ADDR_WIDTH | 19
MEM_QDR2_BWS_EN | true
MEM_QDR2_BL | 4
MEM_QDR2_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_QDR2_DEVICE_WIDTH | 1
MEM_QDR2_DATA_WIDTH | 36
MEM_QDR2_BWS_N_WIDTH | 4
MEM_QDR2_BWS_N_PER_DEVICE | 4
MEM_QDR2_CQ_WIDTH | 1
MEM_QDR2_K_WIDTH | 1
MEM_QDR2_TWL_CYC | 1
MEM_QDR2_SPEEDBIN_ENUM | QDR2_SPEEDBIN_633
MEM_QDR2_TRL_CYC | 2.5
MEM_QDR2_TSA_NS | 0.23
MEM_QDR2_THA_NS | 0.18
MEM_QDR2_TSD_NS | 0.23
MEM_QDR2_THD_NS | 0.18
MEM_QDR2_TCQD_NS | 0.09
MEM_QDR2_TCQDOH_NS | -0.09
MEM_QDR2_INTERNAL_JITTER_NS | 0.08
MEM_QDR2_TCQH_NS | 0.71
MEM_QDR2_TCCQO_NS | 0.45
MEM_QDR4_WIDTH_EXPANDED | false
MEM_QDR4_DQ_PER_PORT_PER_DEVICE | 36
MEM_QDR4_ADDR_WIDTH | 21
MEM_QDR4_CK_ODT_MODE_ENUM | QDR4_ODT_25_PCT
MEM_QDR4_AC_ODT_MODE_ENUM | QDR4_ODT_25_PCT
MEM_QDR4_DATA_ODT_MODE_ENUM | QDR4_ODT_25_PCT
MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM | QDR4_OUTPUT_DRIVE_25_PCT
MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM | QDR4_OUTPUT_DRIVE_25_PCT
MEM_QDR4_DATA_INV_ENA | true
MEM_QDR4_ADDR_INV_ENA | false
MEM_QDR4_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_QDR4_DEVICE_WIDTH | 1
MEM_QDR4_DEVICE_DEPTH | 1
MEM_QDR4_DQ_PER_RD_GROUP | 18
MEM_QDR4_DQ_PER_WR_GROUP | 18
MEM_QDR4_DQ_WIDTH | 72
MEM_QDR4_QK_WIDTH | 4
MEM_QDR4_DK_WIDTH | 4
MEM_QDR4_DINV_WIDTH | 4
MEM_QDR4_USE_ADDR_PARITY | false
MEM_QDR4_DQ_PER_PORT_WIDTH | 36
MEM_QDR4_QK_PER_PORT_WIDTH | 2
MEM_QDR4_DK_PER_PORT_WIDTH | 2
MEM_QDR4_DINV_PER_PORT_WIDTH | 2
MEM_QDR4_BL | 2
MEM_QDR4_TRL_CYC | 8
MEM_QDR4_TWL_CYC | 5
MEM_QDR4_CR0 | 0
MEM_QDR4_CR1 | 0
MEM_QDR4_CR2 | 0
MEM_QDR4_SPEEDBIN_ENUM | QDR4_SPEEDBIN_2133
MEM_QDR4_TISH_PS | 150
MEM_QDR4_TQKQ_MAX_PS | 75
MEM_QDR4_TQH_CYC | 0.4
MEM_QDR4_TCKDK_MAX_PS | 150
MEM_QDR4_TCKDK_MIN_PS | -150
MEM_QDR4_TCKQK_MAX_PS | 225
MEM_QDR4_TASH_PS | 170
MEM_QDR4_TCSH_PS | 170
MEM_RLD2_WIDTH_EXPANDED | false
MEM_RLD2_DQ_PER_DEVICE | 9
MEM_RLD2_ADDR_WIDTH | 21
MEM_RLD2_BANK_ADDR_WIDTH | 3
MEM_RLD2_DM_EN | true
MEM_RLD2_BL | 4
MEM_RLD2_CONFIG_ENUM | RLD2_CONFIG_TRC_8_TRL_8_TWL_9
MEM_RLD2_DRIVE_IMPEDENCE_ENUM | RLD2_DRIVE_IMPEDENCE_INTERNAL_50
MEM_RLD2_ODT_MODE_ENUM | RLD2_ODT_ON
MEM_RLD2_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_RLD2_DEVICE_WIDTH | 1
MEM_RLD2_DEVICE_DEPTH | 1
MEM_RLD2_DQ_WIDTH | 9
MEM_RLD2_DQ_PER_RD_GROUP | 9
MEM_RLD2_DQ_PER_WR_GROUP | 9
MEM_RLD2_QK_WIDTH | 1
MEM_RLD2_DK_WIDTH | 1
MEM_RLD2_DM_WIDTH | 1
MEM_RLD2_CS_WIDTH | 1
MEM_RLD2_TRC | 8
MEM_RLD2_TRL | 8
MEM_RLD2_TWL | 9
MEM_RLD2_MR | 0
MEM_RLD2_SPEEDBIN_ENUM | RLD2_SPEEDBIN_18
MEM_RLD2_REFRESH_INTERVAL_US | 0.24
MEM_RLD2_TCKH_CYC | 0.45
MEM_RLD2_TQKH_HCYC | 0.9
MEM_RLD2_TAS_NS | 0.3
MEM_RLD2_TAH_NS | 0.3
MEM_RLD2_TDS_NS | 0.17
MEM_RLD2_TDH_NS | 0.17
MEM_RLD2_TQKQ_MAX_NS | 0.12
MEM_RLD2_TQKQ_MIN_NS | -0.12
MEM_RLD2_TCKDK_MAX_NS | 0.3
MEM_RLD2_TCKDK_MIN_NS | -0.3
MEM_RLD2_TCKQK_MAX_NS | 0.2
MEM_RLD3_WIDTH_EXPANDED | false
MEM_RLD3_DEPTH_EXPANDED | false
MEM_RLD3_DQ_PER_DEVICE | 36
MEM_RLD3_ADDR_WIDTH | 20
MEM_RLD3_BANK_ADDR_WIDTH | 4
MEM_RLD3_DM_EN | true
MEM_RLD3_BL | 2
MEM_RLD3_DATA_LATENCY_MODE_ENUM | RLD3_DL_RL16_WL17
MEM_RLD3_T_RC_MODE_ENUM | RLD3_TRC_9
MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM | RLD3_OUTPUT_DRIVE_40
MEM_RLD3_ODT_MODE_ENUM | RLD3_ODT_40
MEM_RLD3_AREF_PROTOCOL_ENUM | RLD3_AREF_BAC
MEM_RLD3_WRITE_PROTOCOL_ENUM | RLD3_WRITE_1BANK
MEM_RLD3_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_RLD3_DEVICE_WIDTH | 1
MEM_RLD3_DEVICE_DEPTH | 1
MEM_RLD3_DQ_WIDTH | 36
MEM_RLD3_DQ_PER_RD_GROUP | 9
MEM_RLD3_DQ_PER_WR_GROUP | 18
MEM_RLD3_QK_WIDTH | 4
MEM_RLD3_DK_WIDTH | 2
MEM_RLD3_DM_WIDTH | 2
MEM_RLD3_CS_WIDTH | 1
MEM_RLD3_MR0 | 0
MEM_RLD3_MR1 | 0
MEM_RLD3_MR2 | 0
MEM_RLD3_SPEEDBIN_ENUM | RLD3_SPEEDBIN_093E
MEM_RLD3_TDS_PS | -30
MEM_RLD3_TDS_AC_MV | 150
MEM_RLD3_TDH_PS | 5
MEM_RLD3_TDH_DC_MV | 100
MEM_RLD3_TQKQ_MAX_PS | 75
MEM_RLD3_TQH_CYC | 0.38
MEM_RLD3_TCKDK_MAX_CYC | 0.27
MEM_RLD3_TCKDK_MIN_CYC | -0.27
MEM_RLD3_TCKQK_MAX_PS | 135
MEM_RLD3_TIS_PS | 85
MEM_RLD3_TIS_AC_MV | 150
MEM_RLD3_TIH_PS | 65
MEM_RLD3_TIH_DC_MV | 100
MEM_LPDDR3_DQ_WIDTH | 32
MEM_LPDDR3_DISCRETE_CS_WIDTH | 1
MEM_LPDDR3_CK_WIDTH | 1
MEM_LPDDR3_DM_EN | true
MEM_LPDDR3_ROW_ADDR_WIDTH | 15
MEM_LPDDR3_COL_ADDR_WIDTH | 10
MEM_LPDDR3_BANK_ADDR_WIDTH | 3
MEM_LPDDR3_DQS_WIDTH | 1
MEM_LPDDR3_DM_WIDTH | 1
MEM_LPDDR3_CS_WIDTH | 1
MEM_LPDDR3_CKE_WIDTH | 1
MEM_LPDDR3_ODT_WIDTH | 1
MEM_LPDDR3_ADDR_WIDTH | 10
MEM_LPDDR3_DQ_PER_DQS | 8
MEM_LPDDR3_FORMAT_ENUM | MEM_FORMAT_DISCRETE
MEM_LPDDR3_MR1 | 0
MEM_LPDDR3_MR2 | 0
MEM_LPDDR3_MR3 | 0
MEM_LPDDR3_MR11 | 0
MEM_LPDDR3_BL | LPDDR3_BL_BL8
MEM_LPDDR3_DATA_LATENCY | LPDDR3_DL_RL12_WL6
MEM_LPDDR3_DRV_STR | LPDDR3_DRV_STR_40D_40U
MEM_LPDDR3_DQODT | LPDDR3_DQODT_DISABLE
MEM_LPDDR3_PDODT | LPDDR3_PDODT_DISABLED
MEM_LPDDR3_WLSELECT | Set A
MEM_LPDDR3_NWR | LPDDR3_NWR_NWR12
MEM_LPDDR3_NUM_OF_LOGICAL_RANKS | 1
MEM_LPDDR3_NUM_OF_PHYSICAL_RANKS | 1
MEM_LPDDR3_USE_DEFAULT_ODT | true
MEM_LPDDR3_R_ODTN_1X1 | Rank 0
MEM_LPDDR3_R_ODT0_1X1 | off
MEM_LPDDR3_W_ODTN_1X1 | Rank 0
MEM_LPDDR3_W_ODT0_1X1 | on
MEM_LPDDR3_R_ODTN_2X2 | Rank 0,Rank 1
MEM_LPDDR3_R_ODT0_2X2 | off,off
MEM_LPDDR3_R_ODT1_2X2 | off,off
MEM_LPDDR3_W_ODTN_2X2 | Rank 0,Rank 1
MEM_LPDDR3_W_ODT0_2X2 | on,on
MEM_LPDDR3_W_ODT1_2X2 | off,off
MEM_LPDDR3_R_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_LPDDR3_R_ODT0_4X4 | off,off,off,off
MEM_LPDDR3_R_ODT1_4X4 | off,off,off,off
MEM_LPDDR3_R_ODT2_4X4 | off,off,off,off
MEM_LPDDR3_R_ODT3_4X4 | off,off,off,off
MEM_LPDDR3_W_ODTN_4X4 | Rank 0,Rank 1,Rank 2,Rank 3
MEM_LPDDR3_W_ODT0_4X4 | on,on,on,on
MEM_LPDDR3_W_ODT1_4X4 | off,off,off,off
MEM_LPDDR3_W_ODT2_4X4 | off,off,off,off
MEM_LPDDR3_W_ODT3_4X4 | off,off,off,off
MEM_LPDDR3_R_DERIVED_ODTN | ,
MEM_LPDDR3_R_DERIVED_ODT0 | ,
MEM_LPDDR3_R_DERIVED_ODT1 | ,
MEM_LPDDR3_R_DERIVED_ODT2 | ,
MEM_LPDDR3_R_DERIVED_ODT3 | ,
MEM_LPDDR3_W_DERIVED_ODTN | ,
MEM_LPDDR3_W_DERIVED_ODT0 | ,
MEM_LPDDR3_W_DERIVED_ODT1 | ,
MEM_LPDDR3_W_DERIVED_ODT2 | ,
MEM_LPDDR3_W_DERIVED_ODT3 | ,
MEM_LPDDR3_SEQ_ODT_TABLE_LO | 0
MEM_LPDDR3_SEQ_ODT_TABLE_HI | 0
MEM_LPDDR3_CTRL_CFG_READ_ODT_CHIP | 0
MEM_LPDDR3_CTRL_CFG_WRITE_ODT_CHIP | 0
MEM_LPDDR3_CTRL_CFG_READ_ODT_RANK | 0
MEM_LPDDR3_CTRL_CFG_WRITE_ODT_RANK | 0
MEM_LPDDR3_SPEEDBIN_ENUM | LPDDR3_SPEEDBIN_1600
MEM_LPDDR3_TIS_PS | 75
MEM_LPDDR3_TIS_AC_MV | 150
MEM_LPDDR3_TIH_PS | 100
MEM_LPDDR3_TIH_DC_MV | 100
MEM_LPDDR3_TDS_PS | 75
MEM_LPDDR3_TDS_AC_MV | 150
MEM_LPDDR3_TDH_PS | 100
MEM_LPDDR3_TDH_DC_MV | 100
MEM_LPDDR3_TDQSQ_PS | 135
MEM_LPDDR3_TQH_CYC | 0.38
MEM_LPDDR3_TDQSCKDL | 614
MEM_LPDDR3_TDQSS_CYC | 1.25
MEM_LPDDR3_TQSH_CYC | 0.38
MEM_LPDDR3_TDSH_CYC | 0.2
MEM_LPDDR3_TWLS_PS | 175.0
MEM_LPDDR3_TWLH_PS | 175.0
MEM_LPDDR3_TDSS_CYC | 0.2
MEM_LPDDR3_TINIT_US | 500
MEM_LPDDR3_TMRR_CK_CYC | 4
MEM_LPDDR3_TMRW_CK_CYC | 10
MEM_LPDDR3_TRAS_NS | 42.5
MEM_LPDDR3_TRCD_NS | 18.0
MEM_LPDDR3_TRP_NS | 18.0
MEM_LPDDR3_TREFI_US | 3.9
MEM_LPDDR3_TRFC_NS | 210.0
MEM_LPDDR3_TWR_NS | 15.0
MEM_LPDDR3_TWTR_CYC | 6
MEM_LPDDR3_TFAW_NS | 50.0
MEM_LPDDR3_TRRD_CYC | 8
MEM_LPDDR3_TRTP_CYC | 6
MEM_LPDDR3_TINIT_CK | 499
MEM_LPDDR3_TDQSCK_DERV_PS | 2
MEM_LPDDR3_TDQSCKDS | 220
MEM_LPDDR3_TDQSCKDM | 511
MEM_LPDDR3_TDQSCK_PS | 5500
MEM_LPDDR3_TRAS_CYC | 34
MEM_LPDDR3_TRCD_CYC | 17
MEM_LPDDR3_TRP_CYC | 17
MEM_LPDDR3_TRFC_CYC | 168
MEM_LPDDR3_TWR_CYC | 12
MEM_LPDDR3_TFAW_CYC | 40
MEM_LPDDR3_TREFI_CYC | 3120
MEM_LPDDR3_TRL_CYC | 10
MEM_LPDDR3_TWL_CYC | 6
BOARD_DDR3_USE_DEFAULT_SLEW_RATES | true
BOARD_DDR3_USE_DEFAULT_ISI_VALUES | true
BOARD_DDR3_USER_CK_SLEW_RATE | 4.0
BOARD_DDR3_USER_AC_SLEW_RATE | 2.0
BOARD_DDR3_USER_RCLK_SLEW_RATE | 5.0
BOARD_DDR3_USER_WCLK_SLEW_RATE | 4.0
BOARD_DDR3_USER_RDATA_SLEW_RATE | 2.5
BOARD_DDR3_USER_WDATA_SLEW_RATE | 2.0
BOARD_DDR3_USER_AC_ISI_NS | 0.0
BOARD_DDR3_USER_RCLK_ISI_NS | 0.0
BOARD_DDR3_USER_WCLK_ISI_NS | 0.0
BOARD_DDR3_USER_RDATA_ISI_NS | 0.0
BOARD_DDR3_USER_WDATA_ISI_NS | 0.0
BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED | false
BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED | true
BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_DDR3_DQS_TO_CK_SKEW_NS | 0.02
BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS | 0.05
BOARD_DDR3_SKEW_BETWEEN_DQS_NS | 0.02
BOARD_DDR3_AC_TO_CK_SKEW_NS | 0.0
BOARD_DDR3_MAX_CK_DELAY_NS | 0.6
BOARD_DDR3_MAX_DQS_DELAY_NS | 0.6
BOARD_DDR3_TIS_DERATING_PS | 0
BOARD_DDR3_TIH_DERATING_PS | 0
BOARD_DDR3_TDS_DERATING_PS | 0
BOARD_DDR3_TDH_DERATING_PS | 0
BOARD_DDR3_CK_SLEW_RATE | 4.0
BOARD_DDR3_AC_SLEW_RATE | 2.0
BOARD_DDR3_RCLK_SLEW_RATE | 5.0
BOARD_DDR3_WCLK_SLEW_RATE | 4.0
BOARD_DDR3_RDATA_SLEW_RATE | 2.5
BOARD_DDR3_WDATA_SLEW_RATE | 2.0
BOARD_DDR3_AC_ISI_NS | 0.0
BOARD_DDR3_RCLK_ISI_NS | 0.0
BOARD_DDR3_WCLK_ISI_NS | 0.0
BOARD_DDR3_RDATA_ISI_NS | 0.0
BOARD_DDR3_WDATA_ISI_NS | 0.0
BOARD_DDR3_SKEW_WITHIN_DQS_NS | 0.0
BOARD_DDR3_SKEW_WITHIN_AC_NS | 0.0
BOARD_DDR4_USE_DEFAULT_SLEW_RATES | true
BOARD_DDR4_USE_DEFAULT_ISI_VALUES | true
BOARD_DDR4_USER_CK_SLEW_RATE | 4.0
BOARD_DDR4_USER_AC_SLEW_RATE | 2.0
BOARD_DDR4_USER_RCLK_SLEW_RATE | 8.0
BOARD_DDR4_USER_WCLK_SLEW_RATE | 4.0
BOARD_DDR4_USER_RDATA_SLEW_RATE | 4.0
BOARD_DDR4_USER_WDATA_SLEW_RATE | 2.0
BOARD_DDR4_USER_AC_ISI_NS | 0.0
BOARD_DDR4_USER_RCLK_ISI_NS | 0.0
BOARD_DDR4_USER_WCLK_ISI_NS | 0.0
BOARD_DDR4_USER_RDATA_ISI_NS | 0.0
BOARD_DDR4_USER_WDATA_ISI_NS | 0.0
BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED | true
BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED | false
BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_DDR4_DQS_TO_CK_SKEW_NS | 0.02
BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS | 0.05
BOARD_DDR4_SKEW_BETWEEN_DQS_NS | 0.02
BOARD_DDR4_AC_TO_CK_SKEW_NS | 0.0
BOARD_DDR4_MAX_CK_DELAY_NS | 0.6
BOARD_DDR4_MAX_DQS_DELAY_NS | 0.6
BOARD_DDR4_TIS_DERATING_PS | 0
BOARD_DDR4_TIH_DERATING_PS | 0
BOARD_DDR4_CK_SLEW_RATE | 4.0
BOARD_DDR4_AC_SLEW_RATE | 2.0
BOARD_DDR4_RCLK_SLEW_RATE | 8.0
BOARD_DDR4_WCLK_SLEW_RATE | 4.0
BOARD_DDR4_RDATA_SLEW_RATE | 4.0
BOARD_DDR4_WDATA_SLEW_RATE | 2.0
BOARD_DDR4_AC_ISI_NS | 0.15
BOARD_DDR4_RCLK_ISI_NS | 0.15
BOARD_DDR4_WCLK_ISI_NS | 0.038
BOARD_DDR4_RDATA_ISI_NS | 0.075
BOARD_DDR4_WDATA_ISI_NS | 0.09
BOARD_DDR4_SKEW_WITHIN_DQS_NS | 0.02
BOARD_DDR4_SKEW_WITHIN_AC_NS | 0.18
BOARD_QDR2_USE_DEFAULT_SLEW_RATES | true
BOARD_QDR2_USE_DEFAULT_ISI_VALUES | true
BOARD_QDR2_USER_K_SLEW_RATE | 4.0
BOARD_QDR2_USER_AC_SLEW_RATE | 2.0
BOARD_QDR2_USER_RCLK_SLEW_RATE | 4.0
BOARD_QDR2_USER_RDATA_SLEW_RATE | 2.0
BOARD_QDR2_USER_WDATA_SLEW_RATE | 2.0
BOARD_QDR2_USER_AC_ISI_NS | 0.0
BOARD_QDR2_USER_RCLK_ISI_NS | 0.0
BOARD_QDR2_USER_WCLK_ISI_NS | 0.0
BOARD_QDR2_USER_RDATA_ISI_NS | 0.0
BOARD_QDR2_USER_WDATA_ISI_NS | 0.0
BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED | false
BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED | false
BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED | true
BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS | 0.02
BOARD_QDR2_BRD_SKEW_WITHIN_D_NS | 0.02
BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS | 0.02
BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS | 0.02
BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_QDR2_AC_TO_K_SKEW_NS | 0.0
BOARD_QDR2_MAX_K_DELAY_NS | 0.6
BOARD_QDR2_K_SLEW_RATE | 4.0
BOARD_QDR2_AC_SLEW_RATE | 2.0
BOARD_QDR2_RCLK_SLEW_RATE | 4.0
BOARD_QDR2_WCLK_SLEW_RATE | 4.0
BOARD_QDR2_RDATA_SLEW_RATE | 2.0
BOARD_QDR2_WDATA_SLEW_RATE | 2.0
BOARD_QDR2_AC_ISI_NS | 0.0
BOARD_QDR2_RCLK_ISI_NS | 0.0
BOARD_QDR2_WCLK_ISI_NS | 0.0
BOARD_QDR2_RDATA_ISI_NS | 0.0
BOARD_QDR2_WDATA_ISI_NS | 0.0
BOARD_QDR2_SKEW_WITHIN_Q_NS | 0.0
BOARD_QDR2_SKEW_WITHIN_D_NS | 0.0
BOARD_QDR2_SKEW_WITHIN_AC_NS | 0.0
BOARD_QDR4_USE_DEFAULT_SLEW_RATES | true
BOARD_QDR4_USE_DEFAULT_ISI_VALUES | true
BOARD_QDR4_USER_CK_SLEW_RATE | 4.0
BOARD_QDR4_USER_AC_SLEW_RATE | 2.0
BOARD_QDR4_USER_RCLK_SLEW_RATE | 5.0
BOARD_QDR4_USER_WCLK_SLEW_RATE | 4.0
BOARD_QDR4_USER_RDATA_SLEW_RATE | 2.5
BOARD_QDR4_USER_WDATA_SLEW_RATE | 2.0
BOARD_QDR4_USER_AC_ISI_NS | 0.0
BOARD_QDR4_USER_RCLK_ISI_NS | 0.0
BOARD_QDR4_USER_WCLK_ISI_NS | 0.0
BOARD_QDR4_USER_RDATA_ISI_NS | 0.0
BOARD_QDR4_USER_WDATA_ISI_NS | 0.0
BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED | true
BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS | 0.02
BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS | 0.02
BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED | true
BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_QDR4_DK_TO_CK_SKEW_NS | -0.02
BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS | 0.05
BOARD_QDR4_SKEW_BETWEEN_DK_NS | 0.02
BOARD_QDR4_AC_TO_CK_SKEW_NS | 0.0
BOARD_QDR4_MAX_CK_DELAY_NS | 0.6
BOARD_QDR4_MAX_DK_DELAY_NS | 0.6
BOARD_QDR4_CK_SLEW_RATE | 4.0
BOARD_QDR4_AC_SLEW_RATE | 2.0
BOARD_QDR4_RCLK_SLEW_RATE | 5.0
BOARD_QDR4_WCLK_SLEW_RATE | 4.0
BOARD_QDR4_RDATA_SLEW_RATE | 2.5
BOARD_QDR4_WDATA_SLEW_RATE | 2.0
BOARD_QDR4_AC_ISI_NS | 0.0
BOARD_QDR4_RCLK_ISI_NS | 0.0
BOARD_QDR4_WCLK_ISI_NS | 0.0
BOARD_QDR4_RDATA_ISI_NS | 0.0
BOARD_QDR4_WDATA_ISI_NS | 0.0
BOARD_QDR4_SKEW_WITHIN_QK_NS | 0.0
BOARD_QDR4_SKEW_WITHIN_AC_NS | 0.0
BOARD_RLD3_USE_DEFAULT_SLEW_RATES | true
BOARD_RLD3_USE_DEFAULT_ISI_VALUES | true
BOARD_RLD3_USER_CK_SLEW_RATE | 4.0
BOARD_RLD3_USER_AC_SLEW_RATE | 2.0
BOARD_RLD3_USER_RCLK_SLEW_RATE | 7.0
BOARD_RLD3_USER_WCLK_SLEW_RATE | 4.0
BOARD_RLD3_USER_RDATA_SLEW_RATE | 3.5
BOARD_RLD3_USER_WDATA_SLEW_RATE | 2.0
BOARD_RLD3_USER_AC_ISI_NS | 0.0
BOARD_RLD3_USER_RCLK_ISI_NS | 0.0
BOARD_RLD3_USER_WCLK_ISI_NS | 0.0
BOARD_RLD3_USER_RDATA_ISI_NS | 0.0
BOARD_RLD3_USER_WDATA_ISI_NS | 0.0
BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED | false
BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS | 0.02
BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS | 0.02
BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED | true
BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_RLD3_DK_TO_CK_SKEW_NS | -0.02
BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS | 0.05
BOARD_RLD3_SKEW_BETWEEN_DK_NS | 0.02
BOARD_RLD3_AC_TO_CK_SKEW_NS | 0.0
BOARD_RLD3_MAX_CK_DELAY_NS | 0.6
BOARD_RLD3_MAX_DK_DELAY_NS | 0.6
BOARD_RLD3_TIS_DERATING_PS | 0
BOARD_RLD3_TIH_DERATING_PS | 0
BOARD_RLD3_TDS_DERATING_PS | 0
BOARD_RLD3_TDH_DERATING_PS | 0
BOARD_RLD3_CK_SLEW_RATE | 4.0
BOARD_RLD3_AC_SLEW_RATE | 2.0
BOARD_RLD3_RCLK_SLEW_RATE | 7.0
BOARD_RLD3_WCLK_SLEW_RATE | 4.0
BOARD_RLD3_RDATA_SLEW_RATE | 3.5
BOARD_RLD3_WDATA_SLEW_RATE | 2.0
BOARD_RLD3_AC_ISI_NS | 0.0
BOARD_RLD3_RCLK_ISI_NS | 0.0
BOARD_RLD3_WCLK_ISI_NS | 0.0
BOARD_RLD3_RDATA_ISI_NS | 0.0
BOARD_RLD3_WDATA_ISI_NS | 0.0
BOARD_RLD3_SKEW_WITHIN_QK_NS | 0.0
BOARD_RLD3_SKEW_WITHIN_AC_NS | 0.0
BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES | true
BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES | true
BOARD_LPDDR3_USER_CK_SLEW_RATE | 4.0
BOARD_LPDDR3_USER_AC_SLEW_RATE | 2.0
BOARD_LPDDR3_USER_RCLK_SLEW_RATE | 4.0
BOARD_LPDDR3_USER_WCLK_SLEW_RATE | 4.0
BOARD_LPDDR3_USER_RDATA_SLEW_RATE | 2.0
BOARD_LPDDR3_USER_WDATA_SLEW_RATE | 2.0
BOARD_LPDDR3_USER_AC_ISI_NS | 0.0
BOARD_LPDDR3_USER_RCLK_ISI_NS | 0.0
BOARD_LPDDR3_USER_WCLK_ISI_NS | 0.0
BOARD_LPDDR3_USER_RDATA_ISI_NS | 0.0
BOARD_LPDDR3_USER_WDATA_ISI_NS | 0.0
BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED | false
BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS | 0.02
BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED | true
BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS | 0.02
BOARD_LPDDR3_DQS_TO_CK_SKEW_NS | 0.02
BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS | 0.05
BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS | 0.02
BOARD_LPDDR3_AC_TO_CK_SKEW_NS | 0.0
BOARD_LPDDR3_MAX_CK_DELAY_NS | 0.6
BOARD_LPDDR3_MAX_DQS_DELAY_NS | 0.6
BOARD_LPDDR3_TIS_DERATING_PS | 0
BOARD_LPDDR3_TIH_DERATING_PS | 0
BOARD_LPDDR3_TDS_DERATING_PS | 0
BOARD_LPDDR3_TDH_DERATING_PS | 0
BOARD_LPDDR3_CK_SLEW_RATE | 4.0
BOARD_LPDDR3_AC_SLEW_RATE | 2.0
BOARD_LPDDR3_RCLK_SLEW_RATE | 4.0
BOARD_LPDDR3_WCLK_SLEW_RATE | 4.0
BOARD_LPDDR3_RDATA_SLEW_RATE | 2.0
BOARD_LPDDR3_WDATA_SLEW_RATE | 2.0
BOARD_LPDDR3_AC_ISI_NS | 0.0
BOARD_LPDDR3_RCLK_ISI_NS | 0.0
BOARD_LPDDR3_WCLK_ISI_NS | 0.0
BOARD_LPDDR3_RDATA_ISI_NS | 0.0
BOARD_LPDDR3_WDATA_ISI_NS | 0.0
BOARD_LPDDR3_SKEW_WITHIN_DQS_NS | 0.0
BOARD_LPDDR3_SKEW_WITHIN_AC_NS | 0.0
CTRL_ECC_EN | false
CTRL_MMR_EN | false
CTRL_AUTO_PRECHARGE_EN | false
CTRL_USER_PRIORITY_EN | false
CTRL_DDR3_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_DDR3_SELF_REFRESH_EN | false
CTRL_DDR3_AUTO_POWER_DOWN_EN | false
CTRL_DDR3_AUTO_POWER_DOWN_CYCS | 32
CTRL_DDR3_USER_REFRESH_EN | false
CTRL_DDR3_USER_PRIORITY_EN | false
CTRL_DDR3_AUTO_PRECHARGE_EN | false
CTRL_DDR3_ADDR_ORDER_ENUM | DDR3_CTRL_ADDR_ORDER_CS_R_B_C
CTRL_DDR3_ECC_EN | false
CTRL_DDR3_ECC_AUTO_CORRECTION_EN | false
CTRL_DDR3_REORDER_EN | true
CTRL_DDR3_STARVE_LIMIT | 10
CTRL_DDR3_MMR_EN | false
CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS | 0
CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS | 0
CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR4_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_DDR4_SELF_REFRESH_EN | false
CTRL_DDR4_AUTO_POWER_DOWN_EN | false
CTRL_DDR4_AUTO_POWER_DOWN_CYCS | 32
CTRL_DDR4_USER_REFRESH_EN | false
CTRL_DDR4_USER_PRIORITY_EN | false
CTRL_DDR4_AUTO_PRECHARGE_EN | false
CTRL_DDR4_ADDR_ORDER_ENUM | DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG
CTRL_DDR4_ECC_EN | false
CTRL_DDR4_ECC_AUTO_CORRECTION_EN | false
CTRL_DDR4_REORDER_EN | true
CTRL_DDR4_STARVE_LIMIT | 10
CTRL_DDR4_MMR_EN | false
CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS | 0
CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS | 0
CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
CTRL_QDR2_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_QDR2_AVL_MAX_BURST_COUNT | 4
CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS | false
CTRL_QDR2_AVL_SYMBOL_WIDTH | 9
CTRL_QDR4_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_QDR4_AVL_MAX_BURST_COUNT | 4
CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS | false
CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC | 0
CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC | 0
CTRL_QDR4_AVL_SYMBOL_WIDTH | 9
CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC | 4
CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC | 11
CTRL_RLD2_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_RLD3_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_RLD3_ADDR_ORDER_ENUM | RLD3_CTRL_ADDR_ORDER_CS_R_B_C
CTRL_LPDDR3_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
CTRL_LPDDR3_SELF_REFRESH_EN | false
CTRL_LPDDR3_AUTO_POWER_DOWN_EN | false
CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS | 32
CTRL_LPDDR3_USER_REFRESH_EN | false
CTRL_LPDDR3_USER_PRIORITY_EN | false
CTRL_LPDDR3_AUTO_PRECHARGE_EN | false
CTRL_LPDDR3_ADDR_ORDER_ENUM | LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C
CTRL_LPDDR3_REORDER_EN | true
CTRL_LPDDR3_STARVE_LIMIT | 10
CTRL_LPDDR3_MMR_EN | false
CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS | 0
CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS | 0
CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS | 0
CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS | 0
DIAG_SIM_REGTEST_MODE | false
DIAG_TIMING_REGTEST_MODE | false
DIAG_SYNTH_FOR_SIM | false
DIAG_FAST_SIM_OVERRIDE | FAST_SIM_OVERRIDE_DEFAULT
DIAG_VERBOSE_IOAUX | false
DIAG_ECLIPSE_DEBUG | false
DIAG_EXPORT_VJI | false
DIAG_ENABLE_JTAG_UART | false
DIAG_ENABLE_JTAG_UART_HEX | false
DIAG_ENABLE_HPS_EMIF_DEBUG | false
DIAG_SOFT_NIOS_MODE | SOFT_NIOS_MODE_DISABLED
DIAG_SOFT_NIOS_CLOCK_FREQUENCY | 100
DIAG_USE_RS232_UART | false
DIAG_RS232_UART_BAUDRATE | 57600
DIAG_EX_DESIGN_ADD_TEST_EMIFS |
DIAG_EX_DESIGN_SEPARATE_RESETS | false
DIAG_EXPOSE_DFT_SIGNALS | false
DIAG_EXTRA_CONFIGS |
DIAG_USE_BOARD_DELAY_MODEL | false
DIAG_BOARD_DELAY_CONFIG_STR |
DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE | false
DIAG_TG_AVL_2_NUM_CFG_INTERFACES | 0
SHORT_QSYS_INTERFACE_NAMES | true
DIAG_EXT_DOCS | false
DIAG_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_EXPORT_SEQ_AVALON_MASTER | false
DIAG_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_EX_DESIGN_SEPARATE_RZQS | false
DIAG_EX_DESIGN_ISSP_EN | true
DIAG_INTERFACE_ID | 0
DIAG_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_FAST_SIM | true
DIAG_USE_TG_AVL_2 | false
DIAG_USE_ABSTRACT_PHY | false
DIAG_TG_DATA_PATTERN_LENGTH | 8
DIAG_TG_BE_PATTERN_LENGTH | 8
DIAG_BYPASS_DEFAULT_PATTERN | false
DIAG_BYPASS_USER_STAGE | true
DIAG_BYPASS_REPEAT_STAGE | true
DIAG_BYPASS_STRESS_STAGE | true
DIAG_ENABLE_SOFT_M20K | true
DIAG_DDR3_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER | false
DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS | false
DIAG_DDR3_EX_DESIGN_ISSP_EN | true
DIAG_DDR3_INTERFACE_ID | 0
DIAG_DDR3_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_DDR3_USE_TG_AVL_2 | false
DIAG_DDR3_ABSTRACT_PHY | false
DIAG_DDR3_BYPASS_DEFAULT_PATTERN | false
DIAG_DDR3_BYPASS_USER_STAGE | true
DIAG_DDR3_BYPASS_REPEAT_STAGE | true
DIAG_DDR3_BYPASS_STRESS_STAGE | true
DIAG_DDR3_TG_DATA_PATTERN_LENGTH | 8
DIAG_DDR3_TG_BE_PATTERN_LENGTH | 8
DIAG_DDR3_SEPARATE_READ_WRITE_ITFS | false
DIAG_DDR3_CA_LEVEL_EN | false
DIAG_DDR3_CAL_ADDR0 | 0
DIAG_DDR3_CAL_ADDR1 | 8
DIAG_DDR3_CAL_ENABLE_NON_DES | false
DIAG_DDR3_CAL_FULL_CAL_ON_RESET | true
DIAG_DDR4_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER | false
DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS | false
DIAG_DDR4_EX_DESIGN_ISSP_EN | true
DIAG_DDR4_INTERFACE_ID | 0
DIAG_DDR4_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_DDR4_USE_TG_AVL_2 | false
DIAG_DDR4_ABSTRACT_PHY | false
DIAG_DDR4_BYPASS_DEFAULT_PATTERN | false
DIAG_DDR4_BYPASS_USER_STAGE | true
DIAG_DDR4_BYPASS_REPEAT_STAGE | true
DIAG_DDR4_BYPASS_STRESS_STAGE | true
DIAG_DDR4_TG_DATA_PATTERN_LENGTH | 8
DIAG_DDR4_TG_BE_PATTERN_LENGTH | 8
DIAG_DDR4_SEPARATE_READ_WRITE_ITFS | false
DIAG_DDR4_SKIP_CA_LEVEL | false
DIAG_DDR4_SKIP_CA_DESKEW | false
DIAG_DDR4_SKIP_VREF_CAL | false
DIAG_DDR4_CAL_ADDR0 | 0
DIAG_DDR4_CAL_ADDR1 | 8
DIAG_DDR4_CAL_ENABLE_NON_DES | false
DIAG_DDR4_CAL_FULL_CAL_ON_RESET | true
DIAG_QDR2_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER | false
DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS | false
DIAG_QDR2_EX_DESIGN_ISSP_EN | true
DIAG_QDR2_INTERFACE_ID | 0
DIAG_QDR2_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_QDR2_USE_TG_AVL_2 | false
DIAG_QDR2_ABSTRACT_PHY | false
DIAG_QDR2_BYPASS_DEFAULT_PATTERN | false
DIAG_QDR2_BYPASS_USER_STAGE | true
DIAG_QDR2_BYPASS_REPEAT_STAGE | true
DIAG_QDR2_BYPASS_STRESS_STAGE | true
DIAG_QDR2_TG_DATA_PATTERN_LENGTH | 8
DIAG_QDR2_TG_BE_PATTERN_LENGTH | 8
DIAG_QDR2_SEPARATE_READ_WRITE_ITFS | false
DIAG_QDR4_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER | false
DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS | false
DIAG_QDR4_EX_DESIGN_ISSP_EN | true
DIAG_QDR4_INTERFACE_ID | 0
DIAG_QDR4_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_QDR4_USE_TG_AVL_2 | false
DIAG_QDR4_ABSTRACT_PHY | false
DIAG_QDR4_BYPASS_DEFAULT_PATTERN | false
DIAG_QDR4_BYPASS_USER_STAGE | true
DIAG_QDR4_BYPASS_REPEAT_STAGE | true
DIAG_QDR4_BYPASS_STRESS_STAGE | true
DIAG_QDR4_TG_DATA_PATTERN_LENGTH | 8
DIAG_QDR4_TG_BE_PATTERN_LENGTH | 8
DIAG_QDR4_SEPARATE_READ_WRITE_ITFS | false
DIAG_QDR4_SKIP_VREF_CAL | false
DIAG_RLD2_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER | false
DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS | false
DIAG_RLD2_EX_DESIGN_ISSP_EN | true
DIAG_RLD2_INTERFACE_ID | 0
DIAG_RLD2_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_RLD2_USE_TG_AVL_2 | false
DIAG_RLD2_ABSTRACT_PHY | false
DIAG_RLD2_BYPASS_DEFAULT_PATTERN | false
DIAG_RLD2_BYPASS_USER_STAGE | true
DIAG_RLD2_BYPASS_REPEAT_STAGE | true
DIAG_RLD2_BYPASS_STRESS_STAGE | true
DIAG_RLD2_TG_DATA_PATTERN_LENGTH | 8
DIAG_RLD2_TG_BE_PATTERN_LENGTH | 8
DIAG_RLD2_SEPARATE_READ_WRITE_ITFS | false
DIAG_RLD3_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER | false
DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS | false
DIAG_RLD3_EX_DESIGN_ISSP_EN | true
DIAG_RLD3_INTERFACE_ID | 0
DIAG_RLD3_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_RLD3_USE_TG_AVL_2 | false
DIAG_RLD3_ABSTRACT_PHY | false
DIAG_RLD3_BYPASS_DEFAULT_PATTERN | false
DIAG_RLD3_BYPASS_USER_STAGE | true
DIAG_RLD3_BYPASS_REPEAT_STAGE | true
DIAG_RLD3_BYPASS_STRESS_STAGE | true
DIAG_RLD3_TG_DATA_PATTERN_LENGTH | 8
DIAG_RLD3_TG_BE_PATTERN_LENGTH | 8
DIAG_RLD3_SEPARATE_READ_WRITE_ITFS | false
DIAG_LPDDR3_SIM_CAL_MODE_ENUM | SIM_CAL_MODE_SKIP
DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE | CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER | false
DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES | 1
DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS | false
DIAG_LPDDR3_EX_DESIGN_ISSP_EN | true
DIAG_LPDDR3_INTERFACE_ID | 0
DIAG_LPDDR3_EFFICIENCY_MONITOR | EFFMON_MODE_DISABLED
DIAG_LPDDR3_USE_TG_AVL_2 | false
DIAG_LPDDR3_ABSTRACT_PHY | false
DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN | false
DIAG_LPDDR3_BYPASS_USER_STAGE | true
DIAG_LPDDR3_BYPASS_REPEAT_STAGE | true
DIAG_LPDDR3_BYPASS_STRESS_STAGE | true
DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH | 8
DIAG_LPDDR3_TG_BE_PATTERN_LENGTH | 8
DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS | false
DIAG_LPDDR3_SKIP_CA_LEVEL | false
DIAG_LPDDR3_SKIP_CA_DESKEW | false
EX_DESIGN_GUI_GEN_SIM | true
EX_DESIGN_GUI_GEN_SYNTH | true
EX_DESIGN_GUI_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR3_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_DDR3_GEN_SIM | false
EX_DESIGN_GUI_DDR3_GEN_SYNTH | true
EX_DESIGN_GUI_DDR3_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR3_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR4_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_DDR4_GEN_SIM | false
EX_DESIGN_GUI_DDR4_GEN_SYNTH | true
EX_DESIGN_GUI_DDR4_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR4_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR2_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_QDR2_GEN_SIM | true
EX_DESIGN_GUI_QDR2_GEN_SYNTH | true
EX_DESIGN_GUI_QDR2_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR2_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR4_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_QDR4_GEN_SIM | true
EX_DESIGN_GUI_QDR4_GEN_SYNTH | true
EX_DESIGN_GUI_QDR4_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR4_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD2_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_RLD2_GEN_SIM | true
EX_DESIGN_GUI_RLD2_GEN_SYNTH | true
EX_DESIGN_GUI_RLD2_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD2_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD3_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_RLD3_GEN_SIM | true
EX_DESIGN_GUI_RLD3_GEN_SYNTH | true
EX_DESIGN_GUI_RLD3_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD3_PREV_PRESET | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_LPDDR3_SEL_DESIGN | AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_LPDDR3_GEN_SIM | true
EX_DESIGN_GUI_LPDDR3_GEN_SYNTH | true
EX_DESIGN_GUI_LPDDR3_HDL_FORMAT | HDL_FORMAT_VERILOG
EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT | TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_LPDDR3_PREV_PRESET | TARGET_DEV_KIT_NONE
SILICON_REV | 20nm5
IS_HPS | false
IS_VID | false
USER_CLK_RATIO | 4
C2P_P2C_CLK_RATIO | 4
PHY_HMC_CLK_RATIO | 2
DIAG_ABSTRACT_PHY_WLAT | 6
DIAG_ABSTRACT_PHY_RLAT | 18
DIAG_CPA_OUT_1_EN | false
DIAG_USE_CPA_LOCK | false
DQS_BUS_MODE_ENUM | DQS_BUS_MODE_X8_X9
AC_PIN_MAP_SCHEME | use_0_1_2_lane
NUM_OF_HMC_PORTS | 1
HMC_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
HMC_CTRL_DIMM_TYPE | component
REGISTER_AFI | true
SEQ_SYNTH_CPU_CLK_DIVIDE | 2
SEQ_SYNTH_CAL_CLK_DIVIDE | 10
SEQ_SIM_CPU_CLK_DIVIDE | 1
SEQ_SIM_CAL_CLK_DIVIDE | 32
SEQ_SYNTH_OSC_FREQ_MHZ | 450
SEQ_SIM_OSC_FREQ_MHZ | 1590
NUM_OF_RTL_TILES | 3
PRI_RDATA_TILE_INDEX | 1
PRI_RDATA_LANE_INDEX | 3
PRI_WDATA_TILE_INDEX | 1
PRI_WDATA_LANE_INDEX | 3
PRI_AC_TILE_INDEX | 1
SEC_RDATA_TILE_INDEX | 1
SEC_RDATA_LANE_INDEX | 3
SEC_WDATA_TILE_INDEX | 1
SEC_WDATA_LANE_INDEX | 3
SEC_AC_TILE_INDEX | 1
LANES_USAGE_0 | 765762413
LANES_USAGE_1 | 45
LANES_USAGE_2 | 0
LANES_USAGE_3 | 0
LANES_USAGE_AUTOGEN_WCNT | 4
PINS_USAGE_0 | 1056960511
PINS_USAGE_1 | 763363263
PINS_USAGE_2 | 1055887359
PINS_USAGE_3 | 1073479615
PINS_USAGE_4 | 16773118
PINS_USAGE_5 | 0
PINS_USAGE_6 | 0
PINS_USAGE_7 | 0
PINS_USAGE_8 | 0
PINS_USAGE_9 | 0
PINS_USAGE_10 | 0
PINS_USAGE_11 | 0
PINS_USAGE_12 | 0
PINS_USAGE_AUTOGEN_WCNT | 13
PINS_RATE_0 | 1
PINS_RATE_1 | 561774592
PINS_RATE_2 | 15699967
PINS_RATE_3 | 0
PINS_RATE_4 | 0
PINS_RATE_5 | 0
PINS_RATE_6 | 0
PINS_RATE_7 | 0
PINS_RATE_8 | 0
PINS_RATE_9 | 0
PINS_RATE_10 | 0
PINS_RATE_11 | 0
PINS_RATE_12 | 0
PINS_RATE_AUTOGEN_WCNT | 13
PINS_WDB_0 | 920202678
PINS_WDB_1 | 910912566
PINS_WDB_2 | 316345782
PINS_WDB_3 | 918777270
PINS_WDB_4 | 165375378
PINS_WDB_5 | 136581193
PINS_WDB_6 | 153391689
PINS_WDB_7 | 153387017
PINS_WDB_8 | 316342856
PINS_WDB_9 | 918777270
PINS_WDB_10 | 819686802
PINS_WDB_11 | 920347830
PINS_WDB_12 | 920202672
PINS_WDB_13 | 910912566
PINS_WDB_14 | 3510
PINS_WDB_15 | 0
PINS_WDB_16 | 0
PINS_WDB_17 | 0
PINS_WDB_18 | 0
PINS_WDB_19 | 0
PINS_WDB_20 | 0
PINS_WDB_21 | 0
PINS_WDB_22 | 0
PINS_WDB_23 | 0
PINS_WDB_24 | 0
PINS_WDB_25 | 0
PINS_WDB_26 | 0
PINS_WDB_27 | 0
PINS_WDB_28 | 0
PINS_WDB_29 | 0
PINS_WDB_30 | 0
PINS_WDB_31 | 0
PINS_WDB_32 | 0
PINS_WDB_33 | 0
PINS_WDB_34 | 0
PINS_WDB_35 | 0
PINS_WDB_36 | 0
PINS_WDB_37 | 0
PINS_WDB_38 | 0
PINS_WDB_AUTOGEN_WCNT | 39
PINS_DATA_IN_MODE_0 | 153612873
PINS_DATA_IN_MODE_1 | 167547401
PINS_DATA_IN_MODE_2 | 1059357257
PINS_DATA_IN_MODE_3 | 153129545
PINS_DATA_IN_MODE_4 | 153391743
PINS_DATA_IN_MODE_5 | 150736969
PINS_DATA_IN_MODE_6 | 153391689
PINS_DATA_IN_MODE_7 | 153387017
PINS_DATA_IN_MODE_8 | 1059357256
PINS_DATA_IN_MODE_9 | 153129545
PINS_DATA_IN_MODE_10 | 136614527
PINS_DATA_IN_MODE_11 | 153395145
PINS_DATA_IN_MODE_12 | 153612872
PINS_DATA_IN_MODE_13 | 167547401
PINS_DATA_IN_MODE_14 | 585
PINS_DATA_IN_MODE_15 | 0
PINS_DATA_IN_MODE_16 | 0
PINS_DATA_IN_MODE_17 | 0
PINS_DATA_IN_MODE_18 | 0
PINS_DATA_IN_MODE_19 | 0
PINS_DATA_IN_MODE_20 | 0
PINS_DATA_IN_MODE_21 | 0
PINS_DATA_IN_MODE_22 | 0
PINS_DATA_IN_MODE_23 | 0
PINS_DATA_IN_MODE_24 | 0
PINS_DATA_IN_MODE_25 | 0
PINS_DATA_IN_MODE_26 | 0
PINS_DATA_IN_MODE_27 | 0
PINS_DATA_IN_MODE_28 | 0
PINS_DATA_IN_MODE_29 | 0
PINS_DATA_IN_MODE_30 | 0
PINS_DATA_IN_MODE_31 | 0
PINS_DATA_IN_MODE_32 | 0
PINS_DATA_IN_MODE_33 | 0
PINS_DATA_IN_MODE_34 | 0
PINS_DATA_IN_MODE_35 | 0
PINS_DATA_IN_MODE_36 | 0
PINS_DATA_IN_MODE_37 | 0
PINS_DATA_IN_MODE_38 | 0
PINS_DATA_IN_MODE_AUTOGEN_WCNT | 39
PINS_C2L_DRIVEN_0 | 251457486
PINS_C2L_DRIVEN_1 | 259007
PINS_C2L_DRIVEN_2 | 234881024
PINS_C2L_DRIVEN_3 | 1060893631
PINS_C2L_DRIVEN_4 | 16576462
PINS_C2L_DRIVEN_5 | 0
PINS_C2L_DRIVEN_6 | 0
PINS_C2L_DRIVEN_7 | 0
PINS_C2L_DRIVEN_8 | 0
PINS_C2L_DRIVEN_9 | 0
PINS_C2L_DRIVEN_10 | 0
PINS_C2L_DRIVEN_11 | 0
PINS_C2L_DRIVEN_12 | 0
PINS_C2L_DRIVEN_AUTOGEN_WCNT | 13
PINS_DB_IN_BYPASS_0 | 1
PINS_DB_IN_BYPASS_1 | 763101184
PINS_DB_IN_BYPASS_2 | 15699967
PINS_DB_IN_BYPASS_3 | 0
PINS_DB_IN_BYPASS_4 | 0
PINS_DB_IN_BYPASS_5 | 0
PINS_DB_IN_BYPASS_6 | 0
PINS_DB_IN_BYPASS_7 | 0
PINS_DB_IN_BYPASS_8 | 0
PINS_DB_IN_BYPASS_9 | 0
PINS_DB_IN_BYPASS_10 | 0
PINS_DB_IN_BYPASS_11 | 0
PINS_DB_IN_BYPASS_12 | 0
PINS_DB_IN_BYPASS_AUTOGEN_WCNT | 13
PINS_DB_OUT_BYPASS_0 | 1
PINS_DB_OUT_BYPASS_1 | 763101184
PINS_DB_OUT_BYPASS_2 | 15699967
PINS_DB_OUT_BYPASS_3 | 0
PINS_DB_OUT_BYPASS_4 | 0
PINS_DB_OUT_BYPASS_5 | 0
PINS_DB_OUT_BYPASS_6 | 0
PINS_DB_OUT_BYPASS_7 | 0
PINS_DB_OUT_BYPASS_8 | 0
PINS_DB_OUT_BYPASS_9 | 0
PINS_DB_OUT_BYPASS_10 | 0
PINS_DB_OUT_BYPASS_11 | 0
PINS_DB_OUT_BYPASS_12 | 0
PINS_DB_OUT_BYPASS_AUTOGEN_WCNT | 13
PINS_DB_OE_BYPASS_0 | 1
PINS_DB_OE_BYPASS_1 | 763101184
PINS_DB_OE_BYPASS_2 | 15699967
PINS_DB_OE_BYPASS_3 | 0
PINS_DB_OE_BYPASS_4 | 0
PINS_DB_OE_BYPASS_5 | 0
PINS_DB_OE_BYPASS_6 | 0
PINS_DB_OE_BYPASS_7 | 0
PINS_DB_OE_BYPASS_8 | 0
PINS_DB_OE_BYPASS_9 | 0
PINS_DB_OE_BYPASS_10 | 0
PINS_DB_OE_BYPASS_11 | 0
PINS_DB_OE_BYPASS_12 | 0
PINS_DB_OE_BYPASS_AUTOGEN_WCNT | 13
PINS_INVERT_WR_0 | 537002016
PINS_INVERT_WR_1 | 2048
PINS_INVERT_WR_2 | 536870912
PINS_INVERT_WR_3 | 8390656
PINS_INVERT_WR_4 | 131104
PINS_INVERT_WR_5 | 0
PINS_INVERT_WR_6 | 0
PINS_INVERT_WR_7 | 0
PINS_INVERT_WR_8 | 0
PINS_INVERT_WR_9 | 0
PINS_INVERT_WR_10 | 0
PINS_INVERT_WR_11 | 0
PINS_INVERT_WR_12 | 0
PINS_INVERT_WR_AUTOGEN_WCNT | 13
PINS_INVERT_OE_0 | 1056960510
PINS_INVERT_OE_1 | 763363263
PINS_INVERT_OE_2 | 1055887359
PINS_INVERT_OE_3 | 1073479615
PINS_INVERT_OE_4 | 16773118
PINS_INVERT_OE_5 | 0
PINS_INVERT_OE_6 | 0
PINS_INVERT_OE_7 | 0
PINS_INVERT_OE_8 | 0
PINS_INVERT_OE_9 | 0
PINS_INVERT_OE_10 | 0
PINS_INVERT_OE_11 | 0
PINS_INVERT_OE_12 | 0
PINS_INVERT_OE_AUTOGEN_WCNT | 13
PINS_AC_HMC_DATA_OVERRIDE_ENA_0 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_1 | 201326592
PINS_AC_HMC_DATA_OVERRIDE_ENA_2 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_3 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_4 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_5 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_6 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_7 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_8 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_9 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_10 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_11 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_12 | 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT | 13
PINS_OCT_MODE_0 | 1056960510
PINS_OCT_MODE_1 | 262079
PINS_OCT_MODE_2 | 1040187392
PINS_OCT_MODE_3 | 1073479615
PINS_OCT_MODE_4 | 16773118
PINS_OCT_MODE_5 | 0
PINS_OCT_MODE_6 | 0
PINS_OCT_MODE_7 | 0
PINS_OCT_MODE_8 | 0
PINS_OCT_MODE_9 | 0
PINS_OCT_MODE_10 | 0
PINS_OCT_MODE_11 | 0
PINS_OCT_MODE_12 | 0
PINS_OCT_MODE_AUTOGEN_WCNT | 13
PINS_GPIO_MODE_0 | 1
PINS_GPIO_MODE_1 | 0
PINS_GPIO_MODE_2 | 0
PINS_GPIO_MODE_3 | 0
PINS_GPIO_MODE_4 | 0
PINS_GPIO_MODE_5 | 0
PINS_GPIO_MODE_6 | 0
PINS_GPIO_MODE_7 | 0
PINS_GPIO_MODE_8 | 0
PINS_GPIO_MODE_9 | 0
PINS_GPIO_MODE_10 | 0
PINS_GPIO_MODE_11 | 0
PINS_GPIO_MODE_12 | 0
PINS_GPIO_MODE_AUTOGEN_WCNT | 13
UNUSED_MEM_PINS_PINLOC_0 | 125964303
UNUSED_MEM_PINS_PINLOC_1 | 88178796
UNUSED_MEM_PINS_PINLOC_2 | 76621904
UNUSED_MEM_PINS_PINLOC_3 | 57731144
UNUSED_MEM_PINS_PINLOC_4 | 25202741
UNUSED_MEM_PINS_PINLOC_5 | 12
UNUSED_MEM_PINS_PINLOC_6 | 0
UNUSED_MEM_PINS_PINLOC_7 | 0
UNUSED_MEM_PINS_PINLOC_8 | 0
UNUSED_MEM_PINS_PINLOC_9 | 0
UNUSED_MEM_PINS_PINLOC_10 | 0
UNUSED_MEM_PINS_PINLOC_11 | 0
UNUSED_MEM_PINS_PINLOC_12 | 0
UNUSED_MEM_PINS_PINLOC_13 | 0
UNUSED_MEM_PINS_PINLOC_14 | 0
UNUSED_MEM_PINS_PINLOC_15 | 0
UNUSED_MEM_PINS_PINLOC_16 | 0
UNUSED_MEM_PINS_PINLOC_17 | 0
UNUSED_MEM_PINS_PINLOC_18 | 0
UNUSED_MEM_PINS_PINLOC_19 | 0
UNUSED_MEM_PINS_PINLOC_20 | 0
UNUSED_MEM_PINS_PINLOC_21 | 0
UNUSED_MEM_PINS_PINLOC_22 | 0
UNUSED_MEM_PINS_PINLOC_23 | 0
UNUSED_MEM_PINS_PINLOC_24 | 0
UNUSED_MEM_PINS_PINLOC_25 | 0
UNUSED_MEM_PINS_PINLOC_26 | 0
UNUSED_MEM_PINS_PINLOC_27 | 0
UNUSED_MEM_PINS_PINLOC_28 | 0
UNUSED_MEM_PINS_PINLOC_29 | 0
UNUSED_MEM_PINS_PINLOC_30 | 0
UNUSED_MEM_PINS_PINLOC_31 | 0
UNUSED_MEM_PINS_PINLOC_32 | 0
UNUSED_MEM_PINS_PINLOC_33 | 0
UNUSED_MEM_PINS_PINLOC_34 | 0
UNUSED_MEM_PINS_PINLOC_35 | 0
UNUSED_MEM_PINS_PINLOC_36 | 0
UNUSED_MEM_PINS_PINLOC_37 | 0
UNUSED_MEM_PINS_PINLOC_38 | 0
UNUSED_MEM_PINS_PINLOC_39 | 0
UNUSED_MEM_PINS_PINLOC_40 | 0
UNUSED_MEM_PINS_PINLOC_41 | 0
UNUSED_MEM_PINS_PINLOC_42 | 0
UNUSED_MEM_PINS_PINLOC_43 | 0
UNUSED_MEM_PINS_PINLOC_44 | 0
UNUSED_MEM_PINS_PINLOC_45 | 0
UNUSED_MEM_PINS_PINLOC_46 | 0
UNUSED_MEM_PINS_PINLOC_47 | 0
UNUSED_MEM_PINS_PINLOC_48 | 0
UNUSED_MEM_PINS_PINLOC_49 | 0
UNUSED_MEM_PINS_PINLOC_50 | 0
UNUSED_MEM_PINS_PINLOC_51 | 0
UNUSED_MEM_PINS_PINLOC_52 | 0
UNUSED_MEM_PINS_PINLOC_53 | 0
UNUSED_MEM_PINS_PINLOC_54 | 0
UNUSED_MEM_PINS_PINLOC_55 | 0
UNUSED_MEM_PINS_PINLOC_56 | 0
UNUSED_MEM_PINS_PINLOC_57 | 0
UNUSED_MEM_PINS_PINLOC_58 | 0
UNUSED_MEM_PINS_PINLOC_59 | 0
UNUSED_MEM_PINS_PINLOC_60 | 0
UNUSED_MEM_PINS_PINLOC_61 | 0
UNUSED_MEM_PINS_PINLOC_62 | 0
UNUSED_MEM_PINS_PINLOC_63 | 0
UNUSED_MEM_PINS_PINLOC_64 | 0
UNUSED_MEM_PINS_PINLOC_65 | 0
UNUSED_MEM_PINS_PINLOC_66 | 0
UNUSED_MEM_PINS_PINLOC_67 | 0
UNUSED_MEM_PINS_PINLOC_68 | 0
UNUSED_MEM_PINS_PINLOC_69 | 0
UNUSED_MEM_PINS_PINLOC_70 | 0
UNUSED_MEM_PINS_PINLOC_71 | 0
UNUSED_MEM_PINS_PINLOC_72 | 0
UNUSED_MEM_PINS_PINLOC_73 | 0
UNUSED_MEM_PINS_PINLOC_74 | 0
UNUSED_MEM_PINS_PINLOC_75 | 0
UNUSED_MEM_PINS_PINLOC_76 | 0
UNUSED_MEM_PINS_PINLOC_77 | 0
UNUSED_MEM_PINS_PINLOC_78 | 0
UNUSED_MEM_PINS_PINLOC_79 | 0
UNUSED_MEM_PINS_PINLOC_80 | 0
UNUSED_MEM_PINS_PINLOC_81 | 0
UNUSED_MEM_PINS_PINLOC_82 | 0
UNUSED_MEM_PINS_PINLOC_83 | 0
UNUSED_MEM_PINS_PINLOC_84 | 0
UNUSED_MEM_PINS_PINLOC_85 | 0
UNUSED_MEM_PINS_PINLOC_86 | 0
UNUSED_MEM_PINS_PINLOC_87 | 0
UNUSED_MEM_PINS_PINLOC_88 | 0
UNUSED_MEM_PINS_PINLOC_89 | 0
UNUSED_MEM_PINS_PINLOC_90 | 0
UNUSED_MEM_PINS_PINLOC_91 | 0
UNUSED_MEM_PINS_PINLOC_92 | 0
UNUSED_MEM_PINS_PINLOC_93 | 0
UNUSED_MEM_PINS_PINLOC_94 | 0
UNUSED_MEM_PINS_PINLOC_95 | 0
UNUSED_MEM_PINS_PINLOC_96 | 0
UNUSED_MEM_PINS_PINLOC_97 | 0
UNUSED_MEM_PINS_PINLOC_98 | 0
UNUSED_MEM_PINS_PINLOC_99 | 0
UNUSED_MEM_PINS_PINLOC_100 | 0
UNUSED_MEM_PINS_PINLOC_101 | 0
UNUSED_MEM_PINS_PINLOC_102 | 0
UNUSED_MEM_PINS_PINLOC_103 | 0
UNUSED_MEM_PINS_PINLOC_104 | 0
UNUSED_MEM_PINS_PINLOC_105 | 0
UNUSED_MEM_PINS_PINLOC_106 | 0
UNUSED_MEM_PINS_PINLOC_107 | 0
UNUSED_MEM_PINS_PINLOC_108 | 0
UNUSED_MEM_PINS_PINLOC_109 | 0
UNUSED_MEM_PINS_PINLOC_110 | 0
UNUSED_MEM_PINS_PINLOC_111 | 0
UNUSED_MEM_PINS_PINLOC_112 | 0
UNUSED_MEM_PINS_PINLOC_113 | 0
UNUSED_MEM_PINS_PINLOC_114 | 0
UNUSED_MEM_PINS_PINLOC_115 | 0
UNUSED_MEM_PINS_PINLOC_116 | 0
UNUSED_MEM_PINS_PINLOC_117 | 0
UNUSED_MEM_PINS_PINLOC_118 | 0
UNUSED_MEM_PINS_PINLOC_119 | 0
UNUSED_MEM_PINS_PINLOC_120 | 0
UNUSED_MEM_PINS_PINLOC_121 | 0
UNUSED_MEM_PINS_PINLOC_122 | 0
UNUSED_MEM_PINS_PINLOC_123 | 0
UNUSED_MEM_PINS_PINLOC_124 | 0
UNUSED_MEM_PINS_PINLOC_125 | 0
UNUSED_MEM_PINS_PINLOC_126 | 0
UNUSED_MEM_PINS_PINLOC_127 | 0
UNUSED_MEM_PINS_PINLOC_128 | 0
UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT | 129
UNUSED_DQS_BUSES_LANELOC_0 | 5249027
UNUSED_DQS_BUSES_LANELOC_1 | 4
UNUSED_DQS_BUSES_LANELOC_2 | 0
UNUSED_DQS_BUSES_LANELOC_3 | 0
UNUSED_DQS_BUSES_LANELOC_4 | 0
UNUSED_DQS_BUSES_LANELOC_5 | 0
UNUSED_DQS_BUSES_LANELOC_6 | 0
UNUSED_DQS_BUSES_LANELOC_7 | 0
UNUSED_DQS_BUSES_LANELOC_8 | 0
UNUSED_DQS_BUSES_LANELOC_9 | 0
UNUSED_DQS_BUSES_LANELOC_10 | 0
UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT | 11
CENTER_TIDS_0 | 5249028
CENTER_TIDS_1 | 0
CENTER_TIDS_2 | 0
CENTER_TIDS_AUTOGEN_WCNT | 3
HMC_TIDS_0 | 5511685
HMC_TIDS_1 | 0
HMC_TIDS_2 | 0
HMC_TIDS_AUTOGEN_WCNT | 3
LANE_TIDS_0 | 403177984
LANE_TIDS_1 | 168067584
LANE_TIDS_2 | 35717208
LANE_TIDS_3 | 9746
LANE_TIDS_4 | 0
LANE_TIDS_5 | 0
LANE_TIDS_6 | 0
LANE_TIDS_7 | 0
LANE_TIDS_8 | 0
LANE_TIDS_9 | 0
LANE_TIDS_AUTOGEN_WCNT | 10
PREAMBLE_MODE | preamble_one_cycle
DBI_WR_ENABLE | false
DBI_RD_ENABLE | true
CRC_EN | crc_disable
SWAP_DQS_A_B | false
DQS_PACK_MODE | packed
OCT_SIZE | 2
DBC_WB_RESERVED_ENTRY | 8
DLL_MODE | ctl_dynamic
DLL_CODEWORD | 0
ABPHY_WRITE_PROTOCOL | 0
PHY_USERMODE_OCT | false
PHY_PERIODIC_OCT_RECAL | false
PHY_HAS_DCC | true
PRI_HMC_CFG_ENABLE_ECC | disable
PRI_HMC_CFG_REORDER_DATA | enable
PRI_HMC_CFG_REORDER_READ | enable
PRI_HMC_CFG_REORDER_RDATA | enable
PRI_HMC_CFG_STARVE_LIMIT | 10
PRI_HMC_CFG_DQS_TRACKING_EN | disable
PRI_HMC_CFG_ARBITER_TYPE | twot
PRI_HMC_CFG_OPEN_PAGE_EN | enable
PRI_HMC_CFG_GEAR_DOWN_EN | disable
PRI_HMC_CFG_RLD3_MULTIBANK_MODE | singlebank
PRI_HMC_CFG_PING_PONG_MODE | pingpong_off
PRI_HMC_CFG_SLOT_ROTATE_EN | 0
PRI_HMC_CFG_SLOT_OFFSET | 2
PRI_HMC_CFG_COL_CMD_SLOT | 2
PRI_HMC_CFG_ROW_CMD_SLOT | 1
PRI_HMC_CFG_ENABLE_RC | enable
PRI_HMC_CFG_CS_TO_CHIP_MAPPING | 33825
PRI_HMC_CFG_RB_RESERVED_ENTRY | 8
PRI_HMC_CFG_WB_RESERVED_ENTRY | 8
PRI_HMC_CFG_TCL | 18
PRI_HMC_CFG_POWER_SAVING_EXIT_CYC | 3
PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC | 13
PRI_HMC_CFG_WRITE_ODT_CHIP | 1
PRI_HMC_CFG_READ_ODT_CHIP | 0
PRI_HMC_CFG_WR_ODT_ON | 0
PRI_HMC_CFG_RD_ODT_ON | 5
PRI_HMC_CFG_WR_ODT_PERIOD | 6
PRI_HMC_CFG_RD_ODT_PERIOD | 7
PRI_HMC_CFG_RLD3_REFRESH_SEQ0 | 15
PRI_HMC_CFG_RLD3_REFRESH_SEQ1 | 240
PRI_HMC_CFG_RLD3_REFRESH_SEQ2 | 3840
PRI_HMC_CFG_RLD3_REFRESH_SEQ3 | 61440
PRI_HMC_CFG_SRF_ZQCAL_DISABLE | disable
PRI_HMC_CFG_MPS_ZQCAL_DISABLE | disable
PRI_HMC_CFG_MPS_DQSTRK_DISABLE | disable
PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN | disable
PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN | disable
PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL | 512
PRI_HMC_CFG_DQSTRK_TO_VALID_LAST | 19
PRI_HMC_CFG_DQSTRK_TO_VALID | 4
PRI_HMC_CFG_RFSH_WARN_THRESHOLD | 4
PRI_HMC_CFG_SB_CG_DISABLE | disable
PRI_HMC_CFG_USER_RFSH_EN | disable
PRI_HMC_CFG_SRF_AUTOEXIT_EN | disable
PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK | presrfexit
PRI_HMC_CFG_SB_DDR4_MR3 | 197120
PRI_HMC_CFG_SB_DDR4_MR4 | 264192
PRI_HMC_CFG_SB_DDR4_MR5 | 5152
PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR | 0
PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH | col_width_10
PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH | row_width_15
PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH | bank_width_2
PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH | bg_width_2
PRI_HMC_CFG_LOCAL_IF_CS_WIDTH | cs_width_0
PRI_HMC_CFG_ADDR_ORDER | chip_row_bank_col
PRI_HMC_CFG_ACT_TO_RDWR | 6
PRI_HMC_CFG_ACT_TO_PCH | 13
PRI_HMC_CFG_ACT_TO_ACT | 19
PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK | 3
PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG | 2
PRI_HMC_CFG_RD_TO_RD | 3
PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP | 4
PRI_HMC_CFG_RD_TO_RD_DIFF_BG | 2
PRI_HMC_CFG_RD_TO_WR | 8
PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP | 8
PRI_HMC_CFG_RD_TO_WR_DIFF_BG | 8
PRI_HMC_CFG_RD_TO_PCH | 4
PRI_HMC_CFG_RD_AP_TO_VALID | 10
PRI_HMC_CFG_WR_TO_WR | 3
PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP | 3
PRI_HMC_CFG_WR_TO_WR_DIFF_BG | 2
PRI_HMC_CFG_WR_TO_RD | 15
PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP | 5
PRI_HMC_CFG_WR_TO_RD_DIFF_BG | 13
PRI_HMC_CFG_WR_TO_PCH | 15
PRI_HMC_CFG_WR_AP_TO_VALID | 21
PRI_HMC_CFG_PCH_TO_VALID | 6
PRI_HMC_CFG_PCH_ALL_TO_VALID | 6
PRI_HMC_CFG_ARF_TO_VALID | 105
PRI_HMC_CFG_PDN_TO_VALID | 3
PRI_HMC_CFG_SRF_TO_VALID | 513
PRI_HMC_CFG_SRF_TO_ZQ_CAL | 449
PRI_HMC_CFG_ARF_PERIOD | 3121
PRI_HMC_CFG_PDN_PERIOD | 0
PRI_HMC_CFG_ZQCL_TO_VALID | 257
PRI_HMC_CFG_ZQCS_TO_VALID | 65
PRI_HMC_CFG_MRS_TO_VALID | 7
PRI_HMC_CFG_MPS_TO_VALID | 768
PRI_HMC_CFG_MRR_TO_VALID | 0
PRI_HMC_CFG_MPR_TO_VALID | 16
PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE | 5
PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS | 6
PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY | 0
PRI_HMC_CFG_MMR_CMD_TO_VALID | 16
PRI_HMC_CFG_4_ACT_TO_ACT | 8
PRI_HMC_CFG_16_ACT_TO_ACT | 0
SEC_HMC_CFG_ENABLE_ECC | disable
SEC_HMC_CFG_REORDER_DATA | enable
SEC_HMC_CFG_REORDER_READ | enable
SEC_HMC_CFG_REORDER_RDATA | enable
SEC_HMC_CFG_STARVE_LIMIT | 10
SEC_HMC_CFG_DQS_TRACKING_EN | disable
SEC_HMC_CFG_ARBITER_TYPE | twot
SEC_HMC_CFG_OPEN_PAGE_EN | enable
SEC_HMC_CFG_GEAR_DOWN_EN | disable
SEC_HMC_CFG_RLD3_MULTIBANK_MODE | singlebank
SEC_HMC_CFG_PING_PONG_MODE | pingpong_off
SEC_HMC_CFG_SLOT_ROTATE_EN | 0
SEC_HMC_CFG_SLOT_OFFSET | 2
SEC_HMC_CFG_COL_CMD_SLOT | 2
SEC_HMC_CFG_ROW_CMD_SLOT | 1
SEC_HMC_CFG_ENABLE_RC | enable
SEC_HMC_CFG_CS_TO_CHIP_MAPPING | 33825
SEC_HMC_CFG_RB_RESERVED_ENTRY | 8
SEC_HMC_CFG_WB_RESERVED_ENTRY | 8
SEC_HMC_CFG_TCL | 18
SEC_HMC_CFG_POWER_SAVING_EXIT_CYC | 3
SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC | 13
SEC_HMC_CFG_WRITE_ODT_CHIP | 1
SEC_HMC_CFG_READ_ODT_CHIP | 0
SEC_HMC_CFG_WR_ODT_ON | 0
SEC_HMC_CFG_RD_ODT_ON | 5
SEC_HMC_CFG_WR_ODT_PERIOD | 6
SEC_HMC_CFG_RD_ODT_PERIOD | 7
SEC_HMC_CFG_RLD3_REFRESH_SEQ0 | 15
SEC_HMC_CFG_RLD3_REFRESH_SEQ1 | 240
SEC_HMC_CFG_RLD3_REFRESH_SEQ2 | 3840
SEC_HMC_CFG_RLD3_REFRESH_SEQ3 | 61440
SEC_HMC_CFG_SRF_ZQCAL_DISABLE | disable
SEC_HMC_CFG_MPS_ZQCAL_DISABLE | disable
SEC_HMC_CFG_MPS_DQSTRK_DISABLE | disable
SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN | disable
SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN | disable
SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL | 512
SEC_HMC_CFG_DQSTRK_TO_VALID_LAST | 19
SEC_HMC_CFG_DQSTRK_TO_VALID | 4
SEC_HMC_CFG_RFSH_WARN_THRESHOLD | 4
SEC_HMC_CFG_SB_CG_DISABLE | disable
SEC_HMC_CFG_USER_RFSH_EN | disable
SEC_HMC_CFG_SRF_AUTOEXIT_EN | disable
SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK | presrfexit
SEC_HMC_CFG_SB_DDR4_MR3 | 197120
SEC_HMC_CFG_SB_DDR4_MR4 | 264192
SEC_HMC_CFG_SB_DDR4_MR5 | 5152
SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR | 0
SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH | col_width_10
SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH | row_width_15
SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH | bank_width_2
SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH | bg_width_2
SEC_HMC_CFG_LOCAL_IF_CS_WIDTH | cs_width_0
SEC_HMC_CFG_ADDR_ORDER | chip_row_bank_col
SEC_HMC_CFG_ACT_TO_RDWR | 6
SEC_HMC_CFG_ACT_TO_PCH | 13
SEC_HMC_CFG_ACT_TO_ACT | 19
SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK | 3
SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG | 2
SEC_HMC_CFG_RD_TO_RD | 3
SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP | 4
SEC_HMC_CFG_RD_TO_RD_DIFF_BG | 2
SEC_HMC_CFG_RD_TO_WR | 8
SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP | 8
SEC_HMC_CFG_RD_TO_WR_DIFF_BG | 8
SEC_HMC_CFG_RD_TO_PCH | 4
SEC_HMC_CFG_RD_AP_TO_VALID | 10
SEC_HMC_CFG_WR_TO_WR | 3
SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP | 3
SEC_HMC_CFG_WR_TO_WR_DIFF_BG | 2
SEC_HMC_CFG_WR_TO_RD | 15
SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP | 5
SEC_HMC_CFG_WR_TO_RD_DIFF_BG | 13
SEC_HMC_CFG_WR_TO_PCH | 15
SEC_HMC_CFG_WR_AP_TO_VALID | 21
SEC_HMC_CFG_PCH_TO_VALID | 6
SEC_HMC_CFG_PCH_ALL_TO_VALID | 6
SEC_HMC_CFG_ARF_TO_VALID | 105
SEC_HMC_CFG_PDN_TO_VALID | 3
SEC_HMC_CFG_SRF_TO_VALID | 513
SEC_HMC_CFG_SRF_TO_ZQ_CAL | 449
SEC_HMC_CFG_ARF_PERIOD | 3121
SEC_HMC_CFG_PDN_PERIOD | 0
SEC_HMC_CFG_ZQCL_TO_VALID | 257
SEC_HMC_CFG_ZQCS_TO_VALID | 65
SEC_HMC_CFG_MRS_TO_VALID | 7
SEC_HMC_CFG_MPS_TO_VALID | 768
SEC_HMC_CFG_MRR_TO_VALID | 0
SEC_HMC_CFG_MPR_TO_VALID | 16
SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE | 5
SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS | 6
SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY | 0
SEC_HMC_CFG_MMR_CMD_TO_VALID | 16
SEC_HMC_CFG_4_ACT_TO_ACT | 8
SEC_HMC_CFG_16_ACT_TO_ACT | 0
PINS_PER_LANE | 12
LANES_PER_TILE | 4
OCT_CONTROL_WIDTH | 16
PORT_MEM_CK_WIDTH | 1
PORT_MEM_CK_PINLOC_0 | 57345
PORT_MEM_CK_PINLOC_1 | 0
PORT_MEM_CK_PINLOC_2 | 0
PORT_MEM_CK_PINLOC_3 | 0
PORT_MEM_CK_PINLOC_4 | 0
PORT_MEM_CK_PINLOC_5 | 0
PORT_MEM_CK_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_CK_N_WIDTH | 1
PORT_MEM_CK_N_PINLOC_0 | 58369
PORT_MEM_CK_N_PINLOC_1 | 0
PORT_MEM_CK_N_PINLOC_2 | 0
PORT_MEM_CK_N_PINLOC_3 | 0
PORT_MEM_CK_N_PINLOC_4 | 0
PORT_MEM_CK_N_PINLOC_5 | 0
PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_DK_WIDTH | 1
PORT_MEM_DK_PINLOC_0 | 0
PORT_MEM_DK_PINLOC_1 | 0
PORT_MEM_DK_PINLOC_2 | 0
PORT_MEM_DK_PINLOC_3 | 0
PORT_MEM_DK_PINLOC_4 | 0
PORT_MEM_DK_PINLOC_5 | 0
PORT_MEM_DK_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_DK_N_WIDTH | 1
PORT_MEM_DK_N_PINLOC_0 | 0
PORT_MEM_DK_N_PINLOC_1 | 0
PORT_MEM_DK_N_PINLOC_2 | 0
PORT_MEM_DK_N_PINLOC_3 | 0
PORT_MEM_DK_N_PINLOC_4 | 0
PORT_MEM_DK_N_PINLOC_5 | 0
PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_DKA_WIDTH | 1
PORT_MEM_DKA_PINLOC_0 | 0
PORT_MEM_DKA_PINLOC_1 | 0
PORT_MEM_DKA_PINLOC_2 | 0
PORT_MEM_DKA_PINLOC_3 | 0
PORT_MEM_DKA_PINLOC_4 | 0
PORT_MEM_DKA_PINLOC_5 | 0
PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_DKA_N_WIDTH | 1
PORT_MEM_DKA_N_PINLOC_0 | 0
PORT_MEM_DKA_N_PINLOC_1 | 0
PORT_MEM_DKA_N_PINLOC_2 | 0
PORT_MEM_DKA_N_PINLOC_3 | 0
PORT_MEM_DKA_N_PINLOC_4 | 0
PORT_MEM_DKA_N_PINLOC_5 | 0
PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_DKB_WIDTH | 1
PORT_MEM_DKB_PINLOC_0 | 0
PORT_MEM_DKB_PINLOC_1 | 0
PORT_MEM_DKB_PINLOC_2 | 0
PORT_MEM_DKB_PINLOC_3 | 0
PORT_MEM_DKB_PINLOC_4 | 0
PORT_MEM_DKB_PINLOC_5 | 0
PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_DKB_N_WIDTH | 1
PORT_MEM_DKB_N_PINLOC_0 | 0
PORT_MEM_DKB_N_PINLOC_1 | 0
PORT_MEM_DKB_N_PINLOC_2 | 0
PORT_MEM_DKB_N_PINLOC_3 | 0
PORT_MEM_DKB_N_PINLOC_4 | 0
PORT_MEM_DKB_N_PINLOC_5 | 0
PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_K_WIDTH | 1
PORT_MEM_K_PINLOC_0 | 0
PORT_MEM_K_PINLOC_1 | 0
PORT_MEM_K_PINLOC_2 | 0
PORT_MEM_K_PINLOC_3 | 0
PORT_MEM_K_PINLOC_4 | 0
PORT_MEM_K_PINLOC_5 | 0
PORT_MEM_K_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_K_N_WIDTH | 1
PORT_MEM_K_N_PINLOC_0 | 0
PORT_MEM_K_N_PINLOC_1 | 0
PORT_MEM_K_N_PINLOC_2 | 0
PORT_MEM_K_N_PINLOC_3 | 0
PORT_MEM_K_N_PINLOC_4 | 0
PORT_MEM_K_N_PINLOC_5 | 0
PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_A_WIDTH | 17
PORT_MEM_A_PINLOC_0 | 64024593
PORT_MEM_A_PINLOC_1 | 67173438
PORT_MEM_A_PINLOC_2 | 70322241
PORT_MEM_A_PINLOC_3 | 73471044
PORT_MEM_A_PINLOC_4 | 79768647
PORT_MEM_A_PINLOC_5 | 82917453
PORT_MEM_A_PINLOC_6 | 0
PORT_MEM_A_PINLOC_7 | 0
PORT_MEM_A_PINLOC_8 | 0
PORT_MEM_A_PINLOC_9 | 0
PORT_MEM_A_PINLOC_10 | 0
PORT_MEM_A_PINLOC_11 | 0
PORT_MEM_A_PINLOC_12 | 0
PORT_MEM_A_PINLOC_13 | 0
PORT_MEM_A_PINLOC_14 | 0
PORT_MEM_A_PINLOC_15 | 0
PORT_MEM_A_PINLOC_16 | 0
PORT_MEM_A_PINLOC_AUTOGEN_WCNT | 17
PORT_MEM_BA_WIDTH | 2
PORT_MEM_BA_PINLOC_0 | 86066178
PORT_MEM_BA_PINLOC_1 | 0
PORT_MEM_BA_PINLOC_2 | 0
PORT_MEM_BA_PINLOC_3 | 0
PORT_MEM_BA_PINLOC_4 | 0
PORT_MEM_BA_PINLOC_5 | 0
PORT_MEM_BA_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_BG_WIDTH | 2
PORT_MEM_BG_PINLOC_0 | 50416642
PORT_MEM_BG_PINLOC_1 | 0
PORT_MEM_BG_PINLOC_2 | 0
PORT_MEM_BG_PINLOC_3 | 0
PORT_MEM_BG_PINLOC_4 | 0
PORT_MEM_BG_PINLOC_5 | 0
PORT_MEM_BG_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_C_WIDTH | 1
PORT_MEM_C_PINLOC_0 | 0
PORT_MEM_C_PINLOC_1 | 0
PORT_MEM_C_PINLOC_2 | 0
PORT_MEM_C_PINLOC_3 | 0
PORT_MEM_C_PINLOC_4 | 0
PORT_MEM_C_PINLOC_5 | 0
PORT_MEM_C_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_CKE_WIDTH | 1
PORT_MEM_CKE_PINLOC_0 | 55297
PORT_MEM_CKE_PINLOC_1 | 0
PORT_MEM_CKE_PINLOC_2 | 0
PORT_MEM_CKE_PINLOC_3 | 0
PORT_MEM_CKE_PINLOC_4 | 0
PORT_MEM_CKE_PINLOC_5 | 0
PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_CS_N_WIDTH | 1
PORT_MEM_CS_N_PINLOC_0 | 51201
PORT_MEM_CS_N_PINLOC_1 | 0
PORT_MEM_CS_N_PINLOC_2 | 0
PORT_MEM_CS_N_PINLOC_3 | 0
PORT_MEM_CS_N_PINLOC_4 | 0
PORT_MEM_CS_N_PINLOC_5 | 0
PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_RM_WIDTH | 1
PORT_MEM_RM_PINLOC_0 | 0
PORT_MEM_RM_PINLOC_1 | 0
PORT_MEM_RM_PINLOC_2 | 0
PORT_MEM_RM_PINLOC_3 | 0
PORT_MEM_RM_PINLOC_4 | 0
PORT_MEM_RM_PINLOC_5 | 0
PORT_MEM_RM_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_ODT_WIDTH | 1
PORT_MEM_ODT_PINLOC_0 | 53249
PORT_MEM_ODT_PINLOC_1 | 0
PORT_MEM_ODT_PINLOC_2 | 0
PORT_MEM_ODT_PINLOC_3 | 0
PORT_MEM_ODT_PINLOC_4 | 0
PORT_MEM_ODT_PINLOC_5 | 0
PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_RAS_N_WIDTH | 1
PORT_MEM_RAS_N_PINLOC_0 | 0
PORT_MEM_RAS_N_PINLOC_1 | 0
PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT | 2
PORT_MEM_CAS_N_WIDTH | 1
PORT_MEM_CAS_N_PINLOC_0 | 0
PORT_MEM_CAS_N_PINLOC_1 | 0
PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT | 2
PORT_MEM_WE_N_WIDTH | 1
PORT_MEM_WE_N_PINLOC_0 | 0
PORT_MEM_WE_N_PINLOC_1 | 0
PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT | 2
PORT_MEM_RESET_N_WIDTH | 1
PORT_MEM_RESET_N_PINLOC_0 | 50177
PORT_MEM_RESET_N_PINLOC_1 | 0
PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT | 2
PORT_MEM_ACT_N_WIDTH | 1
PORT_MEM_ACT_N_PINLOC_0 | 52225
PORT_MEM_ACT_N_PINLOC_1 | 0
PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT | 2
PORT_MEM_PAR_WIDTH | 1
PORT_MEM_PAR_PINLOC_0 | 60417
PORT_MEM_PAR_PINLOC_1 | 0
PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT | 2
PORT_MEM_CA_WIDTH | 1
PORT_MEM_CA_PINLOC_0 | 0
PORT_MEM_CA_PINLOC_1 | 0
PORT_MEM_CA_PINLOC_2 | 0
PORT_MEM_CA_PINLOC_3 | 0
PORT_MEM_CA_PINLOC_4 | 0
PORT_MEM_CA_PINLOC_5 | 0
PORT_MEM_CA_PINLOC_6 | 0
PORT_MEM_CA_PINLOC_7 | 0
PORT_MEM_CA_PINLOC_8 | 0
PORT_MEM_CA_PINLOC_9 | 0
PORT_MEM_CA_PINLOC_10 | 0
PORT_MEM_CA_PINLOC_11 | 0
PORT_MEM_CA_PINLOC_12 | 0
PORT_MEM_CA_PINLOC_13 | 0
PORT_MEM_CA_PINLOC_14 | 0
PORT_MEM_CA_PINLOC_15 | 0
PORT_MEM_CA_PINLOC_16 | 0
PORT_MEM_CA_PINLOC_AUTOGEN_WCNT | 17
PORT_MEM_REF_N_WIDTH | 1
PORT_MEM_REF_N_PINLOC_0 | 0
PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_WPS_N_WIDTH | 1
PORT_MEM_WPS_N_PINLOC_0 | 0
PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_RPS_N_WIDTH | 1
PORT_MEM_RPS_N_PINLOC_0 | 0
PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_DOFF_N_WIDTH | 1
PORT_MEM_DOFF_N_PINLOC_0 | 0
PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_LDA_N_WIDTH | 1
PORT_MEM_LDA_N_PINLOC_0 | 0
PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_LDB_N_WIDTH | 1
PORT_MEM_LDB_N_PINLOC_0 | 0
PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_RWA_N_WIDTH | 1
PORT_MEM_RWA_N_PINLOC_0 | 0
PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_RWB_N_WIDTH | 1
PORT_MEM_RWB_N_PINLOC_0 | 0
PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_LBK0_N_WIDTH | 1
PORT_MEM_LBK0_N_PINLOC_0 | 0
PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_LBK1_N_WIDTH | 1
PORT_MEM_LBK1_N_PINLOC_0 | 0
PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_CFG_N_WIDTH | 1
PORT_MEM_CFG_N_PINLOC_0 | 0
PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_AP_WIDTH | 1
PORT_MEM_AP_PINLOC_0 | 0
PORT_MEM_AP_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_AINV_WIDTH | 1
PORT_MEM_AINV_PINLOC_0 | 0
PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT | 1
PORT_MEM_DM_WIDTH | 1
PORT_MEM_DM_PINLOC_0 | 0
PORT_MEM_DM_PINLOC_1 | 0
PORT_MEM_DM_PINLOC_2 | 0
PORT_MEM_DM_PINLOC_3 | 0
PORT_MEM_DM_PINLOC_4 | 0
PORT_MEM_DM_PINLOC_5 | 0
PORT_MEM_DM_PINLOC_6 | 0
PORT_MEM_DM_PINLOC_7 | 0
PORT_MEM_DM_PINLOC_8 | 0
PORT_MEM_DM_PINLOC_9 | 0
PORT_MEM_DM_PINLOC_10 | 0
PORT_MEM_DM_PINLOC_11 | 0
PORT_MEM_DM_PINLOC_12 | 0
PORT_MEM_DM_PINLOC_AUTOGEN_WCNT | 13
PORT_MEM_BWS_N_WIDTH | 1
PORT_MEM_BWS_N_PINLOC_0 | 0
PORT_MEM_BWS_N_PINLOC_1 | 0
PORT_MEM_BWS_N_PINLOC_2 | 0
PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT | 3
PORT_MEM_D_WIDTH | 1
PORT_MEM_D_PINLOC_0 | 0
PORT_MEM_D_PINLOC_1 | 0
PORT_MEM_D_PINLOC_2 | 0
PORT_MEM_D_PINLOC_3 | 0
PORT_MEM_D_PINLOC_4 | 0
PORT_MEM_D_PINLOC_5 | 0
PORT_MEM_D_PINLOC_6 | 0
PORT_MEM_D_PINLOC_7 | 0
PORT_MEM_D_PINLOC_8 | 0
PORT_MEM_D_PINLOC_9 | 0
PORT_MEM_D_PINLOC_10 | 0
PORT_MEM_D_PINLOC_11 | 0
PORT_MEM_D_PINLOC_12 | 0
PORT_MEM_D_PINLOC_13 | 0
PORT_MEM_D_PINLOC_14 | 0
PORT_MEM_D_PINLOC_15 | 0
PORT_MEM_D_PINLOC_16 | 0
PORT_MEM_D_PINLOC_17 | 0
PORT_MEM_D_PINLOC_18 | 0
PORT_MEM_D_PINLOC_19 | 0
PORT_MEM_D_PINLOC_20 | 0
PORT_MEM_D_PINLOC_21 | 0
PORT_MEM_D_PINLOC_22 | 0
PORT_MEM_D_PINLOC_23 | 0
PORT_MEM_D_PINLOC_24 | 0
PORT_MEM_D_PINLOC_25 | 0
PORT_MEM_D_PINLOC_26 | 0
PORT_MEM_D_PINLOC_27 | 0
PORT_MEM_D_PINLOC_28 | 0
PORT_MEM_D_PINLOC_29 | 0
PORT_MEM_D_PINLOC_30 | 0
PORT_MEM_D_PINLOC_31 | 0
PORT_MEM_D_PINLOC_32 | 0
PORT_MEM_D_PINLOC_33 | 0
PORT_MEM_D_PINLOC_34 | 0
PORT_MEM_D_PINLOC_35 | 0
PORT_MEM_D_PINLOC_36 | 0
PORT_MEM_D_PINLOC_37 | 0
PORT_MEM_D_PINLOC_38 | 0
PORT_MEM_D_PINLOC_39 | 0
PORT_MEM_D_PINLOC_40 | 0
PORT_MEM_D_PINLOC_41 | 0
PORT_MEM_D_PINLOC_42 | 0
PORT_MEM_D_PINLOC_43 | 0
PORT_MEM_D_PINLOC_44 | 0
PORT_MEM_D_PINLOC_45 | 0
PORT_MEM_D_PINLOC_46 | 0
PORT_MEM_D_PINLOC_47 | 0
PORT_MEM_D_PINLOC_48 | 0
PORT_MEM_D_PINLOC_AUTOGEN_WCNT | 49
PORT_MEM_DQ_WIDTH | 72
PORT_MEM_DQ_PINLOC_0 | 2098248
PORT_MEM_DQ_PINLOC_1 | 7346179
PORT_MEM_DQ_PINLOC_2 | 10494984
PORT_MEM_DQ_PINLOC_3 | 15742989
PORT_MEM_DQ_PINLOC_4 | 20990994
PORT_MEM_DQ_PINLOC_5 | 26236949
PORT_MEM_DQ_PINLOC_6 | 31484954
PORT_MEM_DQ_PINLOC_7 | 34635807
PORT_MEM_DQ_PINLOC_8 | 39883810
PORT_MEM_DQ_PINLOC_9 | 45131815
PORT_MEM_DQ_PINLOC_10 | 48280620
PORT_MEM_DQ_PINLOC_11 | 91314261
PORT_MEM_DQ_PINLOC_12 | 96562266
PORT_MEM_DQ_PINLOC_13 | 101808221
PORT_MEM_DQ_PINLOC_14 | 107056226
PORT_MEM_DQ_PINLOC_15 | 110207079
PORT_MEM_DQ_PINLOC_16 | 115455082
PORT_MEM_DQ_PINLOC_17 | 120703087
PORT_MEM_DQ_PINLOC_18 | 123851892
PORT_MEM_DQ_PINLOC_19 | 129099897
PORT_MEM_DQ_PINLOC_20 | 134347902
PORT_MEM_DQ_PINLOC_21 | 139593857
PORT_MEM_DQ_PINLOC_22 | 144841862
PORT_MEM_DQ_PINLOC_23 | 147992715
PORT_MEM_DQ_PINLOC_24 | 142
PORT_MEM_DQ_PINLOC_25 | 0
PORT_MEM_DQ_PINLOC_26 | 0
PORT_MEM_DQ_PINLOC_27 | 0
PORT_MEM_DQ_PINLOC_28 | 0
PORT_MEM_DQ_PINLOC_29 | 0
PORT_MEM_DQ_PINLOC_30 | 0
PORT_MEM_DQ_PINLOC_31 | 0
PORT_MEM_DQ_PINLOC_32 | 0
PORT_MEM_DQ_PINLOC_33 | 0
PORT_MEM_DQ_PINLOC_34 | 0
PORT_MEM_DQ_PINLOC_35 | 0
PORT_MEM_DQ_PINLOC_36 | 0
PORT_MEM_DQ_PINLOC_37 | 0
PORT_MEM_DQ_PINLOC_38 | 0
PORT_MEM_DQ_PINLOC_39 | 0
PORT_MEM_DQ_PINLOC_40 | 0
PORT_MEM_DQ_PINLOC_41 | 0
PORT_MEM_DQ_PINLOC_42 | 0
PORT_MEM_DQ_PINLOC_43 | 0
PORT_MEM_DQ_PINLOC_44 | 0
PORT_MEM_DQ_PINLOC_45 | 0
PORT_MEM_DQ_PINLOC_46 | 0
PORT_MEM_DQ_PINLOC_47 | 0
PORT_MEM_DQ_PINLOC_48 | 0
PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT | 49
PORT_MEM_DBI_N_WIDTH | 9
PORT_MEM_DBI_N_PINLOC_0 | 24128521
PORT_MEM_DBI_N_PINLOC_1 | 99662883
PORT_MEM_DBI_N_PINLOC_2 | 137485419
PORT_MEM_DBI_N_PINLOC_3 | 143
PORT_MEM_DBI_N_PINLOC_4 | 0
PORT_MEM_DBI_N_PINLOC_5 | 0
PORT_MEM_DBI_N_PINLOC_6 | 0
PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT | 7
PORT_MEM_DQA_WIDTH | 1
PORT_MEM_DQA_PINLOC_0 | 0
PORT_MEM_DQA_PINLOC_1 | 0
PORT_MEM_DQA_PINLOC_2 | 0
PORT_MEM_DQA_PINLOC_3 | 0
PORT_MEM_DQA_PINLOC_4 | 0
PORT_MEM_DQA_PINLOC_5 | 0
PORT_MEM_DQA_PINLOC_6 | 0
PORT_MEM_DQA_PINLOC_7 | 0
PORT_MEM_DQA_PINLOC_8 | 0
PORT_MEM_DQA_PINLOC_9 | 0
PORT_MEM_DQA_PINLOC_10 | 0
PORT_MEM_DQA_PINLOC_11 | 0
PORT_MEM_DQA_PINLOC_12 | 0
PORT_MEM_DQA_PINLOC_13 | 0
PORT_MEM_DQA_PINLOC_14 | 0
PORT_MEM_DQA_PINLOC_15 | 0
PORT_MEM_DQA_PINLOC_16 | 0
PORT_MEM_DQA_PINLOC_17 | 0
PORT_MEM_DQA_PINLOC_18 | 0
PORT_MEM_DQA_PINLOC_19 | 0
PORT_MEM_DQA_PINLOC_20 | 0
PORT_MEM_DQA_PINLOC_21 | 0
PORT_MEM_DQA_PINLOC_22 | 0
PORT_MEM_DQA_PINLOC_23 | 0
PORT_MEM_DQA_PINLOC_24 | 0
PORT_MEM_DQA_PINLOC_25 | 0
PORT_MEM_DQA_PINLOC_26 | 0
PORT_MEM_DQA_PINLOC_27 | 0
PORT_MEM_DQA_PINLOC_28 | 0
PORT_MEM_DQA_PINLOC_29 | 0
PORT_MEM_DQA_PINLOC_30 | 0
PORT_MEM_DQA_PINLOC_31 | 0
PORT_MEM_DQA_PINLOC_32 | 0
PORT_MEM_DQA_PINLOC_33 | 0
PORT_MEM_DQA_PINLOC_34 | 0
PORT_MEM_DQA_PINLOC_35 | 0
PORT_MEM_DQA_PINLOC_36 | 0
PORT_MEM_DQA_PINLOC_37 | 0
PORT_MEM_DQA_PINLOC_38 | 0
PORT_MEM_DQA_PINLOC_39 | 0
PORT_MEM_DQA_PINLOC_40 | 0
PORT_MEM_DQA_PINLOC_41 | 0
PORT_MEM_DQA_PINLOC_42 | 0
PORT_MEM_DQA_PINLOC_43 | 0
PORT_MEM_DQA_PINLOC_44 | 0
PORT_MEM_DQA_PINLOC_45 | 0
PORT_MEM_DQA_PINLOC_46 | 0
PORT_MEM_DQA_PINLOC_47 | 0
PORT_MEM_DQA_PINLOC_48 | 0
PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT | 49
PORT_MEM_DQB_WIDTH | 1
PORT_MEM_DQB_PINLOC_0 | 0
PORT_MEM_DQB_PINLOC_1 | 0
PORT_MEM_DQB_PINLOC_2 | 0
PORT_MEM_DQB_PINLOC_3 | 0
PORT_MEM_DQB_PINLOC_4 | 0
PORT_MEM_DQB_PINLOC_5 | 0
PORT_MEM_DQB_PINLOC_6 | 0
PORT_MEM_DQB_PINLOC_7 | 0
PORT_MEM_DQB_PINLOC_8 | 0
PORT_MEM_DQB_PINLOC_9 | 0
PORT_MEM_DQB_PINLOC_10 | 0
PORT_MEM_DQB_PINLOC_11 | 0
PORT_MEM_DQB_PINLOC_12 | 0
PORT_MEM_DQB_PINLOC_13 | 0
PORT_MEM_DQB_PINLOC_14 | 0
PORT_MEM_DQB_PINLOC_15 | 0
PORT_MEM_DQB_PINLOC_16 | 0
PORT_MEM_DQB_PINLOC_17 | 0
PORT_MEM_DQB_PINLOC_18 | 0
PORT_MEM_DQB_PINLOC_19 | 0
PORT_MEM_DQB_PINLOC_20 | 0
PORT_MEM_DQB_PINLOC_21 | 0
PORT_MEM_DQB_PINLOC_22 | 0
PORT_MEM_DQB_PINLOC_23 | 0
PORT_MEM_DQB_PINLOC_24 | 0
PORT_MEM_DQB_PINLOC_25 | 0
PORT_MEM_DQB_PINLOC_26 | 0
PORT_MEM_DQB_PINLOC_27 | 0
PORT_MEM_DQB_PINLOC_28 | 0
PORT_MEM_DQB_PINLOC_29 | 0
PORT_MEM_DQB_PINLOC_30 | 0
PORT_MEM_DQB_PINLOC_31 | 0
PORT_MEM_DQB_PINLOC_32 | 0
PORT_MEM_DQB_PINLOC_33 | 0
PORT_MEM_DQB_PINLOC_34 | 0
PORT_MEM_DQB_PINLOC_35 | 0
PORT_MEM_DQB_PINLOC_36 | 0
PORT_MEM_DQB_PINLOC_37 | 0
PORT_MEM_DQB_PINLOC_38 | 0
PORT_MEM_DQB_PINLOC_39 | 0
PORT_MEM_DQB_PINLOC_40 | 0
PORT_MEM_DQB_PINLOC_41 | 0
PORT_MEM_DQB_PINLOC_42 | 0
PORT_MEM_DQB_PINLOC_43 | 0
PORT_MEM_DQB_PINLOC_44 | 0
PORT_MEM_DQB_PINLOC_45 | 0
PORT_MEM_DQB_PINLOC_46 | 0
PORT_MEM_DQB_PINLOC_47 | 0
PORT_MEM_DQB_PINLOC_48 | 0
PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT | 49
PORT_MEM_DINVA_WIDTH | 1
PORT_MEM_DINVA_PINLOC_0 | 0
PORT_MEM_DINVA_PINLOC_1 | 0
PORT_MEM_DINVA_PINLOC_2 | 0
PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT | 3
PORT_MEM_DINVB_WIDTH | 1
PORT_MEM_DINVB_PINLOC_0 | 0
PORT_MEM_DINVB_PINLOC_1 | 0
PORT_MEM_DINVB_PINLOC_2 | 0
PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT | 3
PORT_MEM_Q_WIDTH | 1
PORT_MEM_Q_PINLOC_0 | 0
PORT_MEM_Q_PINLOC_1 | 0
PORT_MEM_Q_PINLOC_2 | 0
PORT_MEM_Q_PINLOC_3 | 0
PORT_MEM_Q_PINLOC_4 | 0
PORT_MEM_Q_PINLOC_5 | 0
PORT_MEM_Q_PINLOC_6 | 0
PORT_MEM_Q_PINLOC_7 | 0
PORT_MEM_Q_PINLOC_8 | 0
PORT_MEM_Q_PINLOC_9 | 0
PORT_MEM_Q_PINLOC_10 | 0
PORT_MEM_Q_PINLOC_11 | 0
PORT_MEM_Q_PINLOC_12 | 0
PORT_MEM_Q_PINLOC_13 | 0
PORT_MEM_Q_PINLOC_14 | 0
PORT_MEM_Q_PINLOC_15 | 0
PORT_MEM_Q_PINLOC_16 | 0
PORT_MEM_Q_PINLOC_17 | 0
PORT_MEM_Q_PINLOC_18 | 0
PORT_MEM_Q_PINLOC_19 | 0
PORT_MEM_Q_PINLOC_20 | 0
PORT_MEM_Q_PINLOC_21 | 0
PORT_MEM_Q_PINLOC_22 | 0
PORT_MEM_Q_PINLOC_23 | 0
PORT_MEM_Q_PINLOC_24 | 0
PORT_MEM_Q_PINLOC_25 | 0
PORT_MEM_Q_PINLOC_26 | 0
PORT_MEM_Q_PINLOC_27 | 0
PORT_MEM_Q_PINLOC_28 | 0
PORT_MEM_Q_PINLOC_29 | 0
PORT_MEM_Q_PINLOC_30 | 0
PORT_MEM_Q_PINLOC_31 | 0
PORT_MEM_Q_PINLOC_32 | 0
PORT_MEM_Q_PINLOC_33 | 0
PORT_MEM_Q_PINLOC_34 | 0
PORT_MEM_Q_PINLOC_35 | 0
PORT_MEM_Q_PINLOC_36 | 0
PORT_MEM_Q_PINLOC_37 | 0
PORT_MEM_Q_PINLOC_38 | 0
PORT_MEM_Q_PINLOC_39 | 0
PORT_MEM_Q_PINLOC_40 | 0
PORT_MEM_Q_PINLOC_41 | 0
PORT_MEM_Q_PINLOC_42 | 0
PORT_MEM_Q_PINLOC_43 | 0
PORT_MEM_Q_PINLOC_44 | 0
PORT_MEM_Q_PINLOC_45 | 0
PORT_MEM_Q_PINLOC_46 | 0
PORT_MEM_Q_PINLOC_47 | 0
PORT_MEM_Q_PINLOC_48 | 0
PORT_MEM_Q_PINLOC_AUTOGEN_WCNT | 49
PORT_MEM_DQS_WIDTH | 9
PORT_MEM_DQS_PINLOC_0 | 16781321
PORT_MEM_DQS_PINLOC_1 | 92315676
PORT_MEM_DQS_PINLOC_2 | 130138212
PORT_MEM_DQS_PINLOC_3 | 136
PORT_MEM_DQS_PINLOC_4 | 0
PORT_MEM_DQS_PINLOC_5 | 0
PORT_MEM_DQS_PINLOC_6 | 0
PORT_MEM_DQS_PINLOC_7 | 0
PORT_MEM_DQS_PINLOC_8 | 0
PORT_MEM_DQS_PINLOC_9 | 0
PORT_MEM_DQS_PINLOC_10 | 0
PORT_MEM_DQS_PINLOC_11 | 0
PORT_MEM_DQS_PINLOC_12 | 0
PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT | 13
PORT_MEM_DQS_N_WIDTH | 9
PORT_MEM_DQS_N_PINLOC_0 | 17830921
PORT_MEM_DQS_N_PINLOC_1 | 93365277
PORT_MEM_DQS_N_PINLOC_2 | 131187813
PORT_MEM_DQS_N_PINLOC_3 | 137
PORT_MEM_DQS_N_PINLOC_4 | 0
PORT_MEM_DQS_N_PINLOC_5 | 0
PORT_MEM_DQS_N_PINLOC_6 | 0
PORT_MEM_DQS_N_PINLOC_7 | 0
PORT_MEM_DQS_N_PINLOC_8 | 0
PORT_MEM_DQS_N_PINLOC_9 | 0
PORT_MEM_DQS_N_PINLOC_10 | 0
PORT_MEM_DQS_N_PINLOC_11 | 0
PORT_MEM_DQS_N_PINLOC_12 | 0
PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT | 13
PORT_MEM_QK_WIDTH | 1
PORT_MEM_QK_PINLOC_0 | 0
PORT_MEM_QK_PINLOC_1 | 0
PORT_MEM_QK_PINLOC_2 | 0
PORT_MEM_QK_PINLOC_3 | 0
PORT_MEM_QK_PINLOC_4 | 0
PORT_MEM_QK_PINLOC_5 | 0
PORT_MEM_QK_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_QK_N_WIDTH | 1
PORT_MEM_QK_N_PINLOC_0 | 0
PORT_MEM_QK_N_PINLOC_1 | 0
PORT_MEM_QK_N_PINLOC_2 | 0
PORT_MEM_QK_N_PINLOC_3 | 0
PORT_MEM_QK_N_PINLOC_4 | 0
PORT_MEM_QK_N_PINLOC_5 | 0
PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_QKA_WIDTH | 1
PORT_MEM_QKA_PINLOC_0 | 0
PORT_MEM_QKA_PINLOC_1 | 0
PORT_MEM_QKA_PINLOC_2 | 0
PORT_MEM_QKA_PINLOC_3 | 0
PORT_MEM_QKA_PINLOC_4 | 0
PORT_MEM_QKA_PINLOC_5 | 0
PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_QKA_N_WIDTH | 1
PORT_MEM_QKA_N_PINLOC_0 | 0
PORT_MEM_QKA_N_PINLOC_1 | 0
PORT_MEM_QKA_N_PINLOC_2 | 0
PORT_MEM_QKA_N_PINLOC_3 | 0
PORT_MEM_QKA_N_PINLOC_4 | 0
PORT_MEM_QKA_N_PINLOC_5 | 0
PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_QKB_WIDTH | 1
PORT_MEM_QKB_PINLOC_0 | 0
PORT_MEM_QKB_PINLOC_1 | 0
PORT_MEM_QKB_PINLOC_2 | 0
PORT_MEM_QKB_PINLOC_3 | 0
PORT_MEM_QKB_PINLOC_4 | 0
PORT_MEM_QKB_PINLOC_5 | 0
PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_QKB_N_WIDTH | 1
PORT_MEM_QKB_N_PINLOC_0 | 0
PORT_MEM_QKB_N_PINLOC_1 | 0
PORT_MEM_QKB_N_PINLOC_2 | 0
PORT_MEM_QKB_N_PINLOC_3 | 0
PORT_MEM_QKB_N_PINLOC_4 | 0
PORT_MEM_QKB_N_PINLOC_5 | 0
PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT | 6
PORT_MEM_CQ_WIDTH | 1
PORT_MEM_CQ_PINLOC_0 | 0
PORT_MEM_CQ_PINLOC_1 | 0
PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT | 2
PORT_MEM_CQ_N_WIDTH | 1
PORT_MEM_CQ_N_PINLOC_0 | 0
PORT_MEM_CQ_N_PINLOC_1 | 0
PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT | 2
PORT_MEM_ALERT_N_WIDTH | 1
PORT_MEM_ALERT_N_PINLOC_0 | 1
PORT_MEM_ALERT_N_PINLOC_1 | 0
PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT | 2
PORT_MEM_PE_N_WIDTH | 1
PORT_MEM_PE_N_PINLOC_0 | 0
PORT_MEM_PE_N_PINLOC_1 | 0
PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT | 2
PORT_CLKS_SHARING_MASTER_OUT_WIDTH | 32
PORT_CLKS_SHARING_SLAVE_IN_WIDTH | 32
PORT_AFI_RLAT_WIDTH | 6
PORT_AFI_WLAT_WIDTH | 6
PORT_AFI_SEQ_BUSY_WIDTH | 4
PORT_AFI_ADDR_WIDTH | 1
PORT_AFI_BA_WIDTH | 1
PORT_AFI_BG_WIDTH | 1
PORT_AFI_C_WIDTH | 1
PORT_AFI_CKE_WIDTH | 1
PORT_AFI_CS_N_WIDTH | 1
PORT_AFI_RM_WIDTH | 1
PORT_AFI_ODT_WIDTH | 1
PORT_AFI_RAS_N_WIDTH | 1
PORT_AFI_CAS_N_WIDTH | 1
PORT_AFI_WE_N_WIDTH | 1
PORT_AFI_RST_N_WIDTH | 1
PORT_AFI_ACT_N_WIDTH | 1
PORT_AFI_PAR_WIDTH | 1
PORT_AFI_CA_WIDTH | 1
PORT_AFI_REF_N_WIDTH | 1
PORT_AFI_WPS_N_WIDTH | 1
PORT_AFI_RPS_N_WIDTH | 1
PORT_AFI_DOFF_N_WIDTH | 1
PORT_AFI_LD_N_WIDTH | 1
PORT_AFI_RW_N_WIDTH | 1
PORT_AFI_LBK0_N_WIDTH | 1
PORT_AFI_LBK1_N_WIDTH | 1
PORT_AFI_CFG_N_WIDTH | 1
PORT_AFI_AP_WIDTH | 1
PORT_AFI_AINV_WIDTH | 1
PORT_AFI_DM_WIDTH | 1
PORT_AFI_DM_N_WIDTH | 1
PORT_AFI_BWS_N_WIDTH | 1
PORT_AFI_RDATA_DBI_N_WIDTH | 1
PORT_AFI_WDATA_DBI_N_WIDTH | 1
PORT_AFI_RDATA_DINV_WIDTH | 1
PORT_AFI_WDATA_DINV_WIDTH | 1
PORT_AFI_DQS_BURST_WIDTH | 1
PORT_AFI_WDATA_VALID_WIDTH | 1
PORT_AFI_WDATA_WIDTH | 1
PORT_AFI_RDATA_EN_FULL_WIDTH | 1
PORT_AFI_RDATA_WIDTH | 1
PORT_AFI_RDATA_VALID_WIDTH | 1
PORT_AFI_RRANK_WIDTH | 1
PORT_AFI_WRANK_WIDTH | 1
PORT_AFI_ALERT_N_WIDTH | 1
PORT_AFI_PE_N_WIDTH | 1
PORT_CTRL_AST_CMD_DATA_WIDTH | 1
PORT_CTRL_AST_WR_DATA_WIDTH | 1
PORT_CTRL_AST_RD_DATA_WIDTH | 1
PORT_CTRL_AMM_ADDRESS_WIDTH | 26
PORT_CTRL_AMM_RDATA_WIDTH | 576
PORT_CTRL_AMM_WDATA_WIDTH | 576
PORT_CTRL_AMM_BCOUNT_WIDTH | 7
PORT_CTRL_AMM_BYTEEN_WIDTH | 72
PORT_CTRL_USER_REFRESH_REQ_WIDTH | 4
PORT_CTRL_USER_REFRESH_BANK_WIDTH | 16
PORT_CTRL_SELF_REFRESH_REQ_WIDTH | 4
PORT_CTRL_ECC_WRITE_INFO_WIDTH | 15
PORT_CTRL_ECC_RDATA_ID_WIDTH | 13
PORT_CTRL_ECC_READ_INFO_WIDTH | 3
PORT_CTRL_ECC_CMD_INFO_WIDTH | 3
PORT_CTRL_ECC_WB_POINTER_WIDTH | 12
PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH | 10
PORT_CTRL_MMR_SLAVE_RDATA_WIDTH | 32
PORT_CTRL_MMR_SLAVE_WDATA_WIDTH | 32
PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH | 2
PORT_HPS_EMIF_H2E_WIDTH | 4096
PORT_HPS_EMIF_E2H_WIDTH | 4096
PORT_HPS_EMIF_H2E_GP_WIDTH | 2
PORT_HPS_EMIF_E2H_GP_WIDTH | 1
PORT_CAL_DEBUG_ADDRESS_WIDTH | 24
PORT_CAL_DEBUG_RDATA_WIDTH | 32
PORT_CAL_DEBUG_WDATA_WIDTH | 32
PORT_CAL_DEBUG_BYTEEN_WIDTH | 4
PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH | 24
PORT_CAL_DEBUG_OUT_RDATA_WIDTH | 32
PORT_CAL_DEBUG_OUT_WDATA_WIDTH | 32
PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH | 4
PORT_CAL_MASTER_ADDRESS_WIDTH | 16
PORT_CAL_MASTER_RDATA_WIDTH | 32
PORT_CAL_MASTER_WDATA_WIDTH | 32
PORT_CAL_MASTER_BYTEEN_WIDTH | 4
PORT_DFT_NF_IOAUX_PIO_IN_WIDTH | 8
PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH | 8
PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH | 9
PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH | 8
PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH | 8
PORT_DFT_NF_PLL_CNTSEL_WIDTH | 4
PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH | 3
PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH | 2
PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH | 2
PLL_VCO_FREQ_MHZ_INT | 800
PLL_VCO_TO_MEM_CLK_FREQ_RATIO | 1
PLL_PHY_CLK_VCO_PHASE | 2
PLL_VCO_FREQ_PS_STR | 1250 ps
PLL_REF_CLK_FREQ_PS_STR | 5000 ps
PLL_REF_CLK_FREQ_PS | 5000
PLL_SIM_VCO_FREQ_PS | 1256
PLL_SIM_PHYCLK_0_FREQ_PS | 2512
PLL_SIM_PHYCLK_1_FREQ_PS | 5024
PLL_SIM_PHYCLK_FB_FREQ_PS | 5024
PLL_SIM_PHY_CLK_VCO_PHASE_PS | 314
PLL_SIM_CAL_SLAVE_CLK_FREQ_PS | 6280
PLL_SIM_CAL_MASTER_CLK_FREQ_PS | 6280
PLL_REF_CLK_FREQ_PS_STR_FROM_API | 5000 ps
PLL_VCO_FREQ_PS_STR_FROM_API | 1250 ps
PLL_M_CNT_HIGH | 2
PLL_M_CNT_LOW | 2
PLL_N_CNT_HIGH | 256
PLL_N_CNT_LOW | 256
PLL_M_CNT_BYPASS_EN | false
PLL_N_CNT_BYPASS_EN | true
PLL_M_CNT_EVEN_DUTY_EN | false
PLL_N_CNT_EVEN_DUTY_EN | false
PLL_CP_SETTING | pll_cp_setting15
PLL_BW_CTRL | pll_bw_res_setting2
PLL_C_CNT_HIGH_0 | 2
PLL_C_CNT_LOW_0 | 2
PLL_C_CNT_PRST_0 | 1
PLL_C_CNT_PH_MUX_PRST_0 | 2
PLL_C_CNT_BYPASS_EN_0 | false
PLL_C_CNT_EVEN_DUTY_EN_0 | false
PLL_C_CNT_HIGH_1 | 1
PLL_C_CNT_LOW_1 | 1
PLL_C_CNT_PRST_1 | 1
PLL_C_CNT_PH_MUX_PRST_1 | 2
PLL_C_CNT_BYPASS_EN_1 | false
PLL_C_CNT_EVEN_DUTY_EN_1 | false
PLL_C_CNT_HIGH_2 | 2
PLL_C_CNT_LOW_2 | 2
PLL_C_CNT_PRST_2 | 1
PLL_C_CNT_PH_MUX_PRST_2 | 2
PLL_C_CNT_BYPASS_EN_2 | false
PLL_C_CNT_EVEN_DUTY_EN_2 | false
PLL_C_CNT_HIGH_3 | 3
PLL_C_CNT_LOW_3 | 2
PLL_C_CNT_PRST_3 | 1
PLL_C_CNT_PH_MUX_PRST_3 | 0
PLL_C_CNT_BYPASS_EN_3 | false
PLL_C_CNT_EVEN_DUTY_EN_3 | true
PLL_C_CNT_HIGH_4 | 3
PLL_C_CNT_LOW_4 | 2
PLL_C_CNT_PRST_4 | 1
PLL_C_CNT_PH_MUX_PRST_4 | 0
PLL_C_CNT_BYPASS_EN_4 | false
PLL_C_CNT_EVEN_DUTY_EN_4 | true
PLL_C_CNT_HIGH_5 | 256
PLL_C_CNT_LOW_5 | 256
PLL_C_CNT_PRST_5 | 1
PLL_C_CNT_PH_MUX_PRST_5 | 0
PLL_C_CNT_BYPASS_EN_5 | true
PLL_C_CNT_EVEN_DUTY_EN_5 | false
PLL_C_CNT_HIGH_6 | 256
PLL_C_CNT_LOW_6 | 256
PLL_C_CNT_PRST_6 | 1
PLL_C_CNT_PH_MUX_PRST_6 | 0
PLL_C_CNT_BYPASS_EN_6 | true
PLL_C_CNT_EVEN_DUTY_EN_6 | false
PLL_C_CNT_HIGH_7 | 256
PLL_C_CNT_LOW_7 | 256
PLL_C_CNT_PRST_7 | 1
PLL_C_CNT_PH_MUX_PRST_7 | 0
PLL_C_CNT_BYPASS_EN_7 | true
PLL_C_CNT_EVEN_DUTY_EN_7 | false
PLL_C_CNT_HIGH_8 | 256
PLL_C_CNT_LOW_8 | 256
PLL_C_CNT_PRST_8 | 1
PLL_C_CNT_PH_MUX_PRST_8 | 0
PLL_C_CNT_BYPASS_EN_8 | true
PLL_C_CNT_EVEN_DUTY_EN_8 | false
PLL_C_CNT_FREQ_PS_STR_0 | 5000 ps
PLL_C_CNT_PHASE_PS_STR_0 | 313 ps
PLL_C_CNT_DUTY_CYCLE_0 | 50
PLL_C_CNT_FREQ_PS_STR_1 | 2500 ps
PLL_C_CNT_PHASE_PS_STR_1 | 313 ps
PLL_C_CNT_DUTY_CYCLE_1 | 50
PLL_C_CNT_FREQ_PS_STR_2 | 5000 ps
PLL_C_CNT_PHASE_PS_STR_2 | 313 ps
PLL_C_CNT_DUTY_CYCLE_2 | 50
PLL_C_CNT_FREQ_PS_STR_3 | 6250 ps
PLL_C_CNT_PHASE_PS_STR_3 | 0 ps
PLL_C_CNT_DUTY_CYCLE_3 | 50
PLL_C_CNT_FREQ_PS_STR_4 | 6250 ps
PLL_C_CNT_PHASE_PS_STR_4 | 0 ps
PLL_C_CNT_DUTY_CYCLE_4 | 50
PLL_C_CNT_FREQ_PS_STR_5 | 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_5 | 0 ps
PLL_C_CNT_DUTY_CYCLE_5 | 50
PLL_C_CNT_FREQ_PS_STR_6 | 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_6 | 0 ps
PLL_C_CNT_DUTY_CYCLE_6 | 50
PLL_C_CNT_FREQ_PS_STR_7 | 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_7 | 0 ps
PLL_C_CNT_DUTY_CYCLE_7 | 50
PLL_C_CNT_FREQ_PS_STR_8 | 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_8 | 0 ps
PLL_C_CNT_DUTY_CYCLE_8 | 50
PLL_C_CNT_OUT_EN_0 | true
PLL_C_CNT_OUT_EN_1 | true
PLL_C_CNT_OUT_EN_2 | true
PLL_C_CNT_OUT_EN_3 | true
PLL_C_CNT_OUT_EN_4 | true
PLL_C_CNT_OUT_EN_5 | false
PLL_C_CNT_OUT_EN_6 | false
PLL_C_CNT_OUT_EN_7 | false
PLL_C_CNT_OUT_EN_8 | false
PLL_FBCLK_MUX_1 | pll_fbclk_mux_1_glb
PLL_FBCLK_MUX_2 | pll_fbclk_mux_2_m_cnt
PLL_M_CNT_IN_SRC | c_m_cnt_in_src_ph_mux_clk
PLL_BW_SEL | high
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## system_emif_0_cal_slave_component

altera_emif_cal_slave_nf v16.1

## Parameters
ENABLE_JTAG_UART | false
ENABLE_SOFT_RAM | true
SOFT_RAM_HEXFILE | ../../emif/ip_arch_nf/src/seq_cal_soft_m20k.hex
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX115R4F40I3SG
AUTO_DEVICE_SPEEDGRADE | 3
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## system_emif_0_cal_slave_component_clk_bridge

altera_clock_bridge v16.1

system_emif_0_arch | cal_slave_clk | system_emif_0_cal_slave_component_clk_bridge
in_clk
|  | out_clk | system_emif_0_cal_slave_component_ioaux_master_bridge
|  | clk
|  | out_clk | system_emif_0_cal_slave_component_ioaux_soft_ram
|  | clk1

## Parameters
DERIVED_CLOCK_RATE | 0
EXPLICIT_CLOCK_RATE | 0
NUM_CLOCK_OUTPUTS | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## system_emif_0_cal_slave_component_rst_bridge

altera_reset_bridge v16.1

system_emif_0_arch | cal_slave_reset_n | system_emif_0_cal_slave_component_rst_bridge
in_reset
|  | out_reset | system_emif_0_cal_slave_component_ioaux_master_bridge
|  | reset
|  | out_reset | system_emif_0_cal_slave_component_ioaux_soft_ram
|  | reset1

## Parameters
ACTIVE_LOW_RESET | 0
SYNCHRONOUS_EDGES | none
NUM_RESET_OUTPUTS | 1
USE_RESET_REQUEST | 0
AUTO_CLK_CLOCK_RATE | -1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## system_emif_0_cal_slave_component_ioaux_master_bridge

altera_avalon_mm_bridge v16.1

system_emif_0_cal_slave_component_clk_bridge | out_clk | system_emif_0_cal_slave_component_ioaux_master_bridge
clk
system_emif_0_cal_slave_component_rst_bridge | out_reset
reset
system_emif_0_arch | cal_master
s0
|  | m0 | system_emif_0_cal_slave_component_ioaux_soft_ram
|  | s1

## Parameters
DATA_WIDTH | 32
SYMBOL_WIDTH | 8
ADDRESS_WIDTH | 16
SYSINFO_ADDR_WIDTH | 14
USE_AUTO_ADDRESS_WIDTH | 0
AUTO_ADDRESS_WIDTH | 14
HDL_ADDR_WIDTH | 16
ADDRESS_UNITS | SYMBOLS
BURSTCOUNT_WIDTH | 1
MAX_BURST_SIZE | 1
MAX_PENDING_RESPONSES | 4
LINEWRAPBURSTS | 0
PIPELINE_COMMAND | 1
PIPELINE_RESPONSE | 1
USE_RESPONSE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## system_emif_0_cal_slave_component_ioaux_soft_ram

altera_avalon_onchip_memory2 v16.1

system_emif_0_cal_slave_component_ioaux_master_bridge | m0 | system_emif_0_cal_slave_component_ioaux_soft_ram
s1
system_emif_0_cal_slave_component_clk_bridge | out_clk
clk1
system_emif_0_cal_slave_component_rst_bridge | out_reset
reset1

## Parameters
allowInSystemMemoryContentEditor | false
blockType | AUTO
dataWidth | 32
dataWidth2 | 32
dualPort | false
enableDiffWidth | false
derived_enableDiffWidth | false
initMemContent | true
initializationFileName | ../../emif/ip_arch_nf/src/seq_cal_soft_m20k.hex
enPRInitMode | false
instanceID | NONE
memorySize | 16383
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
simMemInitOnlyFilename | 0
singleClockOperation | false
derived_singleClockOperation | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | true
copyInitFile | true
useShallowMemBlocks | false
writable | false
ecc_enabled | false
resetrequest_enabled | false
autoInitializationFileName | altera_emif_cal_slave_nf_ioaux_soft_ram
deviceFamily | ARRIA10
deviceFeatures | ADDRESS_STALL 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0
derived_set_addr_width | 12
derived_set_addr_width2 | 12
derived_set_data_width | 32
derived_set_data_width2 | 32
derived_gui_ram_block_type | Automatic
derived_is_hardcopy | false
derived_init_file_name | ../../emif/ip_arch_nf/src/seq_cal_soft_m20k.hex
generateLegacySim | false

## Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
CONTENTS_INFO | ""
DUAL_PORT | 0
GUI_RAM_BLOCK_TYPE | AUTO
INIT_CONTENTS_FILE | seq_cal_soft_m20k
INIT_MEM_CONTENT | 1
INSTANCE_ID | NONE
NON_DEFAULT_INIT_FILE_ENABLED | 1
RAM_BLOCK_TYPE | AUTO
READ_DURING_WRITE_MODE | DONT_CARE
SINGLE_CLOCK_OP | 0
SIZE_MULTIPLE | 1
SIZE_VALUE | 16383
WRITABLE | 0

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