rcfg_debug |
0 |
enable_pll_reconfig |
0 |
rcfg_jtag_enable |
0 |
set_capability_reg_enable |
0 |
set_user_identifier |
0 |
set_csr_soft_logic_enable |
0 |
dbg_embedded_debug_enable |
0 |
dbg_capability_reg_enable |
0 |
dbg_user_identifier |
0 |
dbg_stat_soft_logic_enable |
0 |
dbg_ctrl_soft_logic_enable |
0 |
rcfg_file_prefix |
altera_xcvr_atx_pll_vi |
rcfg_sv_file_enable |
0 |
rcfg_h_file_enable |
0 |
rcfg_txt_file_enable |
0 |
rcfg_mif_file_enable |
0 |
rcfg_multi_enable |
0 |
rcfg_profile_cnt |
2 |
rcfg_profile_select |
1 |
rcfg_params |
rcfg_debug,enable_pll_reconfig,rcfg_jtag_enable,set_capability_reg_enable,set_user_identifier,set_csr_soft_logic_enable,enable_pld_atx_cal_busy_port,support_mode,prot_mode,bw_sel,refclk_cnt,refclk_index,primary_pll_buffer,enable_8G_path,enable_16G_path,enable_pcie_clk,enable_cascade_out,enable_hip_cal_done_port,set_hip_cal_en,select_manual_config,set_output_clock_frequency,enable_fractional,set_auto_reference_clock_frequency,set_manual_reference_clock_frequency,set_fref_clock_frequency,set_m_counter,set_ref_clk_div,set_l_counter,set_k_counter,enable_mcgb,mcgb_div,enable_hfreq_clk,enable_mcgb_pcie_clksw,mcgb_aux_clkin_cnt,enable_bonding_clks,enable_fb_comp_bonding,pma_width,enable_pld_mcgb_cal_busy_port |
rcfg_param_labels |
rcfg_debug,Enable dynamic reconfiguration,Enable Altera Debug Master Endpoint,Enable capability registers,Set user-defined IP identifier,Enable control and status registers,enable_pld_atx_cal_busy_port,Support mode,Protocol mode,Bandwidth,Number of PLL reference clocks,Selected reference clock source,Primary PLL clock output buffer,Enable PLL GX clock output port,Enable PLL GT clock output port,Enable PCIe clock output port,Enable cascade clock output port,Enable calibration status ports for HIP,Enable PCIe hard IP calibration,Configure counters manually,PLL output frequency,Enable fractional mode,PLL integer reference clock frequency,PLL reference clock frequency,PLL fractional reference clock frequency,Multiply factor (M-Counter),Divide factor (N-Counter),Divide factor (L-Counter),Fractional multiply factor (K),Include Master Clock Generation Block,Clock division factor,Enable x6/xN non-bonded high-speed clock output port,Enable PCIe clock switch interface,Number of auxiliary MCGB clock input ports.,Enable bonding clock output ports,Enable feedback compensation bonding,PMA interface width,enable_pld_mcgb_cal_busy_port |
rcfg_param_vals0 |
|
rcfg_param_vals1 |
|
rcfg_param_vals2 |
|
hssi_pma_lc_refclk_select_mux_powerdown_mode |
powerup |
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch0_src |
scratch0_src_lvpecl |
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch1_src |
scratch1_src_lvpecl |
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch2_src |
scratch2_src_lvpecl |
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch3_src |
scratch3_src_lvpecl |
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch4_src |
scratch4_src_lvpecl |
hssi_pma_lc_refclk_select_mux_xmux_refclk_src |
src_lvpecl |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_iqclk_sel |
power_down |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch0_src |
scratch0_power_down |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch1_src |
scratch1_power_down |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch2_src |
scratch2_power_down |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch3_src |
scratch3_power_down |
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch4_src |
scratch4_power_down |
hssi_pma_lc_refclk_select_mux_refclk_select |
ref_iqclk0 |
hssi_pma_lc_refclk_select_mux_silicon_rev |
20nm5es2 |
hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping |
ref_iqclk0 |
hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping |
power_down |
hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping |
power_down |
hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping |
power_down |
hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping |
power_down |
hssi_refclk_divider_silicon_rev |
20nm5es2 |
hssi_refclk_divider_clk_divider |
div2_off |
hssi_refclk_divider_core_clk_lvpecl |
core_clk_lvpecl_off |
hssi_refclk_divider_enable_lvpecl |
lvpecl_enable |
hssi_refclk_divider_optimal |
true |
hssi_refclk_divider_powerdown_mode |
powerup |
hssi_refclk_divider_sel_pldclk |
iqclk_sel_lvpecl |
hssi_refclk_divider_sup_mode |
user_mode |
hssi_refclk_divider_term_tristate |
tristate_off |
hssi_refclk_divider_vcm_pup |
pup_off |
hssi_refclk_divider_clkbuf_sel |
high_vcm |
hssi_refclk_divider_iostandard |
lvpecl |
atx_pll_silicon_rev |
20nm5es2 |
atx_pll_is_cascaded_pll |
false |
atx_pll_cgb_div |
1 |
atx_pll_pma_width |
64 |
atx_pll_lc_atb |
atb_selectdisable |
atx_pll_cp_compensation_enable |
false |
atx_pll_cp_current_setting |
cp_current_setting23 |
atx_pll_cp_testmode |
cp_normal |
atx_pll_cp_lf_3rd_pole_freq |
lf_3rd_pole_setting2 |
atx_pll_lf_cbig_size |
lf_cbig_setting4 |
atx_pll_cp_lf_order |
lf_3rd_order |
atx_pll_lf_resistance |
lf_setting1 |
atx_pll_lf_ripplecap |
lf_ripple_cap_0 |
atx_pll_cal_status |
cal_in_progress |
atx_pll_bonding |
pll_bonding |
atx_pll_expected_lc_boost_voltage |
0 |
atx_pll_power_rail_et |
900 |
atx_pll_dprio_lc_vreg_boost_scratch |
0 |
atx_pll_dprio_lc_vreg1_boost_scratch |
0 |
atx_pll_dprio_clk_vreg_boost_scratch |
0 |
atx_pll_dprio_mcgb_vreg_boost_scratch |
0 |
atx_pll_dprio_vreg_boost_step_size |
0 |
atx_pll_dprio_vreg1_boost_step_size |
0 |
atx_pll_dprio_clk_vreg_boost_step_size |
0 |
atx_pll_dprio_mcgb_vreg_boost_step_size |
0 |
atx_pll_dprio_lc_vreg_boost_expected_voltage |
0 |
atx_pll_dprio_lc_vreg1_boost_expected_voltage |
0 |
atx_pll_dprio_clk_vreg_boost_expected_voltage |
0 |
atx_pll_dprio_mcgb_vreg_boost_expected_voltage |
0 |
atx_pll_clk_high_perf_voltage |
0 |
atx_pll_clk_mid_power_voltage |
0 |
atx_pll_clk_low_power_voltage |
0 |
atx_pll_tank_sel |
lctank2 |
atx_pll_tank_band |
lc_band0 |
atx_pll_tank_voltage_coarse |
vreg_setting_coarse0 |
atx_pll_tank_voltage_fine |
vreg_setting5 |
atx_pll_output_regulator_supply |
vreg1v_setting3 |
atx_pll_overrange_voltage |
over_setting5 |
atx_pll_underrange_voltage |
under_setting4 |
atx_pll_fb_select |
direct_fb |
atx_pll_d2a_voltage |
d2a_setting_4 |
atx_pll_dsm_mode |
dsm_mode_integer |
atx_pll_dsm_out_sel |
pll_dsm_disable |
atx_pll_dsm_ecn_bypass |
false |
atx_pll_dsm_ecn_test_en |
false |
atx_pll_dsm_fractional_division |
1 |
atx_pll_dsm_fractional_value_ready |
pll_k_ready |
atx_pll_enable_lc_calibration |
true |
atx_pll_enable_lc_vreg_calibration |
true |
atx_pll_iqclk_mux_sel |
iqtxrxclk0 |
atx_pll_vco_bypass_enable |
false |
atx_pll_l_counter |
2 |
atx_pll_l_counter_enable |
true |
atx_pll_cascadeclk_test |
cascadetest_off |
atx_pll_hclk_divide |
1 |
atx_pll_enable_hclk |
hclk_disabled |
atx_pll_m_counter |
64 |
atx_pll_ref_clk_div |
4 |
atx_pll_bandwidth_range_high |
0 hz |
atx_pll_bandwidth_range_low |
0 hz |
atx_pll_bw_sel |
low |
atx_pll_calibration_mode |
cal_off |
atx_pll_datarate |
10312500000 bps |
atx_pll_device_variant |
device1 |
atx_pll_f_max_pfd |
800000000 Hz |
atx_pll_f_max_ref |
800000000 Hz |
atx_pll_f_max_tank_0 |
8800000000 Hz |
atx_pll_f_max_tank_1 |
11400000000 Hz |
atx_pll_f_max_tank_2 |
14600000000 Hz |
atx_pll_f_max_vco |
14600000000 Hz |
atx_pll_f_max_x1 |
8700000000 Hz |
atx_pll_f_min_pfd |
61440000 Hz |
atx_pll_f_min_ref |
61440000 Hz |
atx_pll_f_min_tank_0 |
6500000000 Hz |
atx_pll_f_min_tank_1 |
8800000000 Hz |
atx_pll_f_min_tank_2 |
11400000000 Hz |
atx_pll_f_min_vco |
7300000000 Hz |
atx_pll_initial_settings |
true |
atx_pll_l_counter_scratch |
1 |
atx_pll_lc_mode |
lccmu_normal |
atx_pll_n_counter_scratch |
1 |
atx_pll_output_clock_frequency |
5156250000 Hz |
atx_pll_power_mode |
low_power |
atx_pll_powerdown_mode |
powerup |
atx_pll_prot_mode |
basic_tx |
atx_pll_reference_clock_frequency |
322265625 Hz |
atx_pll_side |
side_unknown |
atx_pll_pm_speed_grade |
i4 |
atx_pll_sup_mode |
user_mode |
atx_pll_top_or_bottom |
tb_unknown |
atx_pll_vccdreg_clk |
vreg_clk5 |
atx_pll_vccdreg_fb |
vreg_fb8 |
atx_pll_vccdreg_fw |
vreg_fw5 |
atx_pll_regulator_bypass |
reg_enable |
atx_pll_vco_freq |
10312500000 Hz |
atx_pll_f_max_vco_fractional |
0 hz |
atx_pll_f_max_pfd_fractional |
0 hz |
atx_pll_min_fractional_percentage |
5 |
atx_pll_max_fractional_percentage |
95 |
atx_pll_analog_mode |
user_custom |
enable_advanced_options |
0 |
enable_hip_options |
0 |
enable_manual_configuration |
0 |
generate_docs |
1 |
generate_add_hdl_instance_example |
0 |
device_family |
ARRIA10 |
device |
10AX115S4F45I3SGE2 |
base_device |
NIGHTFURY5ES2 |
test_mode |
0 |
enable_pld_atx_cal_busy_port |
1 |
enable_debug_ports_parameters |
0 |
support_mode |
user_mode |
message_level |
error |
pma_speedgrade |
i4 |
device_revision |
20nm5es2 |
prot_mode |
Basic |
prot_mode_fnl |
basic_tx |
bw_sel |
low |
refclk_cnt |
1 |
refclk_index |
0 |
silicon_rev |
false |
fb_select_fnl |
direct_fb |
primary_pll_buffer |
GX clock output buffer |
enable_8G_buffer_fnl |
true |
enable_16G_buffer_fnl |
false |
enable_8G_path |
1 |
enable_16G_path |
0 |
enable_pcie_clk |
0 |
enable_cascade_out |
0 |
enable_hip_cal_done_port |
0 |
set_hip_cal_en |
0 |
hip_cal_en |
disable |
select_manual_config |
0 |
dsm_mode |
dsm_mode_integer |
set_output_clock_frequency |
5156.25 |
output_clock_datarate |
10312.5 |
output_clock_frequency |
5156.25 MHz |
vco_freq |
10312.5 MHz |
datarate |
10312.5 Mbps |
enable_fractional |
0 |
set_auto_reference_clock_frequency |
322.265625 |
set_manual_reference_clock_frequency |
100.0 |
reference_clock_frequency_fnl |
322.265625 MHz |
set_fref_clock_frequency |
100.0 |
feedback_clock_frequency_fnl |
100.0 |
m_counter |
64 |
effective_m_counter |
1 |
set_m_counter |
1 |
ref_clk_div |
4 |
set_ref_clk_div |
1 |
l_counter |
2 |
set_l_counter |
2 |
k_counter |
1 |
set_k_counter |
1 |
auto_list |
62.123494 {m 83 effective_m 83 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 62.881098 {m 82 effective_m 82 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 63.657407 {m 81 effective_m 81 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 64.453125 {m 80 effective_m 80 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 65.268987 {m 79 effective_m 79 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 66.105769 {m 78 effective_m 78 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 66.964286 {m 77 effective_m 77 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 67.845395 {m 76 effective_m 76 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 68.750000 {m 75 effective_m 75 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 69.679054 {m 74 effective_m 74 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 70.633562 {m 73 effective_m 73 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 71.614583 {m 72 effective_m 72 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 72.623239 {m 71 effective_m 71 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 73.660714 {m 70 effective_m 70 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 74.728261 {m 69 effective_m 69 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 75.827206 {m 68 effective_m 68 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 76.958955 {m 67 effective_m 67 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 78.125000 {m 66 effective_m 66 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 79.326923 {m 65 effective_m 65 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 80.566406 {m 64 effective_m 64 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 81.845238 {m 63 effective_m 63 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 83.165323 {m 62 effective_m 62 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 84.528689 {m 61 effective_m 61 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 85.937500 {m 60 effective_m 60 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 87.394068 {m 59 effective_m 59 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 88.900862 {m 58 effective_m 58 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 90.460526 {m 57 effective_m 57 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 92.075893 {m 56 effective_m 56 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 93.750000 {m 55 effective_m 55 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 95.486111 {m 54 effective_m 54 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 97.287736 {m 53 effective_m 53 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 99.158654 {m 52 effective_m 52 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 101.102941 {m 51 effective_m 51 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 103.125000 {m 50 effective_m 50 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 105.229592 {m 49 effective_m 49 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 107.421875 {m 48 effective_m 48 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 109.707447 {m 47 effective_m 47 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 112.092391 {m 46 effective_m 46 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 114.583333 {m 45 effective_m 45 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 117.187500 {m 44 effective_m 44 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 119.912791 {m 43 effective_m 43 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 122.767857 {m 42 effective_m 42 n 1 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 124.246988 {m 83 effective_m 83 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 125.762195 {m 82 effective_m 82 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 127.314815 {m 81 effective_m 81 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 128.906250 {m 80 effective_m 80 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 130.537975 {m 79 effective_m 79 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 132.211538 {m 78 effective_m 78 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 133.928571 {m 77 effective_m 77 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 135.690789 {m 76 effective_m 76 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 137.500000 {m 75 effective_m 75 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 139.358108 {m 74 effective_m 74 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 141.267123 {m 73 effective_m 73 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 143.229167 {m 72 effective_m 72 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 145.246479 {m 71 effective_m 71 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 147.321429 {m 70 effective_m 70 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 149.456522 {m 69 effective_m 69 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 151.654412 {m 68 effective_m 68 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 153.917910 {m 67 effective_m 67 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 156.250000 {m 66 effective_m 66 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 158.653846 {m 65 effective_m 65 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 161.132812 {m 64 effective_m 64 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 163.690476 {m 63 effective_m 63 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 166.330645 {m 62 effective_m 62 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 169.057377 {m 61 effective_m 61 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 171.875000 {m 60 effective_m 60 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 174.788136 {m 59 effective_m 59 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 177.801724 {m 58 effective_m 58 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 180.921053 {m 57 effective_m 57 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 184.151786 {m 56 effective_m 56 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 187.500000 {m 55 effective_m 55 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 190.972222 {m 54 effective_m 54 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 194.575472 {m 53 effective_m 53 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 198.317308 {m 52 effective_m 52 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 202.205882 {m 51 effective_m 51 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 206.250000 {m 50 effective_m 50 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 210.459184 {m 49 effective_m 49 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 214.843750 {m 48 effective_m 48 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 219.414894 {m 47 effective_m 47 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 224.184783 {m 46 effective_m 46 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 229.166667 {m 45 effective_m 45 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 234.375000 {m 44 effective_m 44 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 239.825581 {m 43 effective_m 43 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 245.535714 {m 42 effective_m 42 n 2 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 248.493976 {m 83 effective_m 83 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 251.524390 {m 82 effective_m 82 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 254.629630 {m 81 effective_m 81 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 257.812500 {m 80 effective_m 80 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 261.075949 {m 79 effective_m 79 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 264.423077 {m 78 effective_m 78 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 267.857143 {m 77 effective_m 77 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 271.381579 {m 76 effective_m 76 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 275.000000 {m 75 effective_m 75 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 278.716216 {m 74 effective_m 74 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 282.534247 {m 73 effective_m 73 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 286.458333 {m 72 effective_m 72 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 290.492958 {m 71 effective_m 71 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 294.642857 {m 70 effective_m 70 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 298.913043 {m 69 effective_m 69 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 303.308824 {m 68 effective_m 68 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 307.835821 {m 67 effective_m 67 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 312.500000 {m 66 effective_m 66 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 317.307692 {m 65 effective_m 65 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 322.265625 {m 64 effective_m 64 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 327.380952 {m 63 effective_m 63 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 332.661290 {m 62 effective_m 62 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 338.114754 {m 61 effective_m 61 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 343.750000 {m 60 effective_m 60 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 349.576271 {m 59 effective_m 59 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 355.603448 {m 58 effective_m 58 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 361.842105 {m 57 effective_m 57 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 368.303571 {m 56 effective_m 56 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 375.000000 {m 55 effective_m 55 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 381.944444 {m 54 effective_m 54 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 389.150943 {m 53 effective_m 53 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 396.634615 {m 52 effective_m 52 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 404.411765 {m 51 effective_m 51 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 412.500000 {m 50 effective_m 50 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 420.918367 {m 49 effective_m 49 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 429.687500 {m 48 effective_m 48 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 438.829787 {m 47 effective_m 47 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 448.369565 {m 46 effective_m 46 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 458.333333 {m 45 effective_m 45 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 468.750000 {m 44 effective_m 44 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 479.651163 {m 43 effective_m 43 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 491.071429 {m 42 effective_m 42 n 4 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 496.987952 {m 83 effective_m 83 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 503.048780 {m 82 effective_m 82 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 509.259259 {m 81 effective_m 81 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 515.625000 {m 80 effective_m 80 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 522.151899 {m 79 effective_m 79 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 528.846154 {m 78 effective_m 78 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 535.714286 {m 77 effective_m 77 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 542.763158 {m 76 effective_m 76 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 550.000000 {m 75 effective_m 75 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 557.432432 {m 74 effective_m 74 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 565.068493 {m 73 effective_m 73 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 572.916667 {m 72 effective_m 72 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 580.985915 {m 71 effective_m 71 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 589.285714 {m 70 effective_m 70 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 597.826087 {m 69 effective_m 69 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 606.617647 {m 68 effective_m 68 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 615.671642 {m 67 effective_m 67 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 625.000000 {m 66 effective_m 66 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 634.615385 {m 65 effective_m 65 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 644.531250 {m 64 effective_m 64 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 654.761905 {m 63 effective_m 63 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 665.322581 {m 62 effective_m 62 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 676.229508 {m 61 effective_m 61 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 687.500000 {m 60 effective_m 60 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 699.152542 {m 59 effective_m 59 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 711.206897 {m 58 effective_m 58 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 723.684211 {m 57 effective_m 57 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 736.607143 {m 56 effective_m 56 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 750.000000 {m 55 effective_m 55 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 763.888889 {m 54 effective_m 54 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 778.301887 {m 53 effective_m 53 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} 793.269231 {m 52 effective_m 52 n 8 l 2 k 1 tank_sel lctank2 tank_band lc_band0} |
manual_list |
|
pll_setting |
refclk {322.265625 MHz} m_cnt 64 n_cnt 4 l_cnt 2 k_cnt 1 tank_sel lctank2 tank_band lc_band0 fractional_value_ready pll_k_not_ready dsm_out_sel pll_dsm_disable outclk {5156.25 MHz} |
tank_sel |
lctank2 |
tank_band |
lc_band0 |
dsm_out_sel |
pll_dsm_disable |
enable_fb_comp_bonding_fnl |
0 |
check_output_ports_pll |
0 |
iqclk_mux_sel |
iqtxrxclk0 |
set_altera_xcvr_atx_pll_a10_calibration_en |
1 |
calibration_en |
enable |
atx_pll_bonding_mode |
cpri_bonding |
lc_refclk_select |
0 |
enable_mcgb |
0 |
mcgb_div |
1 |
mcgb_div_fnl |
1 |
enable_hfreq_clk |
0 |
enable_mcgb_pcie_clksw |
0 |
mcgb_aux_clkin_cnt |
0 |
mcgb_in_clk_freq |
5156.25 |
mcgb_out_datarate |
10312.5 |
enable_bonding_clks |
0 |
enable_fb_comp_bonding |
0 |
mcgb_enable_iqtxrxclk |
disable_iqtxrxclk |
pma_width |
64 |
enable_mcgb_debug_ports_parameters |
0 |
enable_pld_mcgb_cal_busy_port |
1 |
check_output_ports_mcgb |
0 |
is_protocol_PCIe |
0 |
mapped_output_clock_frequency |
5156.25 MHz |
mapped_primary_pll_buffer |
GX clock output buffer |
mapped_hip_cal_done_port |
0 |
hssi_pma_cgb_master_prot_mode |
basic_tx |
hssi_pma_cgb_master_silicon_rev |
20nm5es2 |
hssi_pma_cgb_master_x1_div_m_sel |
divbypass |
hssi_pma_cgb_master_cgb_enable_iqtxrxclk |
disable_iqtxrxclk |
hssi_pma_cgb_master_ser_mode |
sixty_four_bit |
hssi_pma_cgb_master_datarate |
10312500000 bps |
hssi_pma_cgb_master_cgb_power_down |
normal_cgb |
hssi_pma_cgb_master_observe_cgb_clocks |
observe_nothing |
hssi_pma_cgb_master_op_mode |
enabled |
hssi_pma_cgb_master_tx_ucontrol_reset_pcie |
pcscorehip_controls_mcgb |
hssi_pma_cgb_master_vccdreg_output |
vccdreg_nominal |
hssi_pma_cgb_master_input_select |
lcpll_top |
hssi_pma_cgb_master_input_select_gen3 |
unused |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |