TimeQuest Timing Analyzer report for top
Tue Aug  5 17:48:19 2014
Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1100mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1100mV 85C Model Setup Summary
  9. Slow 1100mV 85C Model Hold Summary
 10. Slow 1100mV 85C Model Recovery Summary
 11. Slow 1100mV 85C Model Removal Summary
 12. Slow 1100mV 85C Model Minimum Pulse Width Summary
 13. Setup Times
 14. Hold Times
 15. Clock to Output Times
 16. Minimum Clock to Output Times
 17. Slow 1100mV 85C Model Metastability Report
 18. Slow 1100mV 0C Model Fmax Summary
 19. Slow 1100mV 0C Model Setup Summary
 20. Slow 1100mV 0C Model Hold Summary
 21. Slow 1100mV 0C Model Recovery Summary
 22. Slow 1100mV 0C Model Removal Summary
 23. Slow 1100mV 0C Model Minimum Pulse Width Summary
 24. Setup Times
 25. Hold Times
 26. Clock to Output Times
 27. Minimum Clock to Output Times
 28. Slow 1100mV 0C Model Metastability Report
 29. Fast 1100mV 85C Model Setup Summary
 30. Fast 1100mV 85C Model Hold Summary
 31. Fast 1100mV 85C Model Recovery Summary
 32. Fast 1100mV 85C Model Removal Summary
 33. Fast 1100mV 85C Model Minimum Pulse Width Summary
 34. Setup Times
 35. Hold Times
 36. Clock to Output Times
 37. Minimum Clock to Output Times
 38. Fast 1100mV 85C Model Metastability Report
 39. Fast 1100mV 0C Model Setup Summary
 40. Fast 1100mV 0C Model Hold Summary
 41. Fast 1100mV 0C Model Recovery Summary
 42. Fast 1100mV 0C Model Removal Summary
 43. Fast 1100mV 0C Model Minimum Pulse Width Summary
 44. Setup Times
 45. Hold Times
 46. Clock to Output Times
 47. Minimum Clock to Output Times
 48. Fast 1100mV 0C Model Metastability Report
 49. Multicorner Timing Analysis Summary
 50. Setup Times
 51. Hold Times
 52. Clock to Output Times
 53. Minimum Clock to Output Times
 54. Board Trace Model Assignments
 55. Input Transition Times
 56. Signal Integrity Metrics (Slow 900mv 0c Model)
 57. Signal Integrity Metrics (Slow 900mv 85c Model)
 58. Signal Integrity Metrics (Fast 900mv 0c Model)
 59. Signal Integrity Metrics (Fast 900mv 85c Model)
 60. Setup Transfers
 61. Hold Transfers
 62. Recovery Transfers
 63. Removal Transfers
 64. Report TCCS
 65. Report RSKM
 66. Unconstrained Paths
 67. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+--------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                        ;
+--------------------+-----------------------------------------------------+
; Quartus II Version ; Version 14.0.0 Build 200 06/17/2014 SJ Full Version ;
; Revision Name      ; top                                                 ;
; Device Family      ; Arria V                                             ;
; Device Name        ; 5AGXFB3H4F35C5                                      ;
; Timing Models      ; Final                                               ;
; Delay Model        ; Combined                                            ;
; Rise/Fall Delays   ; Enabled                                             ;
+--------------------+-----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 24          ;
; Maximum allowed            ; 12          ;
;                            ;             ;
; Average used               ; 2.69        ;
; Maximum used               ; 12          ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  20.0%      ;
;     Processors 3-4         ;  17.1%      ;
;     Processors 5-12        ;  14.3%      ;
;     Processors 13-24       ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------+
; SDC File List                                                                                          ;
+--------------------------------------------------------------------+--------+--------------------------+
; SDC File Path                                                      ; Status ; Read at                  ;
+--------------------------------------------------------------------+--------+--------------------------+
; pcie_lib/synthesis/submodules/altera_reset_controller.sdc          ; OK     ; Tue Aug  5 17:47:50 2014 ;
; pcie_lib/synthesis/submodules/altera_pcie_sv_hip_ast_pipen1b.sdc   ; OK     ; Tue Aug  5 17:47:50 2014 ;
; pcie_lib/synthesis/submodules/altera_pcie_sv_hip_ast_rs_serdes.sdc ; OK     ; Tue Aug  5 17:47:50 2014 ;
; pcie_lib/synthesis/submodules/av_xcvr_reconfig.sdc                 ; OK     ; Tue Aug  5 17:47:50 2014 ;
; top_hw.sdc                                                         ; OK     ; Tue Aug  5 17:47:50 2014 ;
+--------------------------------------------------------------------+--------+--------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Name                                                                                                                                                                                               ; Type      ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                                                                                                                                                   ; Source                                                                                                                                                                                                       ; Targets                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; alt_cal_av_edge_detect_clk                                                                                                                                                                               ; Base      ; 10.000 ; 100.0 MHz  ; 0.000 ; 5.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                                                                                                                                          ;                                                                                                                                                                                                              ; { top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd180_det|alt_edge_det_ff1 top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd90_det|alt_edge_det_ff1 top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd0_det|alt_edge_det_ff1 top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd270_det|alt_edge_det_ff1 } ;
; hsma_clk_out_p2                                                                                                                                                                                          ; Base      ; 8.000  ; 125.0 MHz  ; 0.000 ; 4.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                                                                                                                                          ;                                                                                                                                                                                                              ; { hsma_clk_out_p2 }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
; reconfig_xcvr_clk                                                                                                                                                                                        ; Base      ; 8.000  ; 125.0 MHz  ; 0.000 ; 4.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                                                                                                                                          ;                                                                                                                                                                                                              ; { reconfig_xcvr_clk reconfig_xcvr_clk(n) }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; refclk_clk                                                                                                                                                                                               ; Base      ; 10.000 ; 100.0 MHz  ; 0.000 ; 5.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                                                                                                                                          ;                                                                                                                                                                                                              ; { refclk_clk refclk_clk(n) }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
; sv_reconfig_pma_testbus_clk_0                                                                                                                                                                            ; Generated ; 8.000  ; 125.0 MHz  ; 0.000 ; 4.000 ;            ; 1         ; 1           ;       ;        ;           ;            ; false    ; reconfig_xcvr_clk                                                                                                                                                                                        ; top|alt_xcvr_reconfig_0|basic|a5|reg_init[0]|clk                                                                                                                                                             ; { top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|alt_xcvr_arbiter:pif[0].pif_arb|grant[0] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout                                                                                               ; Base      ; 8.000  ; 125.0 MHz  ; 0.000 ; 4.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                                                                                                                                          ;                                                                                                                                                                                                              ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; Generated ; 0.400  ; 2500.0 MHz ; 0.000 ; 0.200 ; 50.00      ; 1         ; 25          ;       ;        ;           ;            ; false    ; refclk_clk                                                                                                                                                                                               ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|refclk                                                       ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.cdr_refclk_mux0|clkout                     ; Generated ; 10.000 ; 100.0 MHz  ; 0.000 ; 5.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; refclk_clk                                                                                                                                                                                               ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.cdr_refclk_mux0|refiqclk0                      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.cdr_refclk_mux0|clkout }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes                           ; Base      ; 0.400  ; 2500.0 MHz ; 0.000 ; 0.200 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                                                                                                                                          ;                                                                                                                                                                                                              ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b                        ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 10        ; 2           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes                           ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes                               ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.cdr_refclk_mux0|clkout                     ; Generated ; 10.000 ; 100.0 MHz  ; 0.000 ; 5.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; refclk_clk                                                                                                                                                                                               ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.cdr_refclk_mux0|refiqclk0                      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.cdr_refclk_mux0|clkout }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes                           ; Base      ; 0.400  ; 2500.0 MHz ; 0.000 ; 0.200 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                                                                                                                                          ;                                                                                                                                                                                                              ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b                        ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 10        ; 2           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes                           ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes                               ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.cdr_refclk_mux0|clkout                     ; Generated ; 10.000 ; 100.0 MHz  ; 0.000 ; 5.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; refclk_clk                                                                                                                                                                                               ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.cdr_refclk_mux0|refiqclk0                      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.cdr_refclk_mux0|clkout }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes                           ; Base      ; 0.400  ; 2500.0 MHz ; 0.000 ; 0.200 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                                                                                                                                          ;                                                                                                                                                                                                              ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b                        ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 10        ; 2           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes                           ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes                               ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.cdr_refclk_mux0|clkout                     ; Generated ; 10.000 ; 100.0 MHz  ; 0.000 ; 5.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; refclk_clk                                                                                                                                                                                               ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.cdr_refclk_mux0|refiqclk5                      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.cdr_refclk_mux0|clkout }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes                           ; Base      ; 0.400  ; 2500.0 MHz ; 0.000 ; 0.200 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                                                                                                                                          ;                                                                                                                                                                                                              ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b                        ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 10        ; 2           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes                           ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes                               ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse    ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp    ; Generated ; 0.400  ; 2500.0 MHz ; 0.000 ; 0.200 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse    ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 5         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|clkcdr1t      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp    ; Generated ; 0.400  ; 2500.0 MHz ; 0.000 ; 0.200 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 5         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|clkcdr1t      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 10        ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|clkcdr1t      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse    ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp    ; Generated ; 0.400  ; 2500.0 MHz ; 0.000 ; 0.200 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse    ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp    ; Generated ; 0.400  ; 2500.0 MHz ; 0.000 ; 0.200 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; Generated ; 2.000  ; 500.0 MHz  ; 0.000 ; 1.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up    ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]   ; Generated ; 4.000  ; 250.0 MHz  ; 0.000 ; 2.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up      ; { top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2] }                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 85C Model Fmax Summary                                                                                                               ;
+------------+-----------------+------------------------------------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                                                 ; Note ;
+------------+-----------------+------------------------------------------------------------------------------------------------------------+------+
; 150.63 MHz ; 150.63 MHz      ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ;      ;
; 170.77 MHz ; 170.77 MHz      ; reconfig_xcvr_clk                                                                                          ;      ;
+------------+-----------------+------------------------------------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 85C Model Setup Summary                                                                                                ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 1.361 ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 2.144 ; 0.000         ;
; n/a                                                                                                        ; 7.984 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 85C Model Hold Summary                                                                                                  ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; reconfig_xcvr_clk                                                                                          ; 0.283  ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 0.368  ; 0.000         ;
; n/a                                                                                                        ; 16.160 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 85C Model Recovery Summary                                                                                             ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 2.178 ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 5.292 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 85C Model Removal Summary                                                                                              ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 0.646 ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 0.663 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 85C Model Minimum Pulse Width Summary                                                                                                                                                                                ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                                                                                                                    ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.998 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.998 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.998 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.998 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; 2.000 ; 0.000         ;
; sv_reconfig_pma_testbus_clk_0                                                                                                                                                                            ; 2.507 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout                                                                                               ; 3.023 ; 0.000         ;
; reconfig_xcvr_clk                                                                                                                                                                                        ; 3.030 ; 0.000         ;
; alt_cal_av_edge_detect_clk                                                                                                                                                                               ; 4.334 ; 0.000         ;
; refclk_clk                                                                                                                                                                                               ; 5.000 ; 0.000         ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                                ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.715 ; 2.523 ; Rise       ; reconfig_xcvr_clk ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.030 ; 1.660 ; Rise       ; reconfig_xcvr_clk ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                                ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.676 ; 1.316 ; Rise       ; reconfig_xcvr_clk ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.435 ; 1.422 ; Rise       ; reconfig_xcvr_clk ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------+--------+------------+-------------------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                               ; Clock Port        ; Rise   ; Fall   ; Clock Edge ; Clock Reference               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------+--------+------------+-------------------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 9.191  ; 10.103 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 10.440 ; 12.016 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 8.582  ;        ; Rise       ; sv_reconfig_pma_testbus_clk_0 ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ;        ; 9.408  ; Fall       ; sv_reconfig_pma_testbus_clk_0 ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------+--------+------------+-------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                               ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 6.160 ; 6.389 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 6.969 ; 7.196 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 6.575 ;       ; Rise       ; sv_reconfig_pma_testbus_clk_0 ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ;       ; 6.841 ; Fall       ; sv_reconfig_pma_testbus_clk_0 ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+


----------------------------------------------
; Slow 1100mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 0C Model Fmax Summary                                                                                                                ;
+------------+-----------------+------------------------------------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                                                 ; Note ;
+------------+-----------------+------------------------------------------------------------------------------------------------------------+------+
; 154.85 MHz ; 154.85 MHz      ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ;      ;
; 174.43 MHz ; 174.43 MHz      ; reconfig_xcvr_clk                                                                                          ;      ;
+------------+-----------------+------------------------------------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 0C Model Setup Summary                                                                                                 ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 1.542 ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 2.267 ; 0.000         ;
; n/a                                                                                                        ; 8.504 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 0C Model Hold Summary                                                                                                   ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; reconfig_xcvr_clk                                                                                          ; 0.263  ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 0.355  ; 0.000         ;
; n/a                                                                                                        ; 15.999 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 0C Model Recovery Summary                                                                                              ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 2.283 ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 5.468 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 0C Model Removal Summary                                                                                               ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 0.579 ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 0.592 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1100mV 0C Model Minimum Pulse Width Summary                                                                                                                                                                                 ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                                                                                                                    ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.999 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.999 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.999 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.999 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; 2.000 ; 0.000         ;
; sv_reconfig_pma_testbus_clk_0                                                                                                                                                                            ; 2.495 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout                                                                                               ; 2.953 ; 0.000         ;
; reconfig_xcvr_clk                                                                                                                                                                                        ; 3.005 ; 0.000         ;
; alt_cal_av_edge_detect_clk                                                                                                                                                                               ; 4.305 ; 0.000         ;
; refclk_clk                                                                                                                                                                                               ; 5.000 ; 0.000         ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                                ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.498 ; 2.273 ; Rise       ; reconfig_xcvr_clk ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 0.763 ; 1.455 ; Rise       ; reconfig_xcvr_clk ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                                ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.850 ; 1.444 ; Rise       ; reconfig_xcvr_clk ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.578 ; 1.528 ; Rise       ; reconfig_xcvr_clk ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------+--------+------------+-------------------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                               ; Clock Port        ; Rise   ; Fall   ; Clock Edge ; Clock Reference               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------+--------+------------+-------------------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 8.833  ; 9.760  ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 10.104 ; 11.496 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 8.190  ;        ; Rise       ; sv_reconfig_pma_testbus_clk_0 ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ;        ; 9.050  ; Fall       ; sv_reconfig_pma_testbus_clk_0 ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------+--------+------------+-------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                               ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 5.999 ; 6.208 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 6.726 ; 7.007 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 6.366 ;       ; Rise       ; sv_reconfig_pma_testbus_clk_0 ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ;       ; 6.636 ; Fall       ; sv_reconfig_pma_testbus_clk_0 ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+


---------------------------------------------
; Slow 1100mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1100mV 85C Model Setup Summary                                                                                                 ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 2.924  ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 3.675  ; 0.000         ;
; n/a                                                                                                        ; 11.589 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1100mV 85C Model Hold Summary                                                                                                  ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; reconfig_xcvr_clk                                                                                          ; 0.172  ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 0.187  ; 0.000         ;
; n/a                                                                                                        ; 13.723 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1100mV 85C Model Recovery Summary                                                                                             ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 4.843 ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 6.138 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1100mV 85C Model Removal Summary                                                                                              ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 0.328 ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 0.345 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1100mV 85C Model Minimum Pulse Width Summary                                                                                                                                                                                ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                                                                                                                    ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.996 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.996 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.996 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.996 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; 2.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout                                                                                               ; 2.944 ; 0.000         ;
; sv_reconfig_pma_testbus_clk_0                                                                                                                                                                            ; 3.197 ; 0.000         ;
; reconfig_xcvr_clk                                                                                                                                                                                        ; 3.238 ; 0.000         ;
; alt_cal_av_edge_detect_clk                                                                                                                                                                               ; 4.600 ; 0.000         ;
; refclk_clk                                                                                                                                                                                               ; 5.000 ; 0.000         ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                                ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.310 ; 2.122 ; Rise       ; reconfig_xcvr_clk ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 0.754 ; 1.392 ; Rise       ; reconfig_xcvr_clk ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                                ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 0.811 ; 0.517 ; Rise       ; reconfig_xcvr_clk ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 0.785 ; 0.672 ; Rise       ; reconfig_xcvr_clk ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                               ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 5.624 ; 6.662 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 6.721 ; 8.411 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 5.292 ;       ; Rise       ; sv_reconfig_pma_testbus_clk_0 ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ;       ; 6.233 ; Fall       ; sv_reconfig_pma_testbus_clk_0 ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                               ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 3.723 ; 3.980 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 4.099 ; 4.526 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 3.965 ;       ; Rise       ; sv_reconfig_pma_testbus_clk_0 ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ;       ; 4.314 ; Fall       ; sv_reconfig_pma_testbus_clk_0 ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+


----------------------------------------------
; Fast 1100mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1100mV 0C Model Setup Summary                                                                                                  ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 3.542  ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 4.095  ; 0.000         ;
; n/a                                                                                                        ; 12.455 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1100mV 0C Model Hold Summary                                                                                                   ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+
; reconfig_xcvr_clk                                                                                          ; 0.160  ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 0.177  ; 0.000         ;
; n/a                                                                                                        ; 13.549 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1100mV 0C Model Recovery Summary                                                                                              ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 5.008 ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 6.370 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1100mV 0C Model Removal Summary                                                                                               ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 0.298 ; 0.000         ;
; reconfig_xcvr_clk                                                                                          ; 0.313 ; 0.000         ;
+------------------------------------------------------------------------------------------------------------+-------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1100mV 0C Model Minimum Pulse Width Summary                                                                                                                                                                                 ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                                                                                                                    ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes                           ; 0.200 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.997 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.997 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.997 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; 0.997 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b                        ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; 1.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; 2.000 ; 0.000         ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout                                                                                               ; 2.980 ; 0.000         ;
; sv_reconfig_pma_testbus_clk_0                                                                                                                                                                            ; 3.204 ; 0.000         ;
; reconfig_xcvr_clk                                                                                                                                                                                        ; 3.223 ; 0.000         ;
; alt_cal_av_edge_detect_clk                                                                                                                                                                               ; 4.618 ; 0.000         ;
; refclk_clk                                                                                                                                                                                               ; 5.000 ; 0.000         ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                                ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.088 ; 1.724 ; Rise       ; reconfig_xcvr_clk ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 0.541 ; 1.107 ; Rise       ; reconfig_xcvr_clk ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                                ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 0.905 ; 0.643 ; Rise       ; reconfig_xcvr_clk ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 0.878 ; 0.771 ; Rise       ; reconfig_xcvr_clk ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                               ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 5.285 ; 6.115 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 6.290 ; 7.545 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 4.964 ;       ; Rise       ; sv_reconfig_pma_testbus_clk_0 ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ;       ; 5.725 ; Fall       ; sv_reconfig_pma_testbus_clk_0 ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                               ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 3.549 ; 3.752 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 3.874 ; 4.209 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 3.752 ;       ; Rise       ; sv_reconfig_pma_testbus_clk_0 ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ;       ; 4.036 ; Fall       ; sv_reconfig_pma_testbus_clk_0 ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+


---------------------------------------------
; Fast 1100mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                                                                                                                                                   ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+--------+----------+---------+---------------------+
; Clock                                                                                                                                                                                                     ; Setup ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+--------+----------+---------+---------------------+
; Worst-case Slack                                                                                                                                                                                          ; 1.361 ; 0.160  ; 2.178    ; 0.298   ; 0.200               ;
;  alt_cal_av_edge_detect_clk                                                                                                                                                                               ; N/A   ; N/A    ; N/A      ; N/A     ; 4.305               ;
;  n/a                                                                                                                                                                                                      ; 7.984 ; 13.549 ; N/A      ; N/A     ; N/A                 ;
;  reconfig_xcvr_clk                                                                                                                                                                                        ; 2.144 ; 0.160  ; 5.292    ; 0.313   ; 3.005               ;
;  refclk_clk                                                                                                                                                                                               ; N/A   ; N/A    ; N/A      ; N/A     ; 5.000               ;
;  sv_reconfig_pma_testbus_clk_0                                                                                                                                                                            ; N/A   ; N/A    ; N/A      ; N/A     ; 2.495               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout                                                                                               ; 1.361 ; 0.177  ; 2.178    ; 0.298   ; 2.944               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; N/A   ; N/A    ; N/A      ; N/A     ; 0.200               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes                           ; N/A   ; N/A    ; N/A      ; N/A     ; 0.200               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b                        ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes                           ; N/A   ; N/A    ; N/A      ; N/A     ; 0.200               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b                        ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes                           ; N/A   ; N/A    ; N/A      ; N/A     ; 0.200               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b                        ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes                           ; N/A   ; N/A    ; N/A      ; N/A     ; 0.200               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b                        ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; N/A   ; N/A    ; N/A      ; N/A     ; 0.996               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; N/A   ; N/A    ; N/A      ; N/A     ; 0.996               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; N/A   ; N/A    ; N/A      ; N/A     ; 1.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; N/A   ; N/A    ; N/A      ; N/A     ; 2.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; N/A   ; N/A    ; N/A      ; N/A     ; 0.996               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; N/A   ; N/A    ; N/A      ; N/A     ; 0.996               ;
; Design-wide TNS                                                                                                                                                                                           ; 0.0   ; 0.0    ; 0.0      ; 0.0     ; 0.0                 ;
;  alt_cal_av_edge_detect_clk                                                                                                                                                                               ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  n/a                                                                                                                                                                                                      ; 0.000 ; 0.000  ; N/A      ; N/A     ; N/A                 ;
;  reconfig_xcvr_clk                                                                                                                                                                                        ; 0.000 ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  refclk_clk                                                                                                                                                                                               ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  sv_reconfig_pma_testbus_clk_0                                                                                                                                                                            ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout                                                                                               ; 0.000 ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr                                                   ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk               ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk          ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes                           ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b                        ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes                           ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b                        ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes                           ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b                        ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes                           ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b                        ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout   ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp    ; N/A   ; N/A    ; N/A      ; N/A     ; 0.000               ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+--------+----------+---------+---------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                                ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.715 ; 2.523 ; Rise       ; reconfig_xcvr_clk ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.030 ; 1.660 ; Rise       ; reconfig_xcvr_clk ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                                ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.850 ; 1.444 ; Rise       ; reconfig_xcvr_clk ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT ; reconfig_xcvr_clk ; 1.578 ; 1.528 ; Rise       ; reconfig_xcvr_clk ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------+--------+------------+-------------------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                               ; Clock Port        ; Rise   ; Fall   ; Clock Edge ; Clock Reference               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------+--------+------------+-------------------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 9.191  ; 10.103 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 10.440 ; 12.016 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 8.582  ;        ; Rise       ; sv_reconfig_pma_testbus_clk_0 ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ;        ; 9.408  ; Fall       ; sv_reconfig_pma_testbus_clk_0 ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+--------+--------+------------+-------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; Data Port                                                                                                                                                                                                                                                                                                                                               ; Clock Port        ; Rise  ; Fall  ; Clock Edge ; Clock Reference               ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 3.549 ; 3.752 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 3.874 ; 4.209 ; Rise       ; reconfig_xcvr_clk             ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ; 3.752 ;       ; Rise       ; sv_reconfig_pma_testbus_clk_0 ;
; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN ; reconfig_xcvr_clk ;       ; 4.036 ; Fall       ; sv_reconfig_pma_testbus_clk_0 ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+-------+-------+------------+-------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                         ;
+--------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin                ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; hsma_clk_out_p2    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; lane_active_led[0] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; lane_active_led[1] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; lane_active_led[2] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; lane_active_led[3] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; L0_led             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; alive_led          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; comp_led           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; gen2_led           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-------------------------------------------------------------------------+
; Input Transition Times                                                  ;
+----------------------+--------------+-----------------+-----------------+
; Pin                  ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+----------------------+--------------+-----------------+-----------------+
; req_compliance_pb    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; set_compliance_mode  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; reconfig_xcvr_clk    ; LVDS         ; 2000 ps         ; 2000 ps         ;
; perstn               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; local_rstn           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; reconfig_xcvr_clk(n) ; LVDS         ; 2000 ps         ; 2000 ps         ;
+----------------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 900mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; hsma_clk_out_p2    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.84e-07 V                   ; 2.43 V              ; -0.0548 V           ; 0.179 V                              ; 0.103 V                              ; 4.48e-10 s                  ; 4.32e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.84e-07 V                  ; 2.43 V             ; -0.0548 V          ; 0.179 V                             ; 0.103 V                             ; 4.48e-10 s                 ; 4.32e-10 s                 ; No                        ; Yes                       ;
; lane_active_led[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.01e-07 V                   ; 2.41 V              ; -0.0344 V           ; 0.195 V                              ; 0.125 V                              ; 4.58e-10 s                  ; 4.59e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.01e-07 V                  ; 2.41 V             ; -0.0344 V          ; 0.195 V                             ; 0.125 V                             ; 4.58e-10 s                 ; 4.59e-10 s                 ; No                        ; Yes                       ;
; lane_active_led[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.06e-07 V                   ; 2.42 V              ; -0.0497 V           ; 0.184 V                              ; 0.113 V                              ; 4.51e-10 s                  ; 4.41e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.06e-07 V                  ; 2.42 V             ; -0.0497 V          ; 0.184 V                             ; 0.113 V                             ; 4.51e-10 s                 ; 4.41e-10 s                 ; No                        ; Yes                       ;
; lane_active_led[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.01e-07 V                   ; 2.41 V              ; -0.0344 V           ; 0.195 V                              ; 0.125 V                              ; 4.58e-10 s                  ; 4.59e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.01e-07 V                  ; 2.41 V             ; -0.0344 V          ; 0.195 V                             ; 0.125 V                             ; 4.58e-10 s                 ; 4.59e-10 s                 ; No                        ; Yes                       ;
; lane_active_led[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.06e-07 V                   ; 2.42 V              ; -0.0497 V           ; 0.184 V                              ; 0.113 V                              ; 4.51e-10 s                  ; 4.41e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.06e-07 V                  ; 2.42 V             ; -0.0497 V          ; 0.184 V                             ; 0.113 V                             ; 4.51e-10 s                 ; 4.41e-10 s                 ; No                        ; Yes                       ;
; L0_led             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.01e-07 V                   ; 2.41 V              ; -0.0344 V           ; 0.195 V                              ; 0.125 V                              ; 4.58e-10 s                  ; 4.59e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.01e-07 V                  ; 2.41 V             ; -0.0344 V          ; 0.195 V                             ; 0.125 V                             ; 4.58e-10 s                 ; 4.59e-10 s                 ; No                        ; Yes                       ;
; alive_led          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.06e-07 V                   ; 2.42 V              ; -0.0497 V           ; 0.184 V                              ; 0.113 V                              ; 4.51e-10 s                  ; 4.41e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.06e-07 V                  ; 2.42 V             ; -0.0497 V          ; 0.184 V                             ; 0.113 V                             ; 4.51e-10 s                 ; 4.41e-10 s                 ; No                        ; Yes                       ;
; comp_led           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.84e-07 V                   ; 2.43 V              ; -0.0548 V           ; 0.179 V                              ; 0.103 V                              ; 4.48e-10 s                  ; 4.32e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.84e-07 V                  ; 2.43 V             ; -0.0548 V          ; 0.179 V                             ; 0.103 V                             ; 4.48e-10 s                 ; 4.32e-10 s                 ; No                        ; Yes                       ;
; gen2_led           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.01e-07 V                   ; 2.41 V              ; -0.0344 V           ; 0.195 V                              ; 0.125 V                              ; 4.58e-10 s                  ; 4.59e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.01e-07 V                  ; 2.41 V             ; -0.0344 V          ; 0.195 V                             ; 0.125 V                             ; 4.58e-10 s                 ; 4.59e-10 s                 ; No                        ; Yes                       ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 900mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; hsma_clk_out_p2    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.22e-05 V                   ; 2.39 V              ; -0.0362 V           ; 0.194 V                              ; 0.15 V                               ; 4.63e-10 s                  ; 4.68e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.22e-05 V                  ; 2.39 V             ; -0.0362 V          ; 0.194 V                             ; 0.15 V                              ; 4.63e-10 s                 ; 4.68e-10 s                 ; No                        ; Yes                       ;
; lane_active_led[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.38e-05 V                   ; 2.38 V              ; -0.0222 V           ; 0.224 V                              ; 0.076 V                              ; 4.79e-10 s                  ; 5.39e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.38e-05 V                  ; 2.38 V             ; -0.0222 V          ; 0.224 V                             ; 0.076 V                             ; 4.79e-10 s                 ; 5.39e-10 s                 ; No                        ; Yes                       ;
; lane_active_led[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.43e-05 V                   ; 2.39 V              ; -0.033 V            ; 0.202 V                              ; 0.178 V                              ; 4.69e-10 s                  ; 4.81e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.43e-05 V                  ; 2.39 V             ; -0.033 V           ; 0.202 V                             ; 0.178 V                             ; 4.69e-10 s                 ; 4.81e-10 s                 ; No                        ; Yes                       ;
; lane_active_led[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.38e-05 V                   ; 2.38 V              ; -0.0222 V           ; 0.224 V                              ; 0.076 V                              ; 4.79e-10 s                  ; 5.39e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.38e-05 V                  ; 2.38 V             ; -0.0222 V          ; 0.224 V                             ; 0.076 V                             ; 4.79e-10 s                 ; 5.39e-10 s                 ; No                        ; Yes                       ;
; lane_active_led[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.43e-05 V                   ; 2.39 V              ; -0.033 V            ; 0.202 V                              ; 0.178 V                              ; 4.69e-10 s                  ; 4.81e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.43e-05 V                  ; 2.39 V             ; -0.033 V           ; 0.202 V                             ; 0.178 V                             ; 4.69e-10 s                 ; 4.81e-10 s                 ; No                        ; Yes                       ;
; L0_led             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.38e-05 V                   ; 2.38 V              ; -0.0222 V           ; 0.224 V                              ; 0.076 V                              ; 4.79e-10 s                  ; 5.39e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.38e-05 V                  ; 2.38 V             ; -0.0222 V          ; 0.224 V                             ; 0.076 V                             ; 4.79e-10 s                 ; 5.39e-10 s                 ; No                        ; Yes                       ;
; alive_led          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.43e-05 V                   ; 2.39 V              ; -0.033 V            ; 0.202 V                              ; 0.178 V                              ; 4.69e-10 s                  ; 4.81e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.43e-05 V                  ; 2.39 V             ; -0.033 V           ; 0.202 V                             ; 0.178 V                             ; 4.69e-10 s                 ; 4.81e-10 s                 ; No                        ; Yes                       ;
; comp_led           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.22e-05 V                   ; 2.39 V              ; -0.0362 V           ; 0.194 V                              ; 0.15 V                               ; 4.63e-10 s                  ; 4.68e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.22e-05 V                  ; 2.39 V             ; -0.0362 V          ; 0.194 V                             ; 0.15 V                              ; 4.63e-10 s                 ; 4.68e-10 s                 ; No                        ; Yes                       ;
; gen2_led           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.38e-05 V                   ; 2.38 V              ; -0.0222 V           ; 0.224 V                              ; 0.076 V                              ; 4.79e-10 s                  ; 5.39e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 2.38e-05 V                  ; 2.38 V             ; -0.0222 V          ; 0.224 V                             ; 0.076 V                             ; 4.79e-10 s                 ; 5.39e-10 s                 ; No                        ; Yes                       ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 900mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; hsma_clk_out_p2    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.46e-06 V                   ; 2.93 V              ; -0.135 V            ; 0.316 V                              ; 0.269 V                              ; 2.68e-10 s                  ; 2.7e-10 s                   ; No                         ; Yes                        ; 2.75 V                      ; 3.46e-06 V                  ; 2.93 V             ; -0.135 V           ; 0.316 V                             ; 0.269 V                             ; 2.68e-10 s                 ; 2.7e-10 s                  ; No                        ; Yes                       ;
; lane_active_led[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.85e-06 V                   ; 2.9 V               ; -0.0978 V           ; 0.335 V                              ; 0.142 V                              ; 2.8e-10 s                   ; 4.21e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.85e-06 V                  ; 2.9 V              ; -0.0978 V          ; 0.335 V                             ; 0.142 V                             ; 2.8e-10 s                  ; 4.21e-10 s                 ; No                        ; No                        ;
; lane_active_led[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.97e-06 V                   ; 2.93 V              ; -0.12 V             ; 0.322 V                              ; 0.296 V                              ; 2.71e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 3.97e-06 V                  ; 2.93 V             ; -0.12 V            ; 0.322 V                             ; 0.296 V                             ; 2.71e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
; lane_active_led[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.85e-06 V                   ; 2.9 V               ; -0.0978 V           ; 0.335 V                              ; 0.142 V                              ; 2.8e-10 s                   ; 4.21e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.85e-06 V                  ; 2.9 V              ; -0.0978 V          ; 0.335 V                             ; 0.142 V                             ; 2.8e-10 s                  ; 4.21e-10 s                 ; No                        ; No                        ;
; lane_active_led[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.97e-06 V                   ; 2.93 V              ; -0.12 V             ; 0.322 V                              ; 0.296 V                              ; 2.71e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 3.97e-06 V                  ; 2.93 V             ; -0.12 V            ; 0.322 V                             ; 0.296 V                             ; 2.71e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
; L0_led             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.85e-06 V                   ; 2.9 V               ; -0.0978 V           ; 0.335 V                              ; 0.142 V                              ; 2.8e-10 s                   ; 4.21e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.85e-06 V                  ; 2.9 V              ; -0.0978 V          ; 0.335 V                             ; 0.142 V                             ; 2.8e-10 s                  ; 4.21e-10 s                 ; No                        ; No                        ;
; alive_led          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.97e-06 V                   ; 2.93 V              ; -0.12 V             ; 0.322 V                              ; 0.296 V                              ; 2.71e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 3.97e-06 V                  ; 2.93 V             ; -0.12 V            ; 0.322 V                             ; 0.296 V                             ; 2.71e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
; comp_led           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.46e-06 V                   ; 2.93 V              ; -0.135 V            ; 0.316 V                              ; 0.269 V                              ; 2.68e-10 s                  ; 2.7e-10 s                   ; No                         ; Yes                        ; 2.75 V                      ; 3.46e-06 V                  ; 2.93 V             ; -0.135 V           ; 0.316 V                             ; 0.269 V                             ; 2.68e-10 s                 ; 2.7e-10 s                  ; No                        ; Yes                       ;
; gen2_led           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.85e-06 V                   ; 2.9 V               ; -0.0978 V           ; 0.335 V                              ; 0.142 V                              ; 2.8e-10 s                   ; 4.21e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.85e-06 V                  ; 2.9 V              ; -0.0978 V          ; 0.335 V                             ; 0.142 V                             ; 2.8e-10 s                  ; 4.21e-10 s                 ; No                        ; No                        ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 900mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; hsma_clk_out_p2    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.46e-06 V                   ; 2.93 V              ; -0.135 V            ; 0.316 V                              ; 0.269 V                              ; 2.68e-10 s                  ; 2.7e-10 s                   ; No                         ; Yes                        ; 2.75 V                      ; 3.46e-06 V                  ; 2.93 V             ; -0.135 V           ; 0.316 V                             ; 0.269 V                             ; 2.68e-10 s                 ; 2.7e-10 s                  ; No                        ; Yes                       ;
; lane_active_led[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.85e-06 V                   ; 2.9 V               ; -0.0978 V           ; 0.335 V                              ; 0.142 V                              ; 2.8e-10 s                   ; 4.21e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.85e-06 V                  ; 2.9 V              ; -0.0978 V          ; 0.335 V                             ; 0.142 V                             ; 2.8e-10 s                  ; 4.21e-10 s                 ; No                        ; No                        ;
; lane_active_led[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.97e-06 V                   ; 2.93 V              ; -0.12 V             ; 0.322 V                              ; 0.296 V                              ; 2.71e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 3.97e-06 V                  ; 2.93 V             ; -0.12 V            ; 0.322 V                             ; 0.296 V                             ; 2.71e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
; lane_active_led[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.85e-06 V                   ; 2.9 V               ; -0.0978 V           ; 0.335 V                              ; 0.142 V                              ; 2.8e-10 s                   ; 4.21e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.85e-06 V                  ; 2.9 V              ; -0.0978 V          ; 0.335 V                             ; 0.142 V                             ; 2.8e-10 s                  ; 4.21e-10 s                 ; No                        ; No                        ;
; lane_active_led[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.97e-06 V                   ; 2.93 V              ; -0.12 V             ; 0.322 V                              ; 0.296 V                              ; 2.71e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 3.97e-06 V                  ; 2.93 V             ; -0.12 V            ; 0.322 V                             ; 0.296 V                             ; 2.71e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
; L0_led             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.85e-06 V                   ; 2.9 V               ; -0.0978 V           ; 0.335 V                              ; 0.142 V                              ; 2.8e-10 s                   ; 4.21e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.85e-06 V                  ; 2.9 V              ; -0.0978 V          ; 0.335 V                             ; 0.142 V                             ; 2.8e-10 s                  ; 4.21e-10 s                 ; No                        ; No                        ;
; alive_led          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.97e-06 V                   ; 2.93 V              ; -0.12 V             ; 0.322 V                              ; 0.296 V                              ; 2.71e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 3.97e-06 V                  ; 2.93 V             ; -0.12 V            ; 0.322 V                             ; 0.296 V                             ; 2.71e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
; comp_led           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.46e-06 V                   ; 2.93 V              ; -0.135 V            ; 0.316 V                              ; 0.269 V                              ; 2.68e-10 s                  ; 2.7e-10 s                   ; No                         ; Yes                        ; 2.75 V                      ; 3.46e-06 V                  ; 2.93 V             ; -0.135 V           ; 0.316 V                             ; 0.269 V                             ; 2.68e-10 s                 ; 2.7e-10 s                  ; No                        ; Yes                       ;
; gen2_led           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.85e-06 V                   ; 2.9 V               ; -0.0978 V           ; 0.335 V                              ; 0.142 V                              ; 2.8e-10 s                   ; 4.21e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.85e-06 V                  ; 2.9 V              ; -0.0978 V          ; 0.335 V                             ; 0.142 V                             ; 2.8e-10 s                  ; 4.21e-10 s                 ; No                        ; No                        ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+------------+------------+----------+
; From Clock                                                                                                 ; To Clock                                                                                                   ; RR Paths   ; FR Paths   ; RF Paths   ; FF Paths ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+------------+------------+----------+
; alt_cal_av_edge_detect_clk                                                                                 ; reconfig_xcvr_clk                                                                                          ; false path ; 0          ; 0          ; 0        ;
; reconfig_xcvr_clk                                                                                          ; reconfig_xcvr_clk                                                                                          ; 38443      ; 0          ; 0          ; 0        ;
; sv_reconfig_pma_testbus_clk_0                                                                              ; reconfig_xcvr_clk                                                                                          ; false path ; false path ; 0          ; 0        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; reconfig_xcvr_clk                                                                                          ; false path ; 0          ; 0          ; 0        ;
; reconfig_xcvr_clk                                                                                          ; sv_reconfig_pma_testbus_clk_0                                                                              ; false path ; 0          ; false path ; 0        ;
; reconfig_xcvr_clk                                                                                          ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; false path ; 0          ; 0          ; 0        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 1212919    ; 0          ; 0          ; 0        ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+------------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                                                                                            ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+------------+------------+----------+
; From Clock                                                                                                 ; To Clock                                                                                                   ; RR Paths   ; FR Paths   ; RF Paths   ; FF Paths ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+------------+------------+----------+
; alt_cal_av_edge_detect_clk                                                                                 ; reconfig_xcvr_clk                                                                                          ; false path ; 0          ; 0          ; 0        ;
; reconfig_xcvr_clk                                                                                          ; reconfig_xcvr_clk                                                                                          ; 38443      ; 0          ; 0          ; 0        ;
; sv_reconfig_pma_testbus_clk_0                                                                              ; reconfig_xcvr_clk                                                                                          ; false path ; false path ; 0          ; 0        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; reconfig_xcvr_clk                                                                                          ; false path ; 0          ; 0          ; 0        ;
; reconfig_xcvr_clk                                                                                          ; sv_reconfig_pma_testbus_clk_0                                                                              ; false path ; 0          ; false path ; 0        ;
; reconfig_xcvr_clk                                                                                          ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; false path ; 0          ; 0          ; 0        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 1212919    ; 0          ; 0          ; 0        ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+------------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                                                                                      ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                                                                 ; To Clock                                                                                                   ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
; reconfig_xcvr_clk                                                                                          ; alt_cal_av_edge_detect_clk                                                                                 ; false path ; 0        ; false path ; 0        ;
; reconfig_xcvr_clk                                                                                          ; reconfig_xcvr_clk                                                                                          ; 394        ; 0        ; 0          ; 0        ;
; reconfig_xcvr_clk                                                                                          ; sv_reconfig_pma_testbus_clk_0                                                                              ; 0          ; 0        ; false path ; 0        ;
; reconfig_xcvr_clk                                                                                          ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; false path ; 0        ; 0          ; 0        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 13084      ; 0        ; 0          ; 0        ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                                                                 ; To Clock                                                                                                   ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
; reconfig_xcvr_clk                                                                                          ; alt_cal_av_edge_detect_clk                                                                                 ; false path ; 0        ; false path ; 0        ;
; reconfig_xcvr_clk                                                                                          ; reconfig_xcvr_clk                                                                                          ; 394        ; 0        ; 0          ; 0        ;
; reconfig_xcvr_clk                                                                                          ; sv_reconfig_pma_testbus_clk_0                                                                              ; 0          ; 0        ; false path ; 0        ;
; reconfig_xcvr_clk                                                                                          ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; false path ; 0        ; 0          ; 0        ;
; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout ; 13084      ; 0        ; 0          ; 0        ;
+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 0     ; 0    ;
; Unconstrained Input Port Paths  ; 0     ; 0    ;
; Unconstrained Output Ports      ; 0     ; 0    ;
; Unconstrained Output Port Paths ; 0     ; 0    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 14.0.0 Build 200 06/17/2014 SJ Full Version
    Info: Processing started: Tue Aug  5 17:47:35 2014
Info: Command: quartus_sta top -c top
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 24 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 12 of the 12 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity alt_cal_av
        Info (332166): set_disable_timing [get_cells -compatibility_mode *|alt_cal_channel[*]] -to q 
        Info (332166): set_disable_timing [get_cells -compatibility_mode *|alt_cal_busy] -to q 
    Info (332165): Entity alt_cal_edge_detect
        Info (332166): create_clock -name alt_cal_av_edge_detect_clk -period 10 [get_registers *alt_cal_av*|*pd*_det|alt_edge_det_ff?]
        Info (332166): set_clock_groups -exclusive -group [get_clocks {alt_cal_av_edge_detect_clk}]
    Info (332165): Entity alt_xcvr_resync
        Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}
Info (332104): Reading SDC File: 'pcie_lib/synthesis/submodules/altera_reset_controller.sdc'
Info (332104): Reading SDC File: 'pcie_lib/synthesis/submodules/altera_pcie_sv_hip_ast_pipen1b.sdc'
Warning (332174): Ignored filter at altera_pcie_sv_hip_ast_pipen1b.sdc(22): *stratixv_hssi_gen3_pcie_hip|testinhip[*] could not be matched with a pin
Warning (332049): Ignored set_false_path at altera_pcie_sv_hip_ast_pipen1b.sdc(22): Argument <from> is an empty collection
    Info (332050): set_false_path -from [ get_pins -compatibility {*stratixv_hssi_gen3_pcie_hip|testinhip[*]}]
Warning (332174): Ignored filter at altera_pcie_sv_hip_ast_pipen1b.sdc(23): *stratixv_hssi_gen3_pcie_hip|testin1hip[*] could not be matched with a pin
Warning (332049): Ignored set_false_path at altera_pcie_sv_hip_ast_pipen1b.sdc(23): Argument <from> is an empty collection
    Info (332050): set_false_path -from [ get_pins -compatibility {*stratixv_hssi_gen3_pcie_hip|testin1hip[*]}]
Info (332104): Reading SDC File: 'pcie_lib/synthesis/submodules/altera_pcie_sv_hip_ast_rs_serdes.sdc'
Warning (332174): Ignored filter at altera_pcie_sv_hip_ast_rs_serdes.sdc(22): *sv_xcvr_pipe_native* could not be matched with a register
Warning (332049): Ignored set_false_path at altera_pcie_sv_hip_ast_rs_serdes.sdc(22): Argument <from> is an empty collection
    Info (332050): set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
Info (332104): Reading SDC File: 'pcie_lib/synthesis/submodules/av_xcvr_reconfig.sdc'
Info (332104): Reading SDC File: 'top_hw.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|refclk} -multiply_by 25 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr}
    Info (332110): create_clock -period 0.400 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes}
    Info (332110): create_clock -period 0.400 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes}
    Info (332110): create_clock -period 0.400 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes}
    Info (332110): create_clock -period 0.400 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|clkcdr1t} -divide_by 5 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|clkcdr1t} -divide_by 5 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|clkcdr1t} -divide_by 10 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.cdr_refclk_mux0|refiqclk5} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.cdr_refclk_mux0|clkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.cdr_refclk_mux0|clkout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.cdr_refclk_mux0|refiqclk0} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.cdr_refclk_mux0|clkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.cdr_refclk_mux0|clkout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.cdr_refclk_mux0|refiqclk0} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.cdr_refclk_mux0|clkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.cdr_refclk_mux0|clkout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.cdr_refclk_mux0|refiqclk0} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.cdr_refclk_mux0|clkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.cdr_refclk_mux0|clkout}
    Info (332110): create_clock -period 8.000 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes} -divide_by 10 -multiply_by 2 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes} -divide_by 10 -multiply_by 2 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes} -divide_by 10 -multiply_by 2 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes} -divide_by 10 -multiply_by 2 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk}
    Info (332110): set_max_delay -to [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN }] 20.000
    Info (332110): set_min_delay -to [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT }] -10.000
    Info (332110): set_max_delay -to [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN }] 20.000
    Info (332110): set_min_delay -to [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[3].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[3].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[2].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[2].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[1].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[1].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] -10.000
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at top_hw.sdc(9): altera_reserved_tck could not be matched with a clock
Warning (332174): Ignored filter at top_hw.sdc(9): altera_reserved_tdi could not be matched with a port
Warning (332049): Ignored set_input_delay at top_hw.sdc(9): Argument <targets> is an empty collection
    Info (332050): set_input_delay  -add_delay  -clock [get_clocks {altera_reserved_tck}]  20.000 [get_ports {altera_reserved_tdi}]
Warning (332049): Ignored set_input_delay at top_hw.sdc(9): Argument -clock is an empty collection
Warning (332174): Ignored filter at top_hw.sdc(10): altera_reserved_tms could not be matched with a port
Warning (332049): Ignored set_input_delay at top_hw.sdc(10): Argument <targets> is an empty collection
    Info (332050): set_input_delay  -add_delay  -clock [get_clocks {altera_reserved_tck}]  20.000 [get_ports {altera_reserved_tms}]
Warning (332049): Ignored set_input_delay at top_hw.sdc(10): Argument -clock is an empty collection
Warning (332174): Ignored filter at top_hw.sdc(11): altera_reserved_tdo could not be matched with a port
Warning (332049): Ignored set_output_delay at top_hw.sdc(11): Argument <targets> is an empty collection
    Info (332050): set_output_delay -add_delay  -clock [get_clocks {altera_reserved_tck}]  20.000 [get_ports {altera_reserved_tdo}]
Warning (332049): Ignored set_output_delay at top_hw.sdc(11): Argument -clock is an empty collection
Warning (332049): Ignored set_false_path at top_hw.sdc(25): Argument <from> is an empty collection
    Info (332050): set_false_path -from [get_clocks {altera_reserved_tck}] -to [get_clocks *]
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|pldclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top~BURIED_SYNC_DATA108
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[1].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[2].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[3].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst|avmmclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_SYNC_DATA18
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst|avmmclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_SYNC_DATA18
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1100mV 85C Model
Info (332146): Worst-case setup slack is 1.361
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     1.361               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     2.144               0.000 reconfig_xcvr_clk 
    Info (332119):     7.984               0.000 n/a 
Info (332146): Worst-case hold slack is 0.283
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.283               0.000 reconfig_xcvr_clk 
    Info (332119):     0.368               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):    16.160               0.000 n/a 
Info (332146): Worst-case recovery slack is 2.178
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     2.178               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     5.292               0.000 reconfig_xcvr_clk 
Info (332146): Worst-case removal slack is 0.646
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.646               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     0.663               0.000 reconfig_xcvr_clk 
Info (332146): Worst-case minimum pulse width slack is 0.200
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.998               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.998               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.998               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.998               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout 
    Info (332119):     2.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout 
    Info (332119):     2.507               0.000 sv_reconfig_pma_testbus_clk_0 
    Info (332119):     3.023               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     3.030               0.000 reconfig_xcvr_clk 
    Info (332119):     4.334               0.000 alt_cal_av_edge_detect_clk 
    Info (332119):     5.000               0.000 refclk_clk 
Info: Analyzing Slow 1100mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|pldclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top~BURIED_SYNC_DATA108
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[1].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[2].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[3].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst|avmmclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_SYNC_DATA18
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst|avmmclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_SYNC_DATA18
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 1.542
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     1.542               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     2.267               0.000 reconfig_xcvr_clk 
    Info (332119):     8.504               0.000 n/a 
Info (332146): Worst-case hold slack is 0.263
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.263               0.000 reconfig_xcvr_clk 
    Info (332119):     0.355               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):    15.999               0.000 n/a 
Info (332146): Worst-case recovery slack is 2.283
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     2.283               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     5.468               0.000 reconfig_xcvr_clk 
Info (332146): Worst-case removal slack is 0.579
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.579               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     0.592               0.000 reconfig_xcvr_clk 
Info (332146): Worst-case minimum pulse width slack is 0.200
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.999               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.999               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.999               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.999               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout 
    Info (332119):     2.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout 
    Info (332119):     2.495               0.000 sv_reconfig_pma_testbus_clk_0 
    Info (332119):     2.953               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     3.005               0.000 reconfig_xcvr_clk 
    Info (332119):     4.305               0.000 alt_cal_av_edge_detect_clk 
    Info (332119):     5.000               0.000 refclk_clk 
Info: Analyzing Fast 1100mV 85C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|pldclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top~BURIED_SYNC_DATA108
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[1].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[2].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[3].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst|avmmclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_SYNC_DATA18
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst|avmmclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_SYNC_DATA18
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 2.924
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     2.924               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     3.675               0.000 reconfig_xcvr_clk 
    Info (332119):    11.589               0.000 n/a 
Info (332146): Worst-case hold slack is 0.172
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.172               0.000 reconfig_xcvr_clk 
    Info (332119):     0.187               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):    13.723               0.000 n/a 
Info (332146): Worst-case recovery slack is 4.843
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     4.843               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     6.138               0.000 reconfig_xcvr_clk 
Info (332146): Worst-case removal slack is 0.328
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.328               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     0.345               0.000 reconfig_xcvr_clk 
Info (332146): Worst-case minimum pulse width slack is 0.200
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.996               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.996               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.996               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.996               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout 
    Info (332119):     2.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout 
    Info (332119):     2.944               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     3.197               0.000 sv_reconfig_pma_testbus_clk_0 
    Info (332119):     3.238               0.000 reconfig_xcvr_clk 
    Info (332119):     4.600               0.000 alt_cal_av_edge_detect_clk 
    Info (332119):     5.000               0.000 refclk_clk 
Info: Analyzing Fast 1100mV 0C Model
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|pldclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top~BURIED_SYNC_DATA108
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[1].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[2].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[3].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst|avmmclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_SYNC_DATA18
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst|avmmclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_SYNC_DATA18
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 3.542
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     3.542               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     4.095               0.000 reconfig_xcvr_clk 
    Info (332119):    12.455               0.000 n/a 
Info (332146): Worst-case hold slack is 0.160
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.160               0.000 reconfig_xcvr_clk 
    Info (332119):     0.177               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):    13.549               0.000 n/a 
Info (332146): Worst-case recovery slack is 5.008
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     5.008               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     6.370               0.000 reconfig_xcvr_clk 
Info (332146): Worst-case removal slack is 0.298
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.298               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     0.313               0.000 reconfig_xcvr_clk 
Info (332146): Worst-case minimum pulse width slack is 0.200
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.200               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes 
    Info (332119):     0.997               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.997               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.997               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     0.997               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout 
    Info (332119):     1.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout 
    Info (332119):     2.000               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout 
    Info (332119):     2.980               0.000 top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout 
    Info (332119):     3.204               0.000 sv_reconfig_pma_testbus_clk_0 
    Info (332119):     3.223               0.000 reconfig_xcvr_clk 
    Info (332119):     4.618               0.000 alt_cal_av_edge_detect_clk 
    Info (332119):     5.000               0.000 refclk_clk 
Info (332101): Design is fully constrained for setup requirements
Info (332101): Design is fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings
    Info: Peak virtual memory: 1985 megabytes
    Info: Processing ended: Tue Aug  5 17:48:19 2014
    Info: Elapsed time: 00:00:44
    Info: Total CPU time (on all processors): 00:01:20


