top |

2014.08.05.17:37:26 | Datasheet

Overview

clk_0 | top

All Components
alt_xcvr_reconfig_0 alt_xcvr_reconfig 14.0
pcie_256_hip_avmm_0 altera_pcie_256_hip_avmm 14.0
onchip_memory2_0 altera_avalon_onchip_memory2 14.0
Memory Map

| pcie_reconfig_driver_0 | pcie_256_hip_avmm_0
reconfig_mgmt | Rxm_BAR2 | dma_rd_master | dma_wr_master | wr_dcm_master | rd_dcm_master
alt_xcvr_reconfig_0 |  |  |  |  |  |
reconfig_mgmt | 0x00000000 |  |  |  |  |
pcie_256_hip_avmm_0 |  |  |  |  |  |
Txs |  |  |  |  | 0x00000000 | 0x00000000
wr_dts_slave |  |  | 0x00004000 |  |  |
rd_dts_slave |  |  | 0x00002000 |  |  |
onchip_memory2_0 |  |  |  |  |  |
s1 |  | 0x00000000 | 0x00000000 |  |  |
s2 |  |  |  | 0x00000000 |  |

## pcie_reconfig_driver_0

altera_pcie_reconfig_driver v14.0

clk_0 | clk | pcie_reconfig_driver_0
reconfig_xcvr_clk
clk_reset
reconfig_xcvr_rst
alt_xcvr_reconfig_0 | cal_busy_in
cal_busy_in
pcie_256_hip_avmm_0 | coreclkout
pld_clk
|  | reconfig_mgmt | alt_xcvr_reconfig_0
|  | reconfig_mgmt
|  | reconfig_busy
|  | reconfig_busy
|  | hip_currentspeed | pcie_256_hip_avmm_0
|  | hip_currentspeed
|  | hip_status_drv
|  | hip_status

## Parameters
INTENDED_DEVICE_FAMILY | ARRIAV
gen123_lane_rate_mode_hwtcl | Gen2 (5.0 Gbps)
number_of_reconfig_interfaces | 5
enable_cal_busy_hwtcl | 1
AUTO_RECONFIG_XCVR_CLK_CLOCK_RATE | 50000000
AUTO_PLD_CLK_CLOCK_RATE | 125000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_xcvr_reconfig_0

alt_xcvr_reconfig v14.0

clk_0 | clk | alt_xcvr_reconfig_0
mgmt_clk_clk
clk_reset
mgmt_rst_reset
pcie_reconfig_driver_0 | reconfig_mgmt
reconfig_mgmt
reconfig_busy
reconfig_busy
pcie_256_hip_avmm_0 | reconfig_to_xcvr
reconfig_to_xcvr
|  | cal_busy_in | pcie_reconfig_driver_0
|  | cal_busy_in
|  | reconfig_from_xcvr | pcie_256_hip_avmm_0
|  | reconfig_from_xcvr

## Parameters
device_family | ARRIAV
number_of_reconfig_interfaces | 5
gui_split_sizes |
enable_offset | 1
enable_lc | 0
enable_dcd | 1
enable_dcd_power_up | 0
enable_analog | 0
enable_eyemon | 0
ber_en | 0
enable_ber | 0
enable_dfe | 0
enable_adce | 0
enable_mif | 0
gui_enable_pll | 0
enable_pll | 0
gui_cal_status_port | false
AUTO_MGMT_CLK_CLK_CLOCK_RATE | 50000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## clk_0

clock_source v14.0

## Parameters
clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## pcie_256_hip_avmm_0

altera_pcie_256_hip_avmm v14.0

alt_xcvr_reconfig_0 | reconfig_from_xcvr | pcie_256_hip_avmm_0
reconfig_from_xcvr
pcie_reconfig_driver_0 | hip_currentspeed
hip_currentspeed
hip_status_drv
hip_status
|  | coreclkout | onchip_memory2_0
|  | clk1
|  | coreclkout
|  | clk2
|  | Rxm_BAR2
|  | s1
|  | dma_rd_master
|  | s1
|  | dma_wr_master
|  | s2
|  | nreset_status
|  | reset1
|  | nreset_status
|  | reset2
|  | reconfig_to_xcvr | alt_xcvr_reconfig_0
|  | reconfig_to_xcvr
|  | coreclkout | pcie_reconfig_driver_0
|  | pld_clk

## Parameters
INTENDED_DEVICE_FAMILY | ARRIAV
pcie_qsys | 1
lane_mask_hwtcl | x4
gen123_lane_rate_mode_hwtcl | Gen2 (5.0 Gbps)
app_interface_width_hwtcl | 128
DMA_WIDTH | 128
DMA_BE_WIDTH | 16
DMA_BRST_CNT_W | 6
port_type_hwtcl | Native endpoint
pcie_spec_version_hwtcl | 2.1
rxbuffer_rxreq_hwtcl | Low
pll_refclk_freq_hwtcl | 100 MHz
set_pld_clk_x1_625MHz_hwtcl | 0
internal_controller_hwtcl | 1
enable_cra_hwtcl | 0
enable_rxm_burst_hwtcl | 0
in_cvp_mode_hwtcl | 0
enable_tl_only_sim_hwtcl | 0
use_atx_pll_hwtcl | 0
hip_tag_checking_hwtcl | 1
enable_power_on_rst_pulse_hwtcl | 0
enable_pcisigtest_hwtcl | 0
SLAVE_ADDRESS_MAP_0 | 0
SLAVE_ADDRESS_MAP_1 | 0
SLAVE_ADDRESS_MAP_2 | 12
SLAVE_ADDRESS_MAP_3 | 0
SLAVE_ADDRESS_MAP_4 | 0
SLAVE_ADDRESS_MAP_5 | 0
RD_SLAVE_ADDRESS_MAP | 15
WR_SLAVE_ADDRESS_MAP | 12
NUM_PREFETCH_MASTERS | 1
bar0_type_hwtcl | 64
bar0_size_mask_hwtcl | 9
bar0_io_space_hwtcl | Disabled
bar0_64bit_mem_space_hwtcl | Enabled
bar0_prefetchable_hwtcl | Enabled
bar1_type_hwtcl | 1
bar1_size_mask_hwtcl | 0
bar1_io_space_hwtcl | Disabled
bar1_prefetchable_hwtcl | Disabled
bar2_type_hwtcl | 64
bar2_size_mask_hwtcl | 12
bar2_io_space_hwtcl | Disabled
bar2_64bit_mem_space_hwtcl | Enabled
bar2_prefetchable_hwtcl | Enabled
bar3_type_hwtcl | 1
bar3_size_mask_hwtcl | 0
bar3_io_space_hwtcl | Disabled
bar3_prefetchable_hwtcl | Disabled
bar4_type_hwtcl | 1
bar4_size_mask_hwtcl | 0
bar4_io_space_hwtcl | Disabled
bar4_64bit_mem_space_hwtcl | Disabled
bar4_prefetchable_hwtcl | Disabled
bar5_type_hwtcl | 1
bar5_size_mask_hwtcl | 0
rd_dma_size_mask_hwtcl | 15
wr_dma_size_mask_hwtcl | 12
bar5_io_space_hwtcl | Disabled
bar5_prefetchable_hwtcl | Disabled
CB_P2A_AVALON_ADDR_B0 | 0x00000000
CB_P2A_AVALON_ADDR_B1 | 0x00000000
CB_P2A_AVALON_ADDR_B2 | 0x00000000
CB_P2A_AVALON_ADDR_B3 | 0x00000000
CB_P2A_AVALON_ADDR_B4 | 0x00000000
CB_P2A_AVALON_ADDR_B5 | 0x00000000
fixed_address_mode | 0
CB_P2A_FIXED_AVALON_ADDR_B0 | 0
CB_P2A_FIXED_AVALON_ADDR_B1 | 0
CB_P2A_FIXED_AVALON_ADDR_B2 | 0
CB_P2A_FIXED_AVALON_ADDR_B3 | 0
CB_P2A_FIXED_AVALON_ADDR_B4 | 0
CB_P2A_FIXED_AVALON_ADDR_B5 | 0
vendor_id_hwtcl | 4466
device_id_hwtcl | 57347
revision_id_hwtcl | 1
class_code_hwtcl | 0
subsystem_vendor_id_hwtcl | 0
subsystem_device_id_hwtcl | 257
max_payload_size_hwtcl | 256
extend_tag_field_hwtcl | 32
completion_timeout_hwtcl | NONE
enable_completion_timeout_disable_hwtcl | 1
use_aer_hwtcl | 1
ecrc_check_capable_hwtcl | 0
ecrc_gen_capable_hwtcl | 0
use_crc_forwarding_hwtcl | 0
port_link_number_hwtcl | 1
dll_active_report_support_hwtcl | 0
surprise_down_error_support_hwtcl | 0
slotclkcfg_hwtcl | 1
msi_multi_message_capable_hwtcl | 4
msi_64bit_addressing_capable_hwtcl | true
msi_masking_capable_hwtcl | false
msi_support_hwtcl | true
enable_function_msix_support_hwtcl | 0
msix_table_size_hwtcl | 0
msix_table_offset_hwtcl | 0
msix_table_bir_hwtcl | 0
msix_pba_offset_hwtcl | 0
msix_pba_bir_hwtcl | 0
enable_slot_register_hwtcl | 0
slot_power_scale_hwtcl | 0
slot_power_limit_hwtcl | 0
slot_number_hwtcl | 0
endpoint_l0_latency_hwtcl | 0
endpoint_l1_latency_hwtcl | 0
CG_COMMON_CLOCK_MODE | 1
avmm_width_hwtcl | 256
avmm_burst_width_hwtcl | 7
CG_RXM_IRQ_NUM | 16
TX_S_ADDR_WIDTH | 32
ast_width_hwtcl | Avalon-ST 128-bit
generate_sdc_for_qsys_design_example | 0
use_rx_st_be_hwtcl | 0
use_ast_parity | 0
pld_clk_MHz | 1250
millisecond_cycle_count_hwtcl | 124250
add_pll_to_hip_coreclkout | 0
set_pll_coreclkout_slack | 10
set_pll_coreclkout_cout_hwtcl | NA
set_pll_coreclkout_cin_hwtcl | NA
port_width_be_hwtcl | 16
port_width_data_hwtcl | 128
hip_reconfig_hwtcl | 0
vsec_id_hwtcl | 40960
vsec_rev_hwtcl | 0
expansion_base_address_register_hwtcl | 0
io_window_addr_width_hwtcl | 0
prefetchable_mem_window_addr_width_hwtcl | 0
advanced_default_parameter_override | 0
override_tbpartner_driver_setting_hwtcl | 0
override_rxbuffer_cred_preset | 0
bypass_cdc_hwtcl | false
enable_rx_buffer_checking_hwtcl | false
disable_link_x2_support_hwtcl | false
wrong_device_id_hwtcl | disable
data_pack_rx_hwtcl | disable
ltssm_1ms_timeout_hwtcl | disable
ltssm_freqlocked_check_hwtcl | disable
deskew_comma_hwtcl | skp_eieos_deskw
device_number_hwtcl | 0
pipex1_debug_sel_hwtcl | disable
pclk_out_sel_hwtcl | pclk
no_soft_reset_hwtcl | false
maximum_current_hwtcl | 0
d1_support_hwtcl | false
d2_support_hwtcl | false
d0_pme_hwtcl | false
d1_pme_hwtcl | false
d2_pme_hwtcl | false
d3_hot_pme_hwtcl | false
d3_cold_pme_hwtcl | false
low_priority_vc_hwtcl | single_vc
disable_snoop_packet_hwtcl | false
enable_l1_aspm_hwtcl | false
set_l0s_hwtcl | 0
rx_ei_l0s_hwtcl | 0
enable_l0s_aspm_hwtcl | false
aspm_config_management_hwtcl | true
l1_exit_latency_sameclock_hwtcl | 0
l1_exit_latency_diffclock_hwtcl | 0
hot_plug_support_hwtcl | 0
extended_tag_reset_hwtcl | false
no_command_completed_hwtcl | false
interrupt_pin_hwtcl | inta
bridge_port_vga_enable_hwtcl | false
bridge_port_ssid_support_hwtcl | false
ssvid_hwtcl | 0
ssid_hwtcl | 0
eie_before_nfts_count_hwtcl | 4
gen2_diffclock_nfts_count_hwtcl | 255
gen2_sameclock_nfts_count_hwtcl | 255
l0_exit_latency_sameclock_hwtcl | 6
l0_exit_latency_diffclock_hwtcl | 6
atomic_op_routing_hwtcl | false
atomic_op_completer_32bit_hwtcl | false
atomic_op_completer_64bit_hwtcl | false
cas_completer_128bit_hwtcl | false
ltr_mechanism_hwtcl | false
tph_completer_hwtcl | false
extended_format_field_hwtcl | false
atomic_malformed_hwtcl | true
flr_capability_hwtcl | false
enable_adapter_half_rate_mode_hwtcl | true
vc0_clk_enable_hwtcl | true
register_pipe_signals_hwtcl | true
skp_os_gen3_count_hwtcl | 0
tx_cdc_almost_empty_hwtcl | 5
rx_l0s_count_idl_hwtcl | 0
cdc_dummy_insert_limit_hwtcl | 11
ei_delay_powerdown_count_hwtcl | 10
skp_os_schedule_count_hwtcl | 0
fc_init_timer_hwtcl | 1024
l01_entry_latency_hwtcl | 31
flow_control_update_count_hwtcl | 30
flow_control_timeout_count_hwtcl | 200
retry_buffer_last_active_address_hwtcl | 2047
reserved_debug_hwtcl | 0
bypass_clk_switch_hwtcl | disable
l2_async_logic_hwtcl | disable
indicator_hwtcl | 0
diffclock_nfts_count_hwtcl | 128
sameclock_nfts_count_hwtcl | 128
rx_cdc_almost_full_hwtcl | 12
tx_cdc_almost_full_hwtcl | 11
credit_buffer_allocation_aux_hwtcl | absolute
vc0_rx_flow_ctrl_posted_header_hwtcl | 16
vc0_rx_flow_ctrl_posted_data_hwtcl | 16
vc0_rx_flow_ctrl_nonposted_header_hwtcl | 16
vc0_rx_flow_ctrl_nonposted_data_hwtcl | 0
vc0_rx_flow_ctrl_compl_header_hwtcl | 0
vc0_rx_flow_ctrl_compl_data_hwtcl | 0
cpl_spc_header_hwtcl | 195
cpl_spc_data_hwtcl | 781
gen3_rxfreqlock_counter_hwtcl | 0
gen3_skip_ph2_ph3_hwtcl | 0
g3_bypass_equlz_hwtcl | 0
cvp_data_compressed_hwtcl | false
cvp_data_encrypted_hwtcl | false
cvp_mode_reset_hwtcl | false
cvp_clk_reset_hwtcl | false
cseb_cpl_status_during_cvp_hwtcl | config_retry_status
core_clk_sel_hwtcl | pld_clk
cvp_rate_sel_hwtcl | full_rate
g3_dis_rx_use_prst_hwtcl | true
g3_dis_rx_use_prst_ep_hwtcl | true
deemphasis_enable_hwtcl | false
reconfig_to_xcvr_width | 350
reconfig_from_xcvr_width | 230
single_rx_detect_hwtcl | 4
hip_hard_reset_hwtcl | 0
force_hrc | 0
force_src | 0
serial_sim_hwtcl | 1
advanced_default_hwtcl_bypass_cdc | false
advanced_default_hwtcl_enable_rx_buffer_checking | false
advanced_default_hwtcl_disable_link_x2_support | false
advanced_default_hwtcl_wrong_device_id | disable
advanced_default_hwtcl_data_pack_rx | disable
advanced_default_hwtcl_ltssm_1ms_timeout | disable
advanced_default_hwtcl_ltssm_freqlocked_check | disable
advanced_default_hwtcl_deskew_comma | com_deskw
advanced_default_hwtcl_device_number | 0
advanced_default_hwtcl_pipex1_debug_sel | disable
advanced_default_hwtcl_pclk_out_sel | pclk
advanced_default_hwtcl_no_soft_reset | false
advanced_default_hwtcl_maximum_current | 0
advanced_default_hwtcl_d1_support | false
advanced_default_hwtcl_d2_support | false
advanced_default_hwtcl_d0_pme | false
advanced_default_hwtcl_d1_pme | false
advanced_default_hwtcl_d2_pme | false
advanced_default_hwtcl_d3_hot_pme | false
advanced_default_hwtcl_d3_cold_pme | false
advanced_default_hwtcl_low_priority_vc | single_vc
advanced_default_hwtcl_disable_snoop_packet | false
advanced_default_hwtcl_enable_l1_aspm | false
advanced_default_hwtcl_set_l0s | 0
advanced_default_hwtcl_l1_exit_latency_sameclock | 0
advanced_default_hwtcl_l1_exit_latency_diffclock | 0
advanced_default_hwtcl_hot_plug_support | 0
advanced_default_hwtcl_extended_tag_reset | false
advanced_default_hwtcl_no_command_completed | false
advanced_default_hwtcl_interrupt_pin | inta
advanced_default_hwtcl_bridge_port_vga_enable | false
advanced_default_hwtcl_bridge_port_ssid_support | false
advanced_default_hwtcl_ssvid | 0
advanced_default_hwtcl_ssid | 0
advanced_default_hwtcl_eie_before_nfts_count | 4
advanced_default_hwtcl_gen2_diffclock_nfts_count | 255
advanced_default_hwtcl_gen2_sameclock_nfts_count | 255
advanced_default_hwtcl_l0_exit_latency_sameclock | 6
advanced_default_hwtcl_l0_exit_latency_diffclock | 6
advanced_default_hwtcl_atomic_op_routing | false
advanced_default_hwtcl_atomic_op_completer_32bit | false
advanced_default_hwtcl_atomic_op_completer_64bit | false
advanced_default_hwtcl_cas_completer_128bit | false
advanced_default_hwtcl_ltr_mechanism | false
advanced_default_hwtcl_tph_completer | false
advanced_default_hwtcl_extended_format_field | false
advanced_default_hwtcl_atomic_malformed | true
advanced_default_hwtcl_flr_capability | false
advanced_default_hwtcl_enable_adapter_half_rate_mode | false
advanced_default_hwtcl_vc0_clk_enable | true
advanced_default_hwtcl_register_pipe_signals | false
advanced_default_hwtcl_skp_os_gen3_count | 0
advanced_default_hwtcl_tx_cdc_almost_empty | 5
advanced_default_hwtcl_rx_l0s_count_idl | 0
advanced_default_hwtcl_cdc_dummy_insert_limit | 11
advanced_default_hwtcl_ei_delay_powerdown_count | 10
advanced_default_hwtcl_skp_os_schedule_count | 0
advanced_default_hwtcl_fc_init_timer | 1024
advanced_default_hwtcl_l01_entry_latency | 31
advanced_default_hwtcl_flow_control_update_count | 30
advanced_default_hwtcl_flow_control_timeout_count | 200
advanced_default_hwtcl_retry_buffer_last_active_address | 2047
advanced_default_hwtcl_reserved_debug | 0
use_tl_cfg_sync_hwtcl | 1
altpcie_avmm_hwtcl | 1
enable_rx_buffer_checking_advanced_default_hwtcl | false
disable_link_x2_support_advanced_default_hwtcl | false
device_number_advanced_default_hwtcl | 0
pipex1_debug_sel_advanced_default_hwtcl | disable
pclk_out_sel_advanced_default_hwtcl | pclk
no_soft_reset_advanced_default_hwtcl | false
d1_support_advanced_default_hwtcl | false
d2_support_advanced_default_hwtcl | false
d0_pme_advanced_default_hwtcl | false
d1_pme_advanced_default_hwtcl | false
d2_pme_advanced_default_hwtcl | false
d3_hot_pme_advanced_default_hwtcl | false
d3_cold_pme_advanced_default_hwtcl | false
low_priority_vc_advanced_default_hwtcl | single_vc
enable_l1_aspm_advanced_default_hwtcl | false
l1_exit_latency_sameclock_advanced_default_hwtcl | 0
l1_exit_latency_diffclock_advanced_default_hwtcl | 0
hot_plug_support_advanced_default_hwtcl | 0
no_command_completed_advanced_default_hwtcl | false
eie_before_nfts_count_advanced_default_hwtcl | 4
gen2_diffclock_nfts_count_advanced_default_hwtcl | 255
gen2_sameclock_nfts_count_advanced_default_hwtcl | 255
deemphasis_enable_advanced_default_hwtcl | false
l0_exit_latency_sameclock_advanced_default_hwtcl | 6
l0_exit_latency_diffclock_advanced_default_hwtcl | 6
vc0_clk_enable_advanced_default_hwtcl | true
register_pipe_signals_advanced_default_hwtcl | true
tx_cdc_almost_empty_advanced_default_hwtcl | 5
rx_l0s_count_idl_advanced_default_hwtcl | 0
cdc_dummy_insert_limit_advanced_default_hwtcl | 11
ei_delay_powerdown_count_advanced_default_hwtcl | 10
skp_os_schedule_count_advanced_default_hwtcl | 0
fc_init_timer_advanced_default_hwtcl | 1024
l01_entry_latency_advanced_default_hwtcl | 31
flow_control_update_count_advanced_default_hwtcl | 30
flow_control_timeout_count_advanced_default_hwtcl | 200
retry_buffer_last_active_address_advanced_default_hwtcl | 255
reserved_debug_advanced_default_hwtcl | 0
use_tl_cfg_sync_advanced_default_hwtcl | 1
diffclock_nfts_count_advanced_default_hwtcl | 255
sameclock_nfts_count_advanced_default_hwtcl | 255
l2_async_logic_advanced_default_hwtcl | disable
rx_cdc_almost_full_advanced_default_hwtcl | 12
tx_cdc_almost_full_advanced_default_hwtcl | 11
indicator_advanced_default_hwtcl | 0
hwtcl_override_g2_txvod | 1
rpre_emph_a_val_hwtcl | 9
rpre_emph_b_val_hwtcl | 0
rpre_emph_c_val_hwtcl | 16
rpre_emph_d_val_hwtcl | 13
rpre_emph_e_val_hwtcl | 5
rvod_sel_a_val_hwtcl | 42
rvod_sel_b_val_hwtcl | 38
rvod_sel_c_val_hwtcl | 38
rvod_sel_d_val_hwtcl | 43
rvod_sel_e_val_hwtcl | 15
av_rpre_emph_a_val_hwtcl | 12
av_rpre_emph_b_val_hwtcl | 0
av_rpre_emph_c_val_hwtcl | 19
av_rpre_emph_d_val_hwtcl | 13
av_rpre_emph_e_val_hwtcl | 21
av_rvod_sel_a_val_hwtcl | 42
av_rvod_sel_b_val_hwtcl | 30
av_rvod_sel_c_val_hwtcl | 43
av_rvod_sel_d_val_hwtcl | 43
av_rvod_sel_e_val_hwtcl | 9
cv_rpre_emph_a_val_hwtcl | 11
cv_rpre_emph_b_val_hwtcl | 0
cv_rpre_emph_c_val_hwtcl | 22
cv_rpre_emph_d_val_hwtcl | 12
cv_rpre_emph_e_val_hwtcl | 21
cv_rvod_sel_a_val_hwtcl | 50
cv_rvod_sel_b_val_hwtcl | 34
cv_rvod_sel_c_val_hwtcl | 50
cv_rvod_sel_d_val_hwtcl | 50
cv_rvod_sel_e_val_hwtcl | 9
AUTO_REFCLK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## onchip_memory2_0

altera_avalon_onchip_memory2 v14.0

pcie_256_hip_avmm_0 | coreclkout | onchip_memory2_0
clk1
coreclkout
clk2
Rxm_BAR2
s1
dma_rd_master
s1
dma_wr_master
s2
nreset_status
reset1
nreset_status
reset2

## Parameters
allowInSystemMemoryContentEditor | false
blockType | AUTO
dataWidth | 128
dualPort | true
initMemContent | true
initializationFileName | onchip_mem.hex
instanceID | NONE
memorySize | 4096
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
simMemInitOnlyFilename | 0
singleClockOperation | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
useShallowMemBlocks | false
writable | true
ecc_enabled | false
resetrequest_enabled | true
autoInitializationFileName | top_onchip_memory2_0
deviceFamily | ARRIAV
deviceFeatures | ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width | 8
derived_set_data_width | 128
derived_gui_ram_block_type | Automatic
derived_is_hardcopy | false
derived_init_file_name | top_onchip_memory2_0.hex
generateLegacySim | false

## Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
CONTENTS_INFO | ""
DUAL_PORT | 1
GUI_RAM_BLOCK_TYPE | AUTO
INIT_CONTENTS_FILE | top_onchip_memory2_0
INIT_MEM_CONTENT | 1
INSTANCE_ID | NONE
NON_DEFAULT_INIT_FILE_ENABLED | 0
RAM_BLOCK_TYPE | AUTO
READ_DURING_WRITE_MODE | DONT_CARE
SINGLE_CLOCK_OP | 0
SIZE_MULTIPLE | 1
SIZE_VALUE | 4096
WRITABLE | 1

generation took 0.01 seconds | rendering took 0.09 seconds