<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2014.08.05.17:38:01"
 outputDirectory="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Arria V"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="5AGXFB3H4F35C5"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DUT_REFCLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DUT_REFCLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DUT_REFCLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <interface name="clk" kind="clock" start="0">
   <property name="clockRate" value="50000000" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="clk_clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="reset" kind="reset" start="0">
   <property name="associatedClock" value="" />
   <property name="synchronousEdges" value="NONE" />
   <port name="reset_reset_n" direction="input" role="reset_n" width="1" />
  </interface>
  <interface name="dut_refclk" kind="clock" start="0">
   <property name="clockRate" value="100000000" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="dut_refclk_clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="dut_npor" kind="conduit" start="0">
   <property name="allowMultipleExportRoles" value="false" />
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <port name="dut_npor_npor" direction="input" role="npor" width="1" />
   <port
       name="dut_npor_pin_perst"
       direction="input"
       role="pin_perst"
       width="1" />
  </interface>
  <interface name="dut_hip_serial" kind="conduit" start="0">
   <property name="allowMultipleExportRoles" value="false" />
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <port
       name="dut_hip_serial_rx_in0"
       direction="input"
       role="rx_in0"
       width="1" />
   <port
       name="dut_hip_serial_rx_in1"
       direction="input"
       role="rx_in1"
       width="1" />
   <port
       name="dut_hip_serial_rx_in2"
       direction="input"
       role="rx_in2"
       width="1" />
   <port
       name="dut_hip_serial_rx_in3"
       direction="input"
       role="rx_in3"
       width="1" />
   <port
       name="dut_hip_serial_tx_out0"
       direction="output"
       role="tx_out0"
       width="1" />
   <port
       name="dut_hip_serial_tx_out1"
       direction="output"
       role="tx_out1"
       width="1" />
   <port
       name="dut_hip_serial_tx_out2"
       direction="output"
       role="tx_out2"
       width="1" />
   <port
       name="dut_hip_serial_tx_out3"
       direction="output"
       role="tx_out3"
       width="1" />
  </interface>
  <interface name="dut_hip_ctrl" kind="conduit" start="0">
   <property name="allowMultipleExportRoles" value="false" />
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <port
       name="dut_hip_ctrl_test_in"
       direction="input"
       role="test_in"
       width="32" />
   <port
       name="dut_hip_ctrl_simu_mode_pipe"
       direction="input"
       role="simu_mode_pipe"
       width="1" />
  </interface>
 </perimeter>
 <entity
   path=""
   parameterizationKey="top:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=5AGXFB3H4F35C5,AUTO_DEVICE_FAMILY=Arria V,AUTO_DUT_REFCLK_CLOCK_DOMAIN=-1,AUTO_DUT_REFCLK_CLOCK_RATE=-1,AUTO_DUT_REFCLK_RESET_DOMAIN=-1,AUTO_GENERATION_ID=1407285445,AUTO_UNIQUE_ID=(altera_pcie_reconfig_driver:14.0:AUTO_PLD_CLK_CLOCK_RATE=125000000,AUTO_RECONFIG_XCVR_CLK_CLOCK_RATE=50000000,INTENDED_DEVICE_FAMILY=Arria V,enable_cal_busy_hwtcl=1,gen123_lane_rate_mode_hwtcl=Gen2 (5.0 Gbps),number_of_reconfig_interfaces=5)(alt_xcvr_reconfig:14.0:AUTO_MGMT_CLK_CLK_CLOCK_RATE=50000000,ber_en=0,device_family=Arria V,enable_adce=0,enable_analog=0,enable_ber=0,enable_dcd=1,enable_dcd_power_up=0,enable_dfe=0,enable_eyemon=0,enable_lc=0,enable_mif=0,enable_offset=1,enable_pll=0,gui_cal_status_port=false,gui_enable_pll=0,gui_split_sizes=,number_of_reconfig_interfaces=5)(clock_source:14.0:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_pcie_256_hip_avmm:14.0:AUTO_REFCLK_CLOCK_RATE=0,CB_P2A_AVALON_ADDR_B0=0x00000000,CB_P2A_AVALON_ADDR_B1=0x00000000,CB_P2A_AVALON_ADDR_B2=0x00000000,CB_P2A_AVALON_ADDR_B3=0x00000000,CB_P2A_AVALON_ADDR_B4=0x00000000,CB_P2A_AVALON_ADDR_B5=0x00000000,CB_P2A_FIXED_AVALON_ADDR_B0=0,CB_P2A_FIXED_AVALON_ADDR_B1=0,CB_P2A_FIXED_AVALON_ADDR_B2=0,CB_P2A_FIXED_AVALON_ADDR_B3=0,CB_P2A_FIXED_AVALON_ADDR_B4=0,CB_P2A_FIXED_AVALON_ADDR_B5=0,CG_COMMON_CLOCK_MODE=1,CG_RXM_IRQ_NUM=16,DMA_BE_WIDTH=16,DMA_BRST_CNT_W=6,DMA_WIDTH=128,INTENDED_DEVICE_FAMILY=Arria V,NUM_PREFETCH_MASTERS=1,RD_SLAVE_ADDRESS_MAP=15,SLAVE_ADDRESS_MAP_0=0,SLAVE_ADDRESS_MAP_1=0,SLAVE_ADDRESS_MAP_2=12,SLAVE_ADDRESS_MAP_3=0,SLAVE_ADDRESS_MAP_4=0,SLAVE_ADDRESS_MAP_5=0,TX_S_ADDR_WIDTH=32,WR_SLAVE_ADDRESS_MAP=12,add_pll_to_hip_coreclkout=0,advanced_default_hwtcl_atomic_malformed=true,advanced_default_hwtcl_atomic_op_completer_32bit=false,advanced_default_hwtcl_atomic_op_completer_64bit=false,advanced_default_hwtcl_atomic_op_routing=false,advanced_default_hwtcl_bridge_port_ssid_support=false,advanced_default_hwtcl_bridge_port_vga_enable=false,advanced_default_hwtcl_bypass_cdc=false,advanced_default_hwtcl_cas_completer_128bit=false,advanced_default_hwtcl_cdc_dummy_insert_limit=11,advanced_default_hwtcl_d0_pme=false,advanced_default_hwtcl_d1_pme=false,advanced_default_hwtcl_d1_support=false,advanced_default_hwtcl_d2_pme=false,advanced_default_hwtcl_d2_support=false,advanced_default_hwtcl_d3_cold_pme=false,advanced_default_hwtcl_d3_hot_pme=false,advanced_default_hwtcl_data_pack_rx=disable,advanced_default_hwtcl_deskew_comma=com_deskw,advanced_default_hwtcl_device_number=0,advanced_default_hwtcl_disable_link_x2_support=false,advanced_default_hwtcl_disable_snoop_packet=false,advanced_default_hwtcl_ei_delay_powerdown_count=10,advanced_default_hwtcl_eie_before_nfts_count=4,advanced_default_hwtcl_enable_adapter_half_rate_mode=false,advanced_default_hwtcl_enable_l1_aspm=false,advanced_default_hwtcl_enable_rx_buffer_checking=false,advanced_default_hwtcl_extended_format_field=false,advanced_default_hwtcl_extended_tag_reset=false,advanced_default_hwtcl_fc_init_timer=1024,advanced_default_hwtcl_flow_control_timeout_count=200,advanced_default_hwtcl_flow_control_update_count=30,advanced_default_hwtcl_flr_capability=false,advanced_default_hwtcl_gen2_diffclock_nfts_count=255,advanced_default_hwtcl_gen2_sameclock_nfts_count=255,advanced_default_hwtcl_hot_plug_support=0,advanced_default_hwtcl_interrupt_pin=inta,advanced_default_hwtcl_l01_entry_latency=31,advanced_default_hwtcl_l0_exit_latency_diffclock=6,advanced_default_hwtcl_l0_exit_latency_sameclock=6,advanced_default_hwtcl_l1_exit_latency_diffclock=0,advanced_default_hwtcl_l1_exit_latency_sameclock=0,advanced_default_hwtcl_low_priority_vc=single_vc,advanced_default_hwtcl_ltr_mechanism=false,advanced_default_hwtcl_ltssm_1ms_timeout=disable,advanced_default_hwtcl_ltssm_freqlocked_check=disable,advanced_default_hwtcl_maximum_current=0,advanced_default_hwtcl_no_command_completed=false,advanced_default_hwtcl_no_soft_reset=false,advanced_default_hwtcl_pclk_out_sel=pclk,advanced_default_hwtcl_pipex1_debug_sel=disable,advanced_default_hwtcl_register_pipe_signals=false,advanced_default_hwtcl_reserved_debug=0,advanced_default_hwtcl_retry_buffer_last_active_address=2047,advanced_default_hwtcl_rx_l0s_count_idl=0,advanced_default_hwtcl_set_l0s=0,advanced_default_hwtcl_skp_os_gen3_count=0,advanced_default_hwtcl_skp_os_schedule_count=0,advanced_default_hwtcl_ssid=0,advanced_default_hwtcl_ssvid=0,advanced_default_hwtcl_tph_completer=false,advanced_default_hwtcl_tx_cdc_almost_empty=5,advanced_default_hwtcl_vc0_clk_enable=true,advanced_default_hwtcl_wrong_device_id=disable,advanced_default_parameter_override=0,altpcie_avmm_hwtcl=1,app_interface_width_hwtcl=128,aspm_config_management_hwtcl=true,ast_width_hwtcl=Avalon-ST 128-bit,atomic_malformed_hwtcl=true,atomic_op_completer_32bit_hwtcl=false,atomic_op_completer_64bit_hwtcl=false,atomic_op_routing_hwtcl=false,av_rpre_emph_a_val_hwtcl=12,av_rpre_emph_b_val_hwtcl=0,av_rpre_emph_c_val_hwtcl=19,av_rpre_emph_d_val_hwtcl=13,av_rpre_emph_e_val_hwtcl=21,av_rvod_sel_a_val_hwtcl=42,av_rvod_sel_b_val_hwtcl=30,av_rvod_sel_c_val_hwtcl=43,av_rvod_sel_d_val_hwtcl=43,av_rvod_sel_e_val_hwtcl=9,avmm_burst_width_hwtcl=7,avmm_width_hwtcl=256,bar0_64bit_mem_space_hwtcl=Enabled,bar0_io_space_hwtcl=Disabled,bar0_prefetchable_hwtcl=Enabled,bar0_size_mask_hwtcl=9,bar0_type_hwtcl=64,bar1_io_space_hwtcl=Disabled,bar1_prefetchable_hwtcl=Disabled,bar1_size_mask_hwtcl=0,bar1_type_hwtcl=1,bar2_64bit_mem_space_hwtcl=Enabled,bar2_io_space_hwtcl=Disabled,bar2_prefetchable_hwtcl=Enabled,bar2_size_mask_hwtcl=12,bar2_type_hwtcl=64,bar3_io_space_hwtcl=Disabled,bar3_prefetchable_hwtcl=Disabled,bar3_size_mask_hwtcl=0,bar3_type_hwtcl=1,bar4_64bit_mem_space_hwtcl=Disabled,bar4_io_space_hwtcl=Disabled,bar4_prefetchable_hwtcl=Disabled,bar4_size_mask_hwtcl=0,bar4_type_hwtcl=1,bar5_io_space_hwtcl=Disabled,bar5_prefetchable_hwtcl=Disabled,bar5_size_mask_hwtcl=0,bar5_type_hwtcl=1,bridge_port_ssid_support_hwtcl=false,bridge_port_vga_enable_hwtcl=false,bypass_cdc_hwtcl=false,bypass_clk_switch_hwtcl=disable,cas_completer_128bit_hwtcl=false,cdc_dummy_insert_limit_advanced_default_hwtcl=11,cdc_dummy_insert_limit_hwtcl=11,class_code_hwtcl=0,completion_timeout_hwtcl=NONE,core_clk_sel_hwtcl=pld_clk,cpl_spc_data_hwtcl=781,cpl_spc_header_hwtcl=195,credit_buffer_allocation_aux_hwtcl=absolute,cseb_cpl_status_during_cvp_hwtcl=config_retry_status,cv_rpre_emph_a_val_hwtcl=11,cv_rpre_emph_b_val_hwtcl=0,cv_rpre_emph_c_val_hwtcl=22,cv_rpre_emph_d_val_hwtcl=12,cv_rpre_emph_e_val_hwtcl=21,cv_rvod_sel_a_val_hwtcl=50,cv_rvod_sel_b_val_hwtcl=34,cv_rvod_sel_c_val_hwtcl=50,cv_rvod_sel_d_val_hwtcl=50,cv_rvod_sel_e_val_hwtcl=9,cvp_clk_reset_hwtcl=false,cvp_data_compressed_hwtcl=false,cvp_data_encrypted_hwtcl=false,cvp_mode_reset_hwtcl=false,cvp_rate_sel_hwtcl=full_rate,d0_pme_advanced_default_hwtcl=false,d0_pme_hwtcl=false,d1_pme_advanced_default_hwtcl=false,d1_pme_hwtcl=false,d1_support_advanced_default_hwtcl=false,d1_support_hwtcl=false,d2_pme_advanced_default_hwtcl=false,d2_pme_hwtcl=false,d2_support_advanced_default_hwtcl=false,d2_support_hwtcl=false,d3_cold_pme_advanced_default_hwtcl=false,d3_cold_pme_hwtcl=false,d3_hot_pme_advanced_default_hwtcl=false,d3_hot_pme_hwtcl=false,data_pack_rx_hwtcl=disable,deemphasis_enable_advanced_default_hwtcl=false,deemphasis_enable_hwtcl=false,deskew_comma_hwtcl=skp_eieos_deskw,device_id_hwtcl=57347,device_number_advanced_default_hwtcl=0,device_number_hwtcl=0,diffclock_nfts_count_advanced_default_hwtcl=255,diffclock_nfts_count_hwtcl=128,disable_link_x2_support_advanced_default_hwtcl=false,disable_link_x2_support_hwtcl=false,disable_snoop_packet_hwtcl=false,dll_active_report_support_hwtcl=0,ecrc_check_capable_hwtcl=0,ecrc_gen_capable_hwtcl=0,ei_delay_powerdown_count_advanced_default_hwtcl=10,ei_delay_powerdown_count_hwtcl=10,eie_before_nfts_count_advanced_default_hwtcl=4,eie_before_nfts_count_hwtcl=4,enable_adapter_half_rate_mode_hwtcl=true,enable_completion_timeout_disable_hwtcl=1,enable_cra_hwtcl=0,enable_function_msix_support_hwtcl=0,enable_l0s_aspm_hwtcl=false,enable_l1_aspm_advanced_default_hwtcl=false,enable_l1_aspm_hwtcl=false,enable_pcisigtest_hwtcl=0,enable_power_on_rst_pulse_hwtcl=0,enable_rx_buffer_checking_advanced_default_hwtcl=false,enable_rx_buffer_checking_hwtcl=false,enable_rxm_burst_hwtcl=0,enable_slot_register_hwtcl=0,enable_tl_only_sim_hwtcl=0,endpoint_l0_latency_hwtcl=0,endpoint_l1_latency_hwtcl=0,expansion_base_address_register_hwtcl=0,extend_tag_field_hwtcl=32,extended_format_field_hwtcl=false,extended_tag_reset_hwtcl=false,fc_init_timer_advanced_default_hwtcl=1024,fc_init_timer_hwtcl=1024,fixed_address_mode=0,flow_control_timeout_count_advanced_default_hwtcl=200,flow_control_timeout_count_hwtcl=200,flow_control_update_count_advanced_default_hwtcl=30,flow_control_update_count_hwtcl=30,flr_capability_hwtcl=false,force_hrc=0,force_src=0,g3_bypass_equlz_hwtcl=0,g3_dis_rx_use_prst_ep_hwtcl=true,g3_dis_rx_use_prst_hwtcl=true,gen123_lane_rate_mode_hwtcl=Gen2 (5.0 Gbps),gen2_diffclock_nfts_count_advanced_default_hwtcl=255,gen2_diffclock_nfts_count_hwtcl=255,gen2_sameclock_nfts_count_advanced_default_hwtcl=255,gen2_sameclock_nfts_count_hwtcl=255,gen3_rxfreqlock_counter_hwtcl=0,gen3_skip_ph2_ph3_hwtcl=0,generate_sdc_for_qsys_design_example=0,hip_hard_reset_hwtcl=0,hip_reconfig_hwtcl=0,hip_tag_checking_hwtcl=1,hot_plug_support_advanced_default_hwtcl=0,hot_plug_support_hwtcl=0,hwtcl_override_g2_txvod=1,in_cvp_mode_hwtcl=0,indicator_advanced_default_hwtcl=0,indicator_hwtcl=0,internal_controller_hwtcl=1,interrupt_pin_hwtcl=inta,io_window_addr_width_hwtcl=0,l01_entry_latency_advanced_default_hwtcl=31,l01_entry_latency_hwtcl=31,l0_exit_latency_diffclock_advanced_default_hwtcl=6,l0_exit_latency_diffclock_hwtcl=6,l0_exit_latency_sameclock_advanced_default_hwtcl=6,l0_exit_latency_sameclock_hwtcl=6,l1_exit_latency_diffclock_advanced_default_hwtcl=0,l1_exit_latency_diffclock_hwtcl=0,l1_exit_latency_sameclock_advanced_default_hwtcl=0,l1_exit_latency_sameclock_hwtcl=0,l2_async_logic_advanced_default_hwtcl=disable,l2_async_logic_hwtcl=disable,lane_mask_hwtcl=x4,low_priority_vc_advanced_default_hwtcl=single_vc,low_priority_vc_hwtcl=single_vc,ltr_mechanism_hwtcl=false,ltssm_1ms_timeout_hwtcl=disable,ltssm_freqlocked_check_hwtcl=disable,max_payload_size_hwtcl=256,maximum_current_hwtcl=0,millisecond_cycle_count_hwtcl=124250,msi_64bit_addressing_capable_hwtcl=true,msi_masking_capable_hwtcl=false,msi_multi_message_capable_hwtcl=4,msi_support_hwtcl=true,msix_pba_bir_hwtcl=0,msix_pba_offset_hwtcl=0,msix_table_bir_hwtcl=0,msix_table_offset_hwtcl=0,msix_table_size_hwtcl=0,no_command_completed_advanced_default_hwtcl=false,no_command_completed_hwtcl=false,no_soft_reset_advanced_default_hwtcl=false,no_soft_reset_hwtcl=false,override_rxbuffer_cred_preset=0,override_tbpartner_driver_setting_hwtcl=0,pcie_qsys=1,pcie_spec_version_hwtcl=2.1,pclk_out_sel_advanced_default_hwtcl=pclk,pclk_out_sel_hwtcl=pclk,pipex1_debug_sel_advanced_default_hwtcl=disable,pipex1_debug_sel_hwtcl=disable,pld_clk_MHz=1250,pll_refclk_freq_hwtcl=100 MHz,port_link_number_hwtcl=1,port_type_hwtcl=Native endpoint,port_width_be_hwtcl=16,port_width_data_hwtcl=128,prefetchable_mem_window_addr_width_hwtcl=0,rd_dma_size_mask_hwtcl=15,reconfig_from_xcvr_width=230,reconfig_to_xcvr_width=350,register_pipe_signals_advanced_default_hwtcl=true,register_pipe_signals_hwtcl=true,reserved_debug_advanced_default_hwtcl=0,reserved_debug_hwtcl=0,retry_buffer_last_active_address_advanced_default_hwtcl=255,retry_buffer_last_active_address_hwtcl=2047,revision_id_hwtcl=1,rpre_emph_a_val_hwtcl=9,rpre_emph_b_val_hwtcl=0,rpre_emph_c_val_hwtcl=16,rpre_emph_d_val_hwtcl=13,rpre_emph_e_val_hwtcl=5,rvod_sel_a_val_hwtcl=42,rvod_sel_b_val_hwtcl=38,rvod_sel_c_val_hwtcl=38,rvod_sel_d_val_hwtcl=43,rvod_sel_e_val_hwtcl=15,rx_cdc_almost_full_advanced_default_hwtcl=12,rx_cdc_almost_full_hwtcl=12,rx_ei_l0s_hwtcl=0,rx_l0s_count_idl_advanced_default_hwtcl=0,rx_l0s_count_idl_hwtcl=0,rxbuffer_rxreq_hwtcl=Low,sameclock_nfts_count_advanced_default_hwtcl=255,sameclock_nfts_count_hwtcl=128,serial_sim_hwtcl=1,set_l0s_hwtcl=0,set_pld_clk_x1_625MHz_hwtcl=0,set_pll_coreclkout_cin_hwtcl=NA,set_pll_coreclkout_cout_hwtcl=NA,set_pll_coreclkout_slack=10,single_rx_detect_hwtcl=4,skp_os_gen3_count_hwtcl=0,skp_os_schedule_count_advanced_default_hwtcl=0,skp_os_schedule_count_hwtcl=0,slot_number_hwtcl=0,slot_power_limit_hwtcl=0,slot_power_scale_hwtcl=0,slotclkcfg_hwtcl=1,ssid_hwtcl=0,ssvid_hwtcl=0,subsystem_device_id_hwtcl=257,subsystem_vendor_id_hwtcl=0,surprise_down_error_support_hwtcl=0,tph_completer_hwtcl=false,tx_cdc_almost_empty_advanced_default_hwtcl=5,tx_cdc_almost_empty_hwtcl=5,tx_cdc_almost_full_advanced_default_hwtcl=11,tx_cdc_almost_full_hwtcl=11,use_aer_hwtcl=1,use_ast_parity=0,use_atx_pll_hwtcl=0,use_crc_forwarding_hwtcl=0,use_rx_st_be_hwtcl=0,use_tl_cfg_sync_advanced_default_hwtcl=1,use_tl_cfg_sync_hwtcl=1,vc0_clk_enable_advanced_default_hwtcl=true,vc0_clk_enable_hwtcl=true,vc0_rx_flow_ctrl_compl_data_hwtcl=0,vc0_rx_flow_ctrl_compl_header_hwtcl=0,vc0_rx_flow_ctrl_nonposted_data_hwtcl=0,vc0_rx_flow_ctrl_nonposted_header_hwtcl=16,vc0_rx_flow_ctrl_posted_data_hwtcl=16,vc0_rx_flow_ctrl_posted_header_hwtcl=16,vendor_id_hwtcl=4466,vsec_id_hwtcl=40960,vsec_rev_hwtcl=0,wr_dma_size_mask_hwtcl=12,wrong_device_id_hwtcl=disable)(altera_avalon_onchip_memory2:14.0:allowInSystemMemoryContentEditor=false,autoInitializationFileName=top_onchip_memory2_0,blockType=AUTO,dataWidth=128,derived_gui_ram_block_type=Automatic,derived_init_file_name=top_onchip_memory2_0.hex,derived_is_hardcopy=false,derived_set_addr_width=8,derived_set_data_width=128,deviceFamily=Arria V,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,initMemContent=true,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=4096,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)(clock:14.0:)(clock:14.0:)(reset:14.0:)(reset:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(conduit:14.0:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:14.0:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:14.0:)(clock:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:14.0:arbitrationPriority=1,baseAddress=0x4000,defaultConnection=false)(avalon:14.0:arbitrationPriority=1,baseAddress=0x2000,defaultConnection=false)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(conduit:14.0:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:14.0:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(reset:14.0:)(reset:14.0:)(conduit:14.0:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:14.0:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:14.0:)"
   instancePathKey="top"
   kind="top"
   version="1.0"
   name="top">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
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  <parameter name="AUTO_DUT_REFCLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_DUT_REFCLK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_DEVICE" value="5AGXFB3H4F35C5" />
  <parameter name="AUTO_GENERATION_ID" value="1407285445" />
  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_DUT_REFCLK_CLOCK_RATE" value="-1" />
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   <message level="Debug" culprit="merlin_burst_transform"><![CDATA[After transform: <b>26</b> modules, <b>97</b> connections]]></message>
   <message level="Debug">Transform: TreeTransform</message>
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   <message level="Debug" culprit="merlin_network_to_switch_transform"><![CDATA[After transform: <b>35</b> modules, <b>115</b> connections]]></message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_width_transform"><![CDATA[After transform: <b>41</b> modules, <b>133</b> connections]]></message>
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   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
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   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_clock_and_reset_bridge_transform"><![CDATA[After transform: <b>43</b> modules, <b>175</b> connections]]></message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>6</b> modules, <b>26</b> connections]]></message>
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   <message level="Info">Interconnect is inserted between master pcie_256_hip_avmm_0.dma_wr_master and slave onchip_memory2_0.s2 because the master has address signal 64 bit wide, but the slave is 8 bit wide.</message>
   <message level="Info">Interconnect is inserted between master pcie_256_hip_avmm_0.dma_wr_master and slave onchip_memory2_0.s2 because the master has read signal 1 bit wide, but the slave is 0 bit wide.</message>
   <message level="Info">Interconnect is inserted between master pcie_256_hip_avmm_0.dma_wr_master and slave onchip_memory2_0.s2 because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.</message>
   <message level="Info">Interconnect is inserted between master pcie_256_hip_avmm_0.dma_wr_master and slave onchip_memory2_0.s2 because the master has burstcount signal 6 bit wide, but the slave is 0 bit wide.</message>
   <message level="Info">Interconnect is inserted between master pcie_256_hip_avmm_0.dma_wr_master and slave onchip_memory2_0.s2 because the master has readdatavalid signal 1 bit wide, but the slave is 0 bit wide.</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>2</b> modules, <b>3</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_translator_transform"><![CDATA[After transform: <b>4</b> modules, <b>9</b> connections]]></message>
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   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces pcie_256_hip_avmm_0.dma_wr_master and pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_anti_master_0</message>
   <message level="Progress" culprit="min"></message>
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   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces onchip_memory2_0_s2_translator.avalon_anti_slave_0 and onchip_memory2_0.s2</message>
   <message level="Debug" culprit="merlin_domain_transform"><![CDATA[After transform: <b>8</b> modules, <b>27</b> connections]]></message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_router_transform"><![CDATA[After transform: <b>10</b> modules, <b>33</b> connections]]></message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_burst_transform"><![CDATA[After transform: <b>11</b> modules, <b>36</b> connections]]></message>
   <message level="Debug">Transform: TreeTransform</message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_network_to_switch_transform"><![CDATA[After transform: <b>14</b> modules, <b>42</b> connections]]></message>
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   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
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   <message level="Debug" culprit="merlin_clock_and_reset_bridge_transform"><![CDATA[After transform: <b>16</b> modules, <b>57</b> connections]]></message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>7</b> modules, <b>29</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>1</b> modules, <b>2</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_translator_transform"><![CDATA[After transform: <b>4</b> modules, <b>11</b> connections]]></message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces pcie_256_hip_avmm_0.wr_dcm_master and pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_anti_master_0</message>
   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces pcie_256_hip_avmm_0.rd_dcm_master and pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_anti_master_0</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
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   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
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   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces pcie_256_hip_avmm_0_Txs_translator.avalon_anti_slave_0 and pcie_256_hip_avmm_0.Txs</message>
   <message level="Debug" culprit="merlin_domain_transform"><![CDATA[After transform: <b>9</b> modules, <b>35</b> connections]]></message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_router_transform"><![CDATA[After transform: <b>12</b> modules, <b>44</b> connections]]></message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Progress" culprit="min"></message>
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   <message level="Progress" culprit="min"></message>
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   <message level="Debug" culprit="merlin_network_to_switch_transform"><![CDATA[After transform: <b>17</b> modules, <b>54</b> connections]]></message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
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   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="merlin_clock_and_reset_bridge_transform"><![CDATA[After transform: <b>19</b> modules, <b>72</b> connections]]></message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>8</b> modules, <b>32</b> connections]]></message>
   <message level="Debug" culprit="merlin_mm_transform"><![CDATA[After transform: <b>8</b> modules, <b>32</b> connections]]></message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
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   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
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   <message level="Debug" culprit="reset_adaptation_transform"><![CDATA[After transform: <b>11</b> modules, <b>40</b> connections]]></message>
   <message level="Debug" culprit="top"><![CDATA["<b>top</b>" reuses <b>altera_pcie_reconfig_driver</b> "<b>submodules/altpcie_reconfig_driver</b>"]]></message>
   <message level="Debug" culprit="top"><![CDATA["<b>top</b>" reuses <b>alt_xcvr_reconfig</b> "<b>submodules/alt_xcvr_reconfig</b>"]]></message>
   <message level="Debug" culprit="top"><![CDATA["<b>top</b>" reuses <b>altera_pcie_256_hip_avmm</b> "<b>submodules/altpcie_256_hip_avmm_hwtcl</b>"]]></message>
   <message level="Debug" culprit="top"><![CDATA["<b>top</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/top_onchip_memory2_0</b>"]]></message>
   <message level="Debug" culprit="top"><![CDATA["<b>top</b>" reuses <b>altera_mm_interconnect</b> "<b>submodules/top_mm_interconnect_1</b>"]]></message>
   <message level="Debug" culprit="top"><![CDATA["<b>top</b>" reuses <b>altera_mm_interconnect</b> "<b>submodules/top_mm_interconnect_2</b>"]]></message>
   <message level="Debug" culprit="top"><![CDATA["<b>top</b>" reuses <b>altera_mm_interconnect</b> "<b>submodules/top_mm_interconnect_3</b>"]]></message>
   <message level="Debug" culprit="top"><![CDATA["<b>top</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
   <message level="Debug" culprit="top"><![CDATA["<b>top</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 8 starting:altera_pcie_reconfig_driver "submodules/altpcie_reconfig_driver"</message>
   <message level="Info" culprit="pcie_reconfig_driver_0"><![CDATA["<b>top</b>" instantiated <b>altera_pcie_reconfig_driver</b> "<b>pcie_reconfig_driver_0</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 7 starting:alt_xcvr_reconfig "submodules/alt_xcvr_reconfig"</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_h.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_h.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cal_seq.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_cal_seq.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_cif.sv SYSTEM_VERILOG PATH .//alt_xreconf_cif.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_uif.sv SYSTEM_VERILOG PATH .//alt_xreconf_uif.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_basic_acq.sv SYSTEM_VERILOG PATH .//alt_xreconf_basic_acq.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_analog.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_analog_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_analog_datactrl_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_datactrl_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_analog_rmw_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_rmw_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_analog_ctrlsm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_ctrlsm.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_offset_cancellation.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_offset_cancellation_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_eyemon.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_eyemon/alt_xcvr_reconfig_eyemon.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_dfe.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dfe/alt_xcvr_reconfig_dfe.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_adce.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_adce/alt_xcvr_reconfig_adce.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_dcd.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_dcd_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_dcd_cal_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_cal_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_dcd_control_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_control_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/alt_xcvr_reconfig_mif.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_mif_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_ctrl.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_mif_avmm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_avmm.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/alt_xcvr_reconfig_pll.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_pll_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll_ctrl.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_soc.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_soc/alt_xcvr_reconfig_soc.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_ram.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_soc/alt_xcvr_reconfig_cpu_ram.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_ram.hex OTHER PATH ../alt_xcvr_reconfig_soc/software/alt_xcvr_reconfig_av/mem_init/alt_xcvr_reconfig_cpu_ram.hex</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_direct.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_direct/alt_xcvr_reconfig_direct.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_arbiter_acq.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_arbiter_acq.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_xcvr_reconfig_basic.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xrbasic_l2p_addr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_addr.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xrbasic_l2p_ch.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_ch.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xrbasic_l2p_rom.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_rom.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xrbasic_lif_csr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif_csr.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xrbasic_lif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xcvr_reconfig_basic.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig.sdc OTHER PATH .//av_xcvr_reconfig.sdc</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_m2s.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_m2s.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./sv_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_basic.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/alt_xcvr_reconfig_cpu.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif OTHER PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif OTHER PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_irq_mapper.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_irq_mapper.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_reset_controller.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_reset_controller.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_reset_synchronizer.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_reset_synchronizer.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_reset_controller.sdc OTHER PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_reset_controller.sdc</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_master_translator.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_master_translator.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_slave_translator.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_slave_translator.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_master_agent.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_master_agent.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_slave_agent.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_slave_agent.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_burst_uncompressor.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_burst_uncompressor.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_avalon_sc_fifo.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_avalon_sc_fifo.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux_001.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_arbitrator.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_arbitrator.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux_001.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux_001.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0"><![CDATA["<b>top</b>" instantiated <b>alt_xcvr_reconfig</b> "<b>alt_xcvr_reconfig_0</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_h.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 6 starting:altera_pcie_256_hip_avmm "submodules/altpcie_256_hip_avmm_hwtcl"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./sv_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_xcvr.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./sv_reconfig_bundle_to_ip.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_ip.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./sv_reconfig_bundle_merger.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_merger.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_reset_ctrl_lego.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_reset_ctrl_lego.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_reset_ctrl_tgx_cdrauto.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_reset_ctrl_tgx_cdrauto.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_csr_common_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_common_h.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_csr_common.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_common.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_csr_pcs8g_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_pcs8g_h.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_csr_pcs8g.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_pcs8g.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_mgmt2dec.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_mgmt2dec.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_avmm_csr.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_tx_pma_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_tx_pma_ch.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_tx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_tx_pma.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_rx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_rx_pma.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pma.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_pcs_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pcs_ch.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_pcs.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pcs.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_avmm.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_native.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_native.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_plls.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_plls.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_data_adapter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_data_adapter.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_8g_rx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_8g_rx_pcs_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_8g_tx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_8g_tx_pcs_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_common_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_common_pcs_pma_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_common_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_common_pld_pcs_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_pipe_gen1_2_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_pipe_gen1_2_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_rx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_rx_pcs_pma_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_rx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_rx_pld_pcs_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_tx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_tx_pcs_pma_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_tx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_tx_pld_pcs_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_pipe_native.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_pipe_native.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_emsip_adapter.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_emsip_adapter.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_pipe_native_hip.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_pipe_native_hip.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0"><![CDATA["<b>top</b>" instantiated <b>altera_pcie_256_hip_avmm</b> "<b>pcie_256_hip_avmm_0</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_xcvr_functions.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_resync.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_csr_selector.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_wait_generate.v</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/av_xcvr_h.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/av_reconfig_bundle_to_basic.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/av_reconfig_bundle_to_xcvr.sv</b>]]></message>
   <message level="Warning"><![CDATA[Overwriting different file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/plain_files.txt</b>]]></message>
   <message level="Debug" culprit="top">queue size: 5 starting:altera_avalon_onchip_memory2 "submodules/top_onchip_memory2_0"</message>
   <message level="Info" culprit="onchip_memory2_0">Starting RTL generation for module 'top_onchip_memory2_0'</message>
   <message level="Info" culprit="onchip_memory2_0">  Generation command is [exec /tools_archive/acds/14.0/200/linux64/quartus/linux64/perl/bin/perl -I /tools_archive/acds/14.0/200/linux64/quartus/linux64/perl/lib -I /tools_archive/acds/14.0/200/linux64/quartus/sopc_builder/bin/europa -I /tools_archive/acds/14.0/200/linux64/quartus/sopc_builder/bin/perl_lib -I /tools_archive/acds/14.0/200/linux64/quartus/sopc_builder/bin -I /tools_archive/acds/14.0/200/linux64/quartus/../ip/altera/sopc_builder_ip/common -I /tools_archive/acds/14.0/200/linux64/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /tools_archive/acds/14.0/200/linux64/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=top_onchip_memory2_0 --dir=/build/arc/temp/217396113/alt6288_3873220473054358287.dir/0004_onchip_memory2_0_gen/ --quartus_dir=/tools_archive/acds/14.0/200/linux64/quartus --verilog --config=/build/arc/temp/217396113/alt6288_3873220473054358287.dir/0004_onchip_memory2_0_gen//top_onchip_memory2_0_component_configuration.pl  --do_build_sim=0  ]</message>
   <message level="Info" culprit="onchip_memory2_0">Done RTL generation for module 'top_onchip_memory2_0'</message>
   <message level="Info" culprit="onchip_memory2_0"><![CDATA["<b>top</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>onchip_memory2_0</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 4 starting:altera_mm_interconnect "submodules/top_mm_interconnect_1"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_1_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_1_router_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_1_router_002</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_1_router_003</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_1_router_003</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_1_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_1_cmd_demux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_1_cmd_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_1_cmd_mux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_1_cmd_mux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_1_rsp_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_1_rsp_demux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_1_rsp_demux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_1_rsp_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_1_rsp_mux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Info" culprit="mm_interconnect_1"><![CDATA["<b>top</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 66 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_translator</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 64 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>onchip_memory2_0_s1_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 61 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 59 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>onchip_memory2_0_s1_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 58 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>onchip_memory2_0_s1_agent_rsp_fifo</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
   <message level="Debug" culprit="top">queue size: 51 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 50 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router_001"</message>
   <message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 49 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router_002"</message>
   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 48 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router_003"</message>
   <message level="Info" culprit="router_003"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_003</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 46 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>onchip_memory2_0_s1_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 43 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 42 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_cmd_demux_001"</message>
   <message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 41 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 40 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_cmd_mux_001"</message>
   <message level="Info" culprit="cmd_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_001</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 38 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_rsp_demux"</message>
   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 37 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_rsp_demux_001"</message>
   <message level="Info" culprit="rsp_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_001</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 35 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 34 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_rsp_mux_001"</message>
   <message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 33 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
   <message
       level="Info"
       culprit="pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 42 starting:altera_mm_interconnect "submodules/top_mm_interconnect_2"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>14</b> modules, <b>39</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>14</b> modules, <b>39</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>14</b> modules, <b>39</b> connections]]></message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_2_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_2_router_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_2_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_2_cmd_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_2_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_2_rsp_mux</b>"]]></message>
   <message level="Info" culprit="mm_interconnect_2"><![CDATA["<b>top</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_2</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 66 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_translator</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 64 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>onchip_memory2_0_s1_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 61 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 59 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>onchip_memory2_0_s1_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 58 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>onchip_memory2_0_s1_agent_rsp_fifo</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
   <message level="Debug" culprit="top">queue size: 22 starting:altera_merlin_router "submodules/top_mm_interconnect_2_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 21 starting:altera_merlin_router "submodules/top_mm_interconnect_2_router_001"</message>
   <message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 46 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>onchip_memory2_0_s1_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 19 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_2_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 18 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_2_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 16 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_2_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 53 starting:altera_mm_interconnect "submodules/top_mm_interconnect_3"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>18</b> modules, <b>52</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>18</b> modules, <b>52</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>18</b> modules, <b>52</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>18</b> modules, <b>52</b> connections]]></message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_3_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_3_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_3_router_002</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_3_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_3_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_3_cmd_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_3_rsp_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_3_rsp_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_3_rsp_mux</b>"]]></message>
   <message level="Info" culprit="mm_interconnect_3"><![CDATA["<b>top</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_3</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 66 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_translator</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 64 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>onchip_memory2_0_s1_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 61 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 59 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>onchip_memory2_0_s1_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 58 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>onchip_memory2_0_s1_agent_rsp_fifo</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
   <message level="Debug" culprit="top">queue size: 8 starting:altera_merlin_router "submodules/top_mm_interconnect_3_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 6 starting:altera_merlin_router "submodules/top_mm_interconnect_3_router_002"</message>
   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 5 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_3_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 3 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_3_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 2 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_3_rsp_demux"</message>
   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 1 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_3_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 68 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
   <message level="Info" culprit="rst_controller"><![CDATA["<b>top</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_controller.v</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_synchronizer.v</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_controller.sdc</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_pcie_reconfig_driver:14.0:AUTO_PLD_CLK_CLOCK_RATE=125000000,AUTO_RECONFIG_XCVR_CLK_CLOCK_RATE=50000000,INTENDED_DEVICE_FAMILY=Arria V,enable_cal_busy_hwtcl=1,gen123_lane_rate_mode_hwtcl=Gen2 (5.0 Gbps),number_of_reconfig_interfaces=5"
   instancePathKey="top:.:pcie_reconfig_driver_0"
   kind="altera_pcie_reconfig_driver"
   version="14.0"
   name="altpcie_reconfig_driver">
  <parameter name="AUTO_RECONFIG_XCVR_CLK_CLOCK_RATE" value="50000000" />
  <parameter name="INTENDED_DEVICE_FAMILY" value="Arria V" />
  <parameter name="number_of_reconfig_interfaces" value="5" />
  <parameter name="enable_cal_busy_hwtcl" value="1" />
  <parameter name="gen123_lane_rate_mode_hwtcl" value="Gen2 (5.0 Gbps)" />
  <parameter name="AUTO_PLD_CLK_CLOCK_RATE" value="125000000" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_h.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altpcie_reconfig_driver.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_reconfig_driver_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top" as="pcie_reconfig_driver_0" />
  <messages>
   <message level="Debug" culprit="top">queue size: 8 starting:altera_pcie_reconfig_driver "submodules/altpcie_reconfig_driver"</message>
   <message level="Info" culprit="pcie_reconfig_driver_0"><![CDATA["<b>top</b>" instantiated <b>altera_pcie_reconfig_driver</b> "<b>pcie_reconfig_driver_0</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="alt_xcvr_reconfig:14.0:AUTO_MGMT_CLK_CLK_CLOCK_RATE=50000000,ber_en=0,device_family=Arria V,enable_adce=0,enable_analog=0,enable_ber=0,enable_dcd=1,enable_dcd_power_up=0,enable_dfe=0,enable_eyemon=0,enable_lc=0,enable_mif=0,enable_offset=1,enable_pll=0,gui_cal_status_port=false,gui_enable_pll=0,gui_split_sizes=,number_of_reconfig_interfaces=5"
   instancePathKey="top:.:alt_xcvr_reconfig_0"
   kind="alt_xcvr_reconfig"
   version="14.0"
   name="alt_xcvr_reconfig">
  <parameter name="enable_eyemon" value="0" />
  <parameter name="device_family" value="Arria V" />
  <parameter name="enable_ber" value="0" />
  <parameter name="number_of_reconfig_interfaces" value="5" />
  <parameter name="enable_analog" value="0" />
  <parameter name="enable_dcd" value="1" />
  <parameter name="gui_cal_status_port" value="false" />
  <parameter name="enable_offset" value="1" />
  <parameter name="enable_dfe" value="0" />
  <parameter name="AUTO_MGMT_CLK_CLK_CLOCK_RATE" value="50000000" />
  <parameter name="enable_pll" value="0" />
  <parameter name="enable_dcd_power_up" value="0" />
  <parameter name="ber_en" value="0" />
  <parameter name="gui_enable_pll" value="0" />
  <parameter name="enable_lc" value="0" />
  <parameter name="enable_adce" value="0" />
  <parameter name="gui_split_sizes" value="" />
  <parameter name="enable_mif" value="0" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_xcvr_functions.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/av_xcvr_h.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_resync.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_h.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cal_seq.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xreconf_cif.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xreconf_uif.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xreconf_basic_acq.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_analog.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_analog_av.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xreconf_analog_datactrl_av.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xreconf_analog_rmw_av.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xreconf_analog_ctrlsm.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_offset_cancellation.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_offset_cancellation_av.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_eyemon.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_dfe.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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   <message level="Debug" culprit="top">queue size: 7 starting:alt_xcvr_reconfig "submodules/alt_xcvr_reconfig"</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_h.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_h.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cal_seq.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_cal_seq.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_cif.sv SYSTEM_VERILOG PATH .//alt_xreconf_cif.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_uif.sv SYSTEM_VERILOG PATH .//alt_xreconf_uif.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_basic_acq.sv SYSTEM_VERILOG PATH .//alt_xreconf_basic_acq.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_analog.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_analog_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_analog_datactrl_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_datactrl_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_analog_rmw_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_rmw_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xreconf_analog_ctrlsm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_ctrlsm.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_offset_cancellation.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_offset_cancellation_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_eyemon.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_eyemon/alt_xcvr_reconfig_eyemon.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_dfe.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dfe/alt_xcvr_reconfig_dfe.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_adce.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_adce/alt_xcvr_reconfig_adce.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_dcd.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_dcd_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_dcd_cal_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_cal_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_dcd_control_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_control_av.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/alt_xcvr_reconfig_mif.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_mif_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_ctrl.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_mif_avmm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_avmm.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/alt_xcvr_reconfig_pll.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_pll_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll_ctrl.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_soc.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_soc/alt_xcvr_reconfig_soc.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_ram.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_soc/alt_xcvr_reconfig_cpu_ram.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_ram.hex OTHER PATH ../alt_xcvr_reconfig_soc/software/alt_xcvr_reconfig_av/mem_init/alt_xcvr_reconfig_cpu_ram.hex</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_direct.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_direct/alt_xcvr_reconfig_direct.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_arbiter_acq.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_arbiter_acq.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_xcvr_reconfig_basic.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xrbasic_l2p_addr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_addr.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xrbasic_l2p_ch.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_ch.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xrbasic_l2p_rom.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_rom.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xrbasic_lif_csr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif_csr.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xrbasic_lif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xcvr_reconfig_basic.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_xcvr_reconfig.sdc OTHER PATH .//av_xcvr_reconfig.sdc</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_m2s.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_m2s.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./sv_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_basic.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/alt_xcvr_reconfig_cpu.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif OTHER PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif OTHER PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_irq_mapper.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_irq_mapper.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_reset_controller.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_reset_controller.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_reset_synchronizer.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_reset_synchronizer.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_reset_controller.sdc OTHER PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_reset_controller.sdc</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_master_translator.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_master_translator.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_slave_translator.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_slave_translator.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_master_agent.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_master_agent.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_slave_agent.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_slave_agent.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_burst_uncompressor.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_burst_uncompressor.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_avalon_sc_fifo.v VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_avalon_sc_fifo.v</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux_001.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./altera_merlin_arbitrator.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_arbitrator.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux_001.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0">add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217396113/alt6288_3873220473054358287.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux_001.sv</message>
   <message level="Info" culprit="alt_xcvr_reconfig_0"><![CDATA["<b>top</b>" instantiated <b>alt_xcvr_reconfig</b> "<b>alt_xcvr_reconfig_0</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_h.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_pcie_256_hip_avmm:14.0:AUTO_REFCLK_CLOCK_RATE=0,CB_P2A_AVALON_ADDR_B0=0x00000000,CB_P2A_AVALON_ADDR_B1=0x00000000,CB_P2A_AVALON_ADDR_B2=0x00000000,CB_P2A_AVALON_ADDR_B3=0x00000000,CB_P2A_AVALON_ADDR_B4=0x00000000,CB_P2A_AVALON_ADDR_B5=0x00000000,CB_P2A_FIXED_AVALON_ADDR_B0=0,CB_P2A_FIXED_AVALON_ADDR_B1=0,CB_P2A_FIXED_AVALON_ADDR_B2=0,CB_P2A_FIXED_AVALON_ADDR_B3=0,CB_P2A_FIXED_AVALON_ADDR_B4=0,CB_P2A_FIXED_AVALON_ADDR_B5=0,CG_COMMON_CLOCK_MODE=1,CG_RXM_IRQ_NUM=16,DMA_BE_WIDTH=16,DMA_BRST_CNT_W=6,DMA_WIDTH=128,INTENDED_DEVICE_FAMILY=Arria V,NUM_PREFETCH_MASTERS=1,RD_SLAVE_ADDRESS_MAP=15,SLAVE_ADDRESS_MAP_0=0,SLAVE_ADDRESS_MAP_1=0,SLAVE_ADDRESS_MAP_2=12,SLAVE_ADDRESS_MAP_3=0,SLAVE_ADDRESS_MAP_4=0,SLAVE_ADDRESS_MAP_5=0,TX_S_ADDR_WIDTH=32,WR_SLAVE_ADDRESS_MAP=12,add_pll_to_hip_coreclkout=0,advanced_default_hwtcl_atomic_malformed=true,advanced_default_hwtcl_atomic_op_completer_32bit=false,advanced_default_hwtcl_atomic_op_completer_64bit=false,advanced_default_hwtcl_atomic_op_routing=false,advanced_default_hwtcl_bridge_port_ssid_support=false,advanced_default_hwtcl_bridge_port_vga_enable=false,advanced_default_hwtcl_bypass_cdc=false,advanced_default_hwtcl_cas_completer_128bit=false,advanced_default_hwtcl_cdc_dummy_insert_limit=11,advanced_default_hwtcl_d0_pme=false,advanced_default_hwtcl_d1_pme=false,advanced_default_hwtcl_d1_support=false,advanced_default_hwtcl_d2_pme=false,advanced_default_hwtcl_d2_support=false,advanced_default_hwtcl_d3_cold_pme=false,advanced_default_hwtcl_d3_hot_pme=false,advanced_default_hwtcl_data_pack_rx=disable,advanced_default_hwtcl_deskew_comma=com_deskw,advanced_default_hwtcl_device_number=0,advanced_default_hwtcl_disable_link_x2_support=false,advanced_default_hwtcl_disable_snoop_packet=false,advanced_default_hwtcl_ei_delay_powerdown_count=10,advanced_default_hwtcl_eie_before_nfts_count=4,advanced_default_hwtcl_enable_adapter_half_rate_mode=false,advanced_default_hwtcl_enable_l1_aspm=false,advanced_default_hwtcl_enable_rx_buffer_checking=false,advanced_default_hwtcl_extended_format_field=false,advanced_default_hwtcl_extended_tag_reset=false,advanced_default_hwtcl_fc_init_timer=1024,advanced_default_hwtcl_flow_control_timeout_count=200,advanced_default_hwtcl_flow_control_update_count=30,advanced_default_hwtcl_flr_capability=false,advanced_default_hwtcl_gen2_diffclock_nfts_count=255,advanced_default_hwtcl_gen2_sameclock_nfts_count=255,advanced_default_hwtcl_hot_plug_support=0,advanced_default_hwtcl_interrupt_pin=inta,advanced_default_hwtcl_l01_entry_latency=31,advanced_default_hwtcl_l0_exit_latency_diffclock=6,advanced_default_hwtcl_l0_exit_latency_sameclock=6,advanced_default_hwtcl_l1_exit_latency_diffclock=0,advanced_default_hwtcl_l1_exit_latency_sameclock=0,advanced_default_hwtcl_low_priority_vc=single_vc,advanced_default_hwtcl_ltr_mechanism=false,advanced_default_hwtcl_ltssm_1ms_timeout=disable,advanced_default_hwtcl_ltssm_freqlocked_check=disable,advanced_default_hwtcl_maximum_current=0,advanced_default_hwtcl_no_command_completed=false,advanced_default_hwtcl_no_soft_reset=false,advanced_default_hwtcl_pclk_out_sel=pclk,advanced_default_hwtcl_pipex1_debug_sel=disable,advanced_default_hwtcl_register_pipe_signals=false,advanced_default_hwtcl_reserved_debug=0,advanced_default_hwtcl_retry_buffer_last_active_address=2047,advanced_default_hwtcl_rx_l0s_count_idl=0,advanced_default_hwtcl_set_l0s=0,advanced_default_hwtcl_skp_os_gen3_count=0,advanced_default_hwtcl_skp_os_schedule_count=0,advanced_default_hwtcl_ssid=0,advanced_default_hwtcl_ssvid=0,advanced_default_hwtcl_tph_completer=false,advanced_default_hwtcl_tx_cdc_almost_empty=5,advanced_default_hwtcl_vc0_clk_enable=true,advanced_default_hwtcl_wrong_device_id=disable,advanced_default_parameter_override=0,altpcie_avmm_hwtcl=1,app_interface_width_hwtcl=128,aspm_config_management_hwtcl=true,ast_width_hwtcl=Avalon-ST 128-bit,atomic_malformed_hwtcl=true,atomic_op_completer_32bit_hwtcl=false,atomic_op_completer_64bit_hwtcl=false,atomic_op_routing_hwtcl=false,av_rpre_emph_a_val_hwtcl=12,av_rpre_emph_b_val_hwtcl=0,av_rpre_emph_c_val_hwtcl=19,av_rpre_emph_d_val_hwtcl=13,av_rpre_emph_e_val_hwtcl=21,av_rvod_sel_a_val_hwtcl=42,av_rvod_sel_b_val_hwtcl=30,av_rvod_sel_c_val_hwtcl=43,av_rvod_sel_d_val_hwtcl=43,av_rvod_sel_e_val_hwtcl=9,avmm_burst_width_hwtcl=7,avmm_width_hwtcl=256,bar0_64bit_mem_space_hwtcl=Enabled,bar0_io_space_hwtcl=Disabled,bar0_prefetchable_hwtcl=Enabled,bar0_size_mask_hwtcl=9,bar0_type_hwtcl=64,bar1_io_space_hwtcl=Disabled,bar1_prefetchable_hwtcl=Disabled,bar1_size_mask_hwtcl=0,bar1_type_hwtcl=1,bar2_64bit_mem_space_hwtcl=Enabled,bar2_io_space_hwtcl=Disabled,bar2_prefetchable_hwtcl=Enabled,bar2_size_mask_hwtcl=12,bar2_type_hwtcl=64,bar3_io_space_hwtcl=Disabled,bar3_prefetchable_hwtcl=Disabled,bar3_size_mask_hwtcl=0,bar3_type_hwtcl=1,bar4_64bit_mem_space_hwtcl=Disabled,bar4_io_space_hwtcl=Disabled,bar4_prefetchable_hwtcl=Disabled,bar4_size_mask_hwtcl=0,bar4_type_hwtcl=1,bar5_io_space_hwtcl=Disabled,bar5_prefetchable_hwtcl=Disabled,bar5_size_mask_hwtcl=0,bar5_type_hwtcl=1,bridge_port_ssid_support_hwtcl=false,bridge_port_vga_enable_hwtcl=false,bypass_cdc_hwtcl=false,bypass_clk_switch_hwtcl=disable,cas_completer_128bit_hwtcl=false,cdc_dummy_insert_limit_advanced_default_hwtcl=11,cdc_dummy_insert_limit_hwtcl=11,class_code_hwtcl=0,completion_timeout_hwtcl=NONE,core_clk_sel_hwtcl=pld_clk,cpl_spc_data_hwtcl=781,cpl_spc_header_hwtcl=195,credit_buffer_allocation_aux_hwtcl=absolute,cseb_cpl_status_during_cvp_hwtcl=config_retry_status,cv_rpre_emph_a_val_hwtcl=11,cv_rpre_emph_b_val_hwtcl=0,cv_rpre_emph_c_val_hwtcl=22,cv_rpre_emph_d_val_hwtcl=12,cv_rpre_emph_e_val_hwtcl=21,cv_rvod_sel_a_val_hwtcl=50,cv_rvod_sel_b_val_hwtcl=34,cv_rvod_sel_c_val_hwtcl=50,cv_rvod_sel_d_val_hwtcl=50,cv_rvod_sel_e_val_hwtcl=9,cvp_clk_reset_hwtcl=false,cvp_data_compressed_hwtcl=false,cvp_data_encrypted_hwtcl=false,cvp_mode_reset_hwtcl=false,cvp_rate_sel_hwtcl=full_rate,d0_pme_advanced_default_hwtcl=false,d0_pme_hwtcl=false,d1_pme_advanced_default_hwtcl=false,d1_pme_hwtcl=false,d1_support_advanced_default_hwtcl=false,d1_support_hwtcl=false,d2_pme_advanced_default_hwtcl=false,d2_pme_hwtcl=false,d2_support_advanced_default_hwtcl=false,d2_support_hwtcl=false,d3_cold_pme_advanced_default_hwtcl=false,d3_cold_pme_hwtcl=false,d3_hot_pme_advanced_default_hwtcl=false,d3_hot_pme_hwtcl=false,data_pack_rx_hwtcl=disable,deemphasis_enable_advanced_default_hwtcl=false,deemphasis_enable_hwtcl=false,deskew_comma_hwtcl=skp_eieos_deskw,device_id_hwtcl=57347,device_number_advanced_default_hwtcl=0,device_number_hwtcl=0,diffclock_nfts_count_advanced_default_hwtcl=255,diffclock_nfts_count_hwtcl=128,disable_link_x2_support_advanced_default_hwtcl=false,disable_link_x2_support_hwtcl=false,disable_snoop_packet_hwtcl=false,dll_active_report_support_hwtcl=0,ecrc_check_capable_hwtcl=0,ecrc_gen_capable_hwtcl=0,ei_delay_powerdown_count_advanced_default_hwtcl=10,ei_delay_powerdown_count_hwtcl=10,eie_before_nfts_count_advanced_default_hwtcl=4,eie_before_nfts_count_hwtcl=4,enable_adapter_half_rate_mode_hwtcl=true,enable_completion_timeout_disable_hwtcl=1,enable_cra_hwtcl=0,enable_function_msix_support_hwtcl=0,enable_l0s_aspm_hwtcl=false,enable_l1_aspm_advanced_default_hwtcl=false,enable_l1_aspm_hwtcl=false,enable_pcisigtest_hwtcl=0,enable_power_on_rst_pulse_hwtcl=0,enable_rx_buffer_checking_advanced_default_hwtcl=false,enable_rx_buffer_checking_hwtcl=false,enable_rxm_burst_hwtcl=0,enable_slot_register_hwtcl=0,enable_tl_only_sim_hwtcl=0,endpoint_l0_latency_hwtcl=0,endpoint_l1_latency_hwtcl=0,expansion_base_address_register_hwtcl=0,extend_tag_field_hwtcl=32,extended_format_field_hwtcl=false,extended_tag_reset_hwtcl=false,fc_init_timer_advanced_default_hwtcl=1024,fc_init_timer_hwtcl=1024,fixed_address_mode=0,flow_control_timeout_count_advanced_default_hwtcl=200,flow_control_timeout_count_hwtcl=200,flow_control_update_count_advanced_default_hwtcl=30,flow_control_update_count_hwtcl=30,flr_capability_hwtcl=false,force_hrc=0,force_src=0,g3_bypass_equlz_hwtcl=0,g3_dis_rx_use_prst_ep_hwtcl=true,g3_dis_rx_use_prst_hwtcl=true,gen123_lane_rate_mode_hwtcl=Gen2 (5.0 Gbps),gen2_diffclock_nfts_count_advanced_default_hwtcl=255,gen2_diffclock_nfts_count_hwtcl=255,gen2_sameclock_nfts_count_advanced_default_hwtcl=255,gen2_sameclock_nfts_count_hwtcl=255,gen3_rxfreqlock_counter_hwtcl=0,gen3_skip_ph2_ph3_hwtcl=0,generate_sdc_for_qsys_design_example=0,hip_hard_reset_hwtcl=0,hip_reconfig_hwtcl=0,hip_tag_checking_hwtcl=1,hot_plug_support_advanced_default_hwtcl=0,hot_plug_support_hwtcl=0,hwtcl_override_g2_txvod=1,in_cvp_mode_hwtcl=0,indicator_advanced_default_hwtcl=0,indicator_hwtcl=0,internal_controller_hwtcl=1,interrupt_pin_hwtcl=inta,io_window_addr_width_hwtcl=0,l01_entry_latency_advanced_default_hwtcl=31,l01_entry_latency_hwtcl=31,l0_exit_latency_diffclock_advanced_default_hwtcl=6,l0_exit_latency_diffclock_hwtcl=6,l0_exit_latency_sameclock_advanced_default_hwtcl=6,l0_exit_latency_sameclock_hwtcl=6,l1_exit_latency_diffclock_advanced_default_hwtcl=0,l1_exit_latency_diffclock_hwtcl=0,l1_exit_latency_sameclock_advanced_default_hwtcl=0,l1_exit_latency_sameclock_hwtcl=0,l2_async_logic_advanced_default_hwtcl=disable,l2_async_logic_hwtcl=disable,lane_mask_hwtcl=x4,low_priority_vc_advanced_default_hwtcl=single_vc,low_priority_vc_hwtcl=single_vc,ltr_mechanism_hwtcl=false,ltssm_1ms_timeout_hwtcl=disable,ltssm_freqlocked_check_hwtcl=disable,max_payload_size_hwtcl=256,maximum_current_hwtcl=0,millisecond_cycle_count_hwtcl=124250,msi_64bit_addressing_capable_hwtcl=true,msi_masking_capable_hwtcl=false,msi_multi_message_capable_hwtcl=4,msi_support_hwtcl=true,msix_pba_bir_hwtcl=0,msix_pba_offset_hwtcl=0,msix_table_bir_hwtcl=0,msix_table_offset_hwtcl=0,msix_table_size_hwtcl=0,no_command_completed_advanced_default_hwtcl=false,no_command_completed_hwtcl=false,no_soft_reset_advanced_default_hwtcl=false,no_soft_reset_hwtcl=false,override_rxbuffer_cred_preset=0,override_tbpartner_driver_setting_hwtcl=0,pcie_qsys=1,pcie_spec_version_hwtcl=2.1,pclk_out_sel_advanced_default_hwtcl=pclk,pclk_out_sel_hwtcl=pclk,pipex1_debug_sel_advanced_default_hwtcl=disable,pipex1_debug_sel_hwtcl=disable,pld_clk_MHz=1250,pll_refclk_freq_hwtcl=100 MHz,port_link_number_hwtcl=1,port_type_hwtcl=Native endpoint,port_width_be_hwtcl=16,port_width_data_hwtcl=128,prefetchable_mem_window_addr_width_hwtcl=0,rd_dma_size_mask_hwtcl=15,reconfig_from_xcvr_width=230,reconfig_to_xcvr_width=350,register_pipe_signals_advanced_default_hwtcl=true,register_pipe_signals_hwtcl=true,reserved_debug_advanced_default_hwtcl=0,reserved_debug_hwtcl=0,retry_buffer_last_active_address_advanced_default_hwtcl=255,retry_buffer_last_active_address_hwtcl=2047,revision_id_hwtcl=1,rpre_emph_a_val_hwtcl=9,rpre_emph_b_val_hwtcl=0,rpre_emph_c_val_hwtcl=16,rpre_emph_d_val_hwtcl=13,rpre_emph_e_val_hwtcl=5,rvod_sel_a_val_hwtcl=42,rvod_sel_b_val_hwtcl=38,rvod_sel_c_val_hwtcl=38,rvod_sel_d_val_hwtcl=43,rvod_sel_e_val_hwtcl=15,rx_cdc_almost_full_advanced_default_hwtcl=12,rx_cdc_almost_full_hwtcl=12,rx_ei_l0s_hwtcl=0,rx_l0s_count_idl_advanced_default_hwtcl=0,rx_l0s_count_idl_hwtcl=0,rxbuffer_rxreq_hwtcl=Low,sameclock_nfts_count_advanced_default_hwtcl=255,sameclock_nfts_count_hwtcl=128,serial_sim_hwtcl=1,set_l0s_hwtcl=0,set_pld_clk_x1_625MHz_hwtcl=0,set_pll_coreclkout_cin_hwtcl=NA,set_pll_coreclkout_cout_hwtcl=NA,set_pll_coreclkout_slack=10,single_rx_detect_hwtcl=4,skp_os_gen3_count_hwtcl=0,skp_os_schedule_count_advanced_default_hwtcl=0,skp_os_schedule_count_hwtcl=0,slot_number_hwtcl=0,slot_power_limit_hwtcl=0,slot_power_scale_hwtcl=0,slotclkcfg_hwtcl=1,ssid_hwtcl=0,ssvid_hwtcl=0,subsystem_device_id_hwtcl=257,subsystem_vendor_id_hwtcl=0,surprise_down_error_support_hwtcl=0,tph_completer_hwtcl=false,tx_cdc_almost_empty_advanced_default_hwtcl=5,tx_cdc_almost_empty_hwtcl=5,tx_cdc_almost_full_advanced_default_hwtcl=11,tx_cdc_almost_full_hwtcl=11,use_aer_hwtcl=1,use_ast_parity=0,use_atx_pll_hwtcl=0,use_crc_forwarding_hwtcl=0,use_rx_st_be_hwtcl=0,use_tl_cfg_sync_advanced_default_hwtcl=1,use_tl_cfg_sync_hwtcl=1,vc0_clk_enable_advanced_default_hwtcl=true,vc0_clk_enable_hwtcl=true,vc0_rx_flow_ctrl_compl_data_hwtcl=0,vc0_rx_flow_ctrl_compl_header_hwtcl=0,vc0_rx_flow_ctrl_nonposted_data_hwtcl=0,vc0_rx_flow_ctrl_nonposted_header_hwtcl=16,vc0_rx_flow_ctrl_posted_data_hwtcl=16,vc0_rx_flow_ctrl_posted_header_hwtcl=16,vendor_id_hwtcl=4466,vsec_id_hwtcl=40960,vsec_rev_hwtcl=0,wr_dma_size_mask_hwtcl=12,wrong_device_id_hwtcl=disable"
   instancePathKey="top:.:pcie_256_hip_avmm_0"
   kind="altera_pcie_256_hip_avmm"
   version="14.0"
   name="altpcie_256_hip_avmm_hwtcl">
  <parameter name="deemphasis_enable_hwtcl" value="false" />
  <parameter name="bar3_io_space_hwtcl" value="Disabled" />
  <parameter name="advanced_default_hwtcl_ssvid" value="0" />
  <parameter name="CG_COMMON_CLOCK_MODE" value="1" />
  <parameter name="rvod_sel_d_val_hwtcl" value="43" />
  <parameter name="use_crc_forwarding_hwtcl" value="0" />
  <parameter name="enable_power_on_rst_pulse_hwtcl" value="0" />
  <parameter name="enable_slot_register_hwtcl" value="0" />
  <parameter name="d2_pme_hwtcl" value="false" />
  <parameter name="reconfig_from_xcvr_width" value="230" />
  <parameter name="port_width_data_hwtcl" value="128" />
  <parameter name="advanced_default_hwtcl_l1_exit_latency_sameclock" value="0" />
  <parameter name="advanced_default_hwtcl_disable_snoop_packet" value="false" />
  <parameter name="av_rpre_emph_d_val_hwtcl" value="13" />
  <parameter name="advanced_default_hwtcl_vc0_clk_enable" value="true" />
  <parameter name="advanced_default_hwtcl_cas_completer_128bit" value="false" />
  <parameter name="rd_dma_size_mask_hwtcl" value="15" />
  <parameter name="l0_exit_latency_diffclock_hwtcl" value="6" />
  <parameter name="advanced_default_hwtcl_d2_pme" value="false" />
  <parameter name="bar5_prefetchable_hwtcl" value="Disabled" />
  <parameter name="low_priority_vc_hwtcl" value="single_vc" />
  <parameter name="vc0_clk_enable_hwtcl" value="true" />
  <parameter name="enable_rx_buffer_checking_advanced_default_hwtcl" value="false" />
  <parameter name="bridge_port_vga_enable_hwtcl" value="false" />
  <parameter name="force_src" value="0" />
  <parameter name="vc0_rx_flow_ctrl_posted_data_hwtcl" value="16" />
  <parameter name="disable_snoop_packet_hwtcl" value="false" />
  <parameter name="advanced_default_hwtcl_deskew_comma" value="com_deskw" />
  <parameter name="hip_reconfig_hwtcl" value="0" />
  <parameter name="eie_before_nfts_count_advanced_default_hwtcl" value="4" />
  <parameter name="advanced_default_hwtcl_enable_l1_aspm" value="false" />
  <parameter name="ltr_mechanism_hwtcl" value="false" />
  <parameter name="pclk_out_sel_advanced_default_hwtcl" value="pclk" />
  <parameter name="enable_pcisigtest_hwtcl" value="0" />
  <parameter name="av_rvod_sel_e_val_hwtcl" value="9" />
  <parameter name="hip_hard_reset_hwtcl" value="0" />
  <parameter name="wrong_device_id_hwtcl" value="disable" />
  <parameter name="enable_l0s_aspm_hwtcl" value="false" />
  <parameter name="advanced_default_hwtcl_tph_completer" value="false" />
  <parameter name="atomic_op_routing_hwtcl" value="false" />
  <parameter name="advanced_default_hwtcl_data_pack_rx" value="disable" />
  <parameter name="msix_table_bir_hwtcl" value="0" />
  <parameter name="rvod_sel_b_val_hwtcl" value="38" />
  <parameter name="advanced_default_hwtcl_skp_os_gen3_count" value="0" />
  <parameter name="gen2_sameclock_nfts_count_hwtcl" value="255" />
  <parameter name="cv_rvod_sel_e_val_hwtcl" value="9" />
  <parameter name="enable_rxm_burst_hwtcl" value="0" />
  <parameter name="gen123_lane_rate_mode_hwtcl" value="Gen2 (5.0 Gbps)" />
  <parameter name="advanced_default_hwtcl_rx_l0s_count_idl" value="0" />
  <parameter name="advanced_default_hwtcl_d2_support" value="false" />
  <parameter name="rx_l0s_count_idl_advanced_default_hwtcl" value="0" />
  <parameter name="rx_cdc_almost_full_hwtcl" value="12" />
  <parameter name="set_pll_coreclkout_cin_hwtcl" value="NA" />
  <parameter name="cpl_spc_header_hwtcl" value="195" />
  <parameter name="l1_exit_latency_sameclock_hwtcl" value="0" />
  <parameter name="advanced_default_hwtcl_bridge_port_vga_enable" value="false" />
  <parameter name="avmm_width_hwtcl" value="256" />
  <parameter name="port_link_number_hwtcl" value="1" />
  <parameter name="RD_SLAVE_ADDRESS_MAP" value="15" />
  <parameter name="rx_l0s_count_idl_hwtcl" value="0" />
  <parameter name="hwtcl_override_g2_txvod" value="1" />
  <parameter name="rpre_emph_b_val_hwtcl" value="0" />
  <parameter name="cv_rvod_sel_d_val_hwtcl" value="50" />
  <parameter name="cv_rpre_emph_b_val_hwtcl" value="0" />
  <parameter name="flow_control_timeout_count_hwtcl" value="200" />
  <parameter name="enable_l1_aspm_advanced_default_hwtcl" value="false" />
  <parameter name="advanced_default_hwtcl_no_command_completed" value="false" />
  <parameter name="advanced_default_hwtcl_atomic_op_completer_32bit" value="false" />
  <parameter name="endpoint_l0_latency_hwtcl" value="0" />
  <parameter name="credit_buffer_allocation_aux_hwtcl" value="absolute" />
  <parameter name="rpre_emph_d_val_hwtcl" value="13" />
  <parameter name="use_tl_cfg_sync_hwtcl" value="1" />
  <parameter name="advanced_default_hwtcl_tx_cdc_almost_empty" value="5" />
  <parameter name="g3_dis_rx_use_prst_hwtcl" value="true" />
  <parameter name="interrupt_pin_hwtcl" value="inta" />
  <parameter name="altpcie_avmm_hwtcl" value="1" />
  <parameter name="g3_dis_rx_use_prst_ep_hwtcl" value="true" />
  <parameter name="rvod_sel_c_val_hwtcl" value="38" />
  <parameter name="d0_pme_advanced_default_hwtcl" value="false" />
  <parameter name="ecrc_gen_capable_hwtcl" value="0" />
  <parameter name="indicator_hwtcl" value="0" />
  <parameter name="add_pll_to_hip_coreclkout" value="0" />
  <parameter name="cas_completer_128bit_hwtcl" value="false" />
  <parameter name="diffclock_nfts_count_advanced_default_hwtcl" value="255" />
  <parameter name="cvp_mode_reset_hwtcl" value="false" />
  <parameter name="d1_pme_hwtcl" value="false" />
  <parameter name="tx_cdc_almost_full_advanced_default_hwtcl" value="11" />
  <parameter name="msi_multi_message_capable_hwtcl" value="4" />
  <parameter name="ssid_hwtcl" value="0" />
  <parameter name="cv_rpre_emph_d_val_hwtcl" value="12" />
  <parameter name="rx_ei_l0s_hwtcl" value="0" />
  <parameter name="advanced_default_hwtcl_ltssm_freqlocked_check" value="disable" />
  <parameter name="dll_active_report_support_hwtcl" value="0" />
  <parameter name="cv_rvod_sel_a_val_hwtcl" value="50" />
  <parameter name="completion_timeout_hwtcl" value="NONE" />
  <parameter name="DMA_BRST_CNT_W" value="6" />
  <parameter name="rvod_sel_e_val_hwtcl" value="15" />
  <parameter name="cvp_clk_reset_hwtcl" value="false" />
  <parameter name="DMA_WIDTH" value="128" />
  <parameter name="hot_plug_support_hwtcl" value="0" />
  <parameter name="msi_64bit_addressing_capable_hwtcl" value="true" />
  <parameter name="advanced_default_hwtcl_ltssm_1ms_timeout" value="disable" />
  <parameter name="generate_sdc_for_qsys_design_example" value="0" />
  <parameter name="sameclock_nfts_count_hwtcl" value="128" />
  <parameter name="bypass_cdc_hwtcl" value="false" />
  <parameter name="force_hrc" value="0" />
  <parameter name="gen2_diffclock_nfts_count_hwtcl" value="255" />
  <parameter name="advanced_default_hwtcl_extended_tag_reset" value="false" />
  <parameter name="extend_tag_field_hwtcl" value="32" />
  <parameter name="av_rvod_sel_d_val_hwtcl" value="43" />
  <parameter name="bar3_prefetchable_hwtcl" value="Disabled" />
  <parameter name="no_command_completed_advanced_default_hwtcl" value="false" />
  <parameter name="gen3_skip_ph2_ph3_hwtcl" value="0" />
  <parameter name="gen3_rxfreqlock_counter_hwtcl" value="0" />
  <parameter name="io_window_addr_width_hwtcl" value="0" />
  <parameter name="register_pipe_signals_advanced_default_hwtcl" value="true" />
  <parameter name="l1_exit_latency_diffclock_advanced_default_hwtcl" value="0" />
  <parameter name="bar4_size_mask_hwtcl" value="0" />
  <parameter name="slot_power_limit_hwtcl" value="0" />
  <parameter name="advanced_default_hwtcl_d3_hot_pme" value="false" />
  <parameter name="bar2_64bit_mem_space_hwtcl" value="Enabled" />
  <parameter name="gen2_sameclock_nfts_count_advanced_default_hwtcl" value="255" />
  <parameter name="rpre_emph_a_val_hwtcl" value="9" />
  <parameter name="slot_number_hwtcl" value="0" />
  <parameter name="disable_link_x2_support_advanced_default_hwtcl" value="false" />
  <parameter name="internal_controller_hwtcl" value="1" />
  <parameter name="advanced_default_hwtcl_d3_cold_pme" value="false" />
  <parameter name="msix_pba_offset_hwtcl" value="0" />
  <parameter name="advanced_default_hwtcl_flow_control_update_count" value="30" />
  <parameter
     name="retry_buffer_last_active_address_advanced_default_hwtcl"
     value="255" />
  <parameter name="device_number_advanced_default_hwtcl" value="0" />
  <parameter name="cdc_dummy_insert_limit_advanced_default_hwtcl" value="11" />
  <parameter name="cseb_cpl_status_during_cvp_hwtcl" value="config_retry_status" />
  <parameter name="msi_masking_capable_hwtcl" value="false" />
  <parameter name="slotclkcfg_hwtcl" value="1" />
  <parameter name="DMA_BE_WIDTH" value="16" />
  <parameter name="set_pll_coreclkout_slack" value="10" />
  <parameter name="ast_width_hwtcl" value="Avalon-ST 128-bit" />
  <parameter name="bar1_size_mask_hwtcl" value="0" />
  <parameter name="pld_clk_MHz" value="1250" />
  <parameter name="deskew_comma_hwtcl" value="skp_eieos_deskw" />
  <parameter
     name="advanced_default_hwtcl_retry_buffer_last_active_address"
     value="2047" />
  <parameter name="bar0_64bit_mem_space_hwtcl" value="Enabled" />
  <parameter name="bar0_prefetchable_hwtcl" value="Enabled" />
  <parameter name="set_pll_coreclkout_cout_hwtcl" value="NA" />
  <parameter name="enable_adapter_half_rate_mode_hwtcl" value="true" />
  <parameter name="bar4_64bit_mem_space_hwtcl" value="Disabled" />
  <parameter name="advanced_default_hwtcl_extended_format_field" value="false" />
  <parameter name="enable_tl_only_sim_hwtcl" value="0" />
  <parameter name="low_priority_vc_advanced_default_hwtcl" value="single_vc" />
  <parameter name="NUM_PREFETCH_MASTERS" value="1" />
  <parameter name="avmm_burst_width_hwtcl" value="7" />
  <parameter name="use_atx_pll_hwtcl" value="0" />
  <parameter name="vc0_clk_enable_advanced_default_hwtcl" value="true" />
  <parameter name="advanced_default_hwtcl_l0_exit_latency_diffclock" value="6" />
  <parameter name="vc0_rx_flow_ctrl_nonposted_data_hwtcl" value="0" />
  <parameter name="vsec_id_hwtcl" value="40960" />
  <parameter name="aspm_config_management_hwtcl" value="true" />
  <parameter name="CG_RXM_IRQ_NUM" value="16" />
  <parameter name="d2_pme_advanced_default_hwtcl" value="false" />
  <parameter name="bar3_type_hwtcl" value="1" />
  <parameter name="enable_completion_timeout_disable_hwtcl" value="1" />
  <parameter name="set_l0s_hwtcl" value="0" />
  <parameter name="bar4_io_space_hwtcl" value="Disabled" />
  <parameter name="bar2_type_hwtcl" value="64" />
  <parameter name="CB_P2A_FIXED_AVALON_ADDR_B0" value="0" />
  <parameter name="advanced_default_hwtcl_flr_capability" value="false" />
  <parameter name="ltssm_1ms_timeout_hwtcl" value="disable" />
  <parameter name="cv_rpre_emph_a_val_hwtcl" value="11" />
  <parameter name="d3_hot_pme_advanced_default_hwtcl" value="false" />
  <parameter name="av_rvod_sel_a_val_hwtcl" value="42" />
  <parameter name="CB_P2A_FIXED_AVALON_ADDR_B5" value="0" />
  <parameter name="advanced_default_hwtcl_ltr_mechanism" value="false" />
  <parameter name="cpl_spc_data_hwtcl" value="781" />
  <parameter name="expansion_base_address_register_hwtcl" value="0" />
  <parameter name="advanced_default_hwtcl_pipex1_debug_sel" value="disable" />
  <parameter name="CB_P2A_FIXED_AVALON_ADDR_B3" value="0" />
  <parameter name="lane_mask_hwtcl" value="x4" />
  <parameter name="tx_cdc_almost_empty_hwtcl" value="5" />
  <parameter name="class_code_hwtcl" value="0" />
  <parameter name="CB_P2A_FIXED_AVALON_ADDR_B4" value="0" />
  <parameter name="vsec_rev_hwtcl" value="0" />
  <parameter name="l0_exit_latency_sameclock_advanced_default_hwtcl" value="6" />
  <parameter name="CB_P2A_FIXED_AVALON_ADDR_B1" value="0" />
  <parameter name="CB_P2A_FIXED_AVALON_ADDR_B2" value="0" />
  <parameter name="prefetchable_mem_window_addr_width_hwtcl" value="0" />
  <parameter name="TX_S_ADDR_WIDTH" value="32" />
  <parameter name="fc_init_timer_hwtcl" value="1024" />
  <parameter name="pipex1_debug_sel_advanced_default_hwtcl" value="disable" />
  <parameter name="set_pld_clk_x1_625MHz_hwtcl" value="0" />
  <parameter name="port_width_be_hwtcl" value="16" />
  <parameter name="advanced_default_hwtcl_bridge_port_ssid_support" value="false" />
  <parameter name="WR_SLAVE_ADDRESS_MAP" value="12" />
  <parameter name="no_soft_reset_advanced_default_hwtcl" value="false" />
  <parameter name="fc_init_timer_advanced_default_hwtcl" value="1024" />
  <parameter name="extended_format_field_hwtcl" value="false" />
  <parameter name="d3_hot_pme_hwtcl" value="false" />
  <parameter name="bar2_prefetchable_hwtcl" value="Enabled" />
  <parameter name="advanced_default_hwtcl_low_priority_vc" value="single_vc" />
  <parameter name="rxbuffer_rxreq_hwtcl" value="Low" />
  <parameter name="subsystem_vendor_id_hwtcl" value="0" />
  <parameter name="advanced_default_hwtcl_enable_rx_buffer_checking" value="false" />
  <parameter name="ecrc_check_capable_hwtcl" value="0" />
  <parameter name="l1_exit_latency_diffclock_hwtcl" value="0" />
  <parameter name="atomic_op_completer_32bit_hwtcl" value="false" />
  <parameter name="indicator_advanced_default_hwtcl" value="0" />
  <parameter name="cv_rpre_emph_c_val_hwtcl" value="22" />
  <parameter name="d3_cold_pme_advanced_default_hwtcl" value="false" />
  <parameter name="maximum_current_hwtcl" value="0" />
  <parameter name="advanced_default_hwtcl_l1_exit_latency_diffclock" value="0" />
  <parameter name="tx_cdc_almost_empty_advanced_default_hwtcl" value="5" />
  <parameter name="no_soft_reset_hwtcl" value="false" />
  <parameter name="bar4_type_hwtcl" value="1" />
  <parameter name="diffclock_nfts_count_hwtcl" value="128" />
  <parameter name="bar2_io_space_hwtcl" value="Disabled" />
  <parameter name="bar0_size_mask_hwtcl" value="9" />
  <parameter name="pclk_out_sel_hwtcl" value="pclk" />
  <parameter name="eie_before_nfts_count_hwtcl" value="4" />
  <parameter name="vc0_rx_flow_ctrl_compl_header_hwtcl" value="0" />
  <parameter name="AUTO_REFCLK_CLOCK_RATE" value="0" />
  <parameter name="tx_cdc_almost_full_hwtcl" value="11" />
  <parameter name="app_interface_width_hwtcl" value="128" />
  <parameter name="advanced_default_hwtcl_d1_support" value="false" />
  <parameter name="enable_l1_aspm_hwtcl" value="false" />
  <parameter name="rvod_sel_a_val_hwtcl" value="42" />
  <parameter name="l0_exit_latency_diffclock_advanced_default_hwtcl" value="6" />
  <parameter name="CB_P2A_AVALON_ADDR_B0" value="0x00000000" />
  <parameter name="advanced_default_hwtcl_device_number" value="0" />
  <parameter name="CB_P2A_AVALON_ADDR_B1" value="0x00000000" />
  <parameter name="g3_bypass_equlz_hwtcl" value="0" />
  <parameter name="CB_P2A_AVALON_ADDR_B2" value="0x00000000" />
  <parameter name="l0_exit_latency_sameclock_hwtcl" value="6" />
  <parameter name="CB_P2A_AVALON_ADDR_B3" value="0x00000000" />
  <parameter name="INTENDED_DEVICE_FAMILY" value="Arria V" />
  <parameter name="advanced_default_hwtcl_ei_delay_powerdown_count" value="10" />
  <parameter name="surprise_down_error_support_hwtcl" value="0" />
  <parameter name="flow_control_update_count_advanced_default_hwtcl" value="30" />
  <parameter name="l2_async_logic_hwtcl" value="disable" />
  <parameter name="bar2_size_mask_hwtcl" value="12" />
  <parameter name="advanced_default_hwtcl_d1_pme" value="false" />
  <parameter name="fixed_address_mode" value="0" />
  <parameter name="wr_dma_size_mask_hwtcl" value="12" />
  <parameter name="flow_control_update_count_hwtcl" value="30" />
  <parameter name="reserved_debug_hwtcl" value="0" />
  <parameter name="vc0_rx_flow_ctrl_posted_header_hwtcl" value="16" />
  <parameter name="vc0_rx_flow_ctrl_compl_data_hwtcl" value="0" />
  <parameter name="bypass_clk_switch_hwtcl" value="disable" />
  <parameter name="rpre_emph_e_val_hwtcl" value="5" />
  <parameter name="vc0_rx_flow_ctrl_nonposted_header_hwtcl" value="16" />
  <parameter name="advanced_default_hwtcl_skp_os_schedule_count" value="0" />
  <parameter name="advanced_default_hwtcl_no_soft_reset" value="false" />
  <parameter name="av_rpre_emph_e_val_hwtcl" value="21" />
  <parameter name="sameclock_nfts_count_advanced_default_hwtcl" value="255" />
  <parameter name="bar3_size_mask_hwtcl" value="0" />
  <parameter name="cv_rpre_emph_e_val_hwtcl" value="21" />
  <parameter name="cdc_dummy_insert_limit_hwtcl" value="11" />
  <parameter name="advanced_default_hwtcl_ssid" value="0" />
  <parameter name="core_clk_sel_hwtcl" value="pld_clk" />
  <parameter name="enable_function_msix_support_hwtcl" value="0" />
  <parameter name="d2_support_hwtcl" value="false" />
  <parameter name="pcie_qsys" value="1" />
  <parameter
     name="advanced_default_hwtcl_enable_adapter_half_rate_mode"
     value="false" />
  <parameter name="SLAVE_ADDRESS_MAP_5" value="0" />
  <parameter name="ei_delay_powerdown_count_advanced_default_hwtcl" value="10" />
  <parameter name="SLAVE_ADDRESS_MAP_4" value="0" />
  <parameter name="av_rpre_emph_c_val_hwtcl" value="19" />
  <parameter name="SLAVE_ADDRESS_MAP_3" value="0" />
  <parameter name="SLAVE_ADDRESS_MAP_2" value="12" />
  <parameter name="SLAVE_ADDRESS_MAP_1" value="0" />
  <parameter name="advanced_default_hwtcl_wrong_device_id" value="disable" />
  <parameter name="SLAVE_ADDRESS_MAP_0" value="0" />
  <parameter name="vendor_id_hwtcl" value="4466" />
  <parameter name="l01_entry_latency_advanced_default_hwtcl" value="31" />
  <parameter name="advanced_default_hwtcl_gen2_diffclock_nfts_count" value="255" />
  <parameter name="cvp_data_compressed_hwtcl" value="false" />
  <parameter name="retry_buffer_last_active_address_hwtcl" value="2047" />
  <parameter name="bar1_type_hwtcl" value="1" />
  <parameter name="bar5_type_hwtcl" value="1" />
  <parameter name="msi_support_hwtcl" value="true" />
  <parameter name="flr_capability_hwtcl" value="false" />
  <parameter name="deemphasis_enable_advanced_default_hwtcl" value="false" />
  <parameter name="skp_os_schedule_count_advanced_default_hwtcl" value="0" />
  <parameter name="d1_support_advanced_default_hwtcl" value="false" />
  <parameter name="bar5_io_space_hwtcl" value="Disabled" />
  <parameter name="hip_tag_checking_hwtcl" value="1" />
  <parameter name="advanced_default_hwtcl_cdc_dummy_insert_limit" value="11" />
  <parameter name="rpre_emph_c_val_hwtcl" value="16" />
  <parameter name="use_rx_st_be_hwtcl" value="0" />
  <parameter name="advanced_default_hwtcl_reserved_debug" value="0" />
  <parameter name="advanced_default_hwtcl_register_pipe_signals" value="false" />
  <parameter name="advanced_default_hwtcl_interrupt_pin" value="inta" />
  <parameter name="tph_completer_hwtcl" value="false" />
  <parameter name="reconfig_to_xcvr_width" value="350" />
  <parameter name="msix_pba_bir_hwtcl" value="0" />
  <parameter name="av_rvod_sel_c_val_hwtcl" value="43" />
  <parameter name="atomic_malformed_hwtcl" value="true" />
  <parameter name="av_rpre_emph_a_val_hwtcl" value="12" />
  <parameter name="advanced_default_hwtcl_disable_link_x2_support" value="false" />
  <parameter name="subsystem_device_id_hwtcl" value="257" />
  <parameter name="bar1_prefetchable_hwtcl" value="Disabled" />
  <parameter name="msix_table_size_hwtcl" value="0" />
  <parameter name="d2_support_advanced_default_hwtcl" value="false" />
  <parameter name="serial_sim_hwtcl" value="1" />
  <parameter name="d1_support_hwtcl" value="false" />
  <parameter name="no_command_completed_hwtcl" value="false" />
  <parameter name="advanced_default_hwtcl_fc_init_timer" value="1024" />
  <parameter name="atomic_op_completer_64bit_hwtcl" value="false" />
  <parameter name="flow_control_timeout_count_advanced_default_hwtcl" value="200" />
  <parameter name="bridge_port_ssid_support_hwtcl" value="false" />
  <parameter name="cv_rvod_sel_b_val_hwtcl" value="34" />
  <parameter name="bar0_io_space_hwtcl" value="Disabled" />
  <parameter name="advanced_default_hwtcl_eie_before_nfts_count" value="4" />
  <parameter name="cvp_rate_sel_hwtcl" value="full_rate" />
  <parameter name="skp_os_gen3_count_hwtcl" value="0" />
  <parameter name="cvp_data_encrypted_hwtcl" value="false" />
  <parameter name="port_type_hwtcl" value="Native endpoint" />
  <parameter name="advanced_default_hwtcl_bypass_cdc" value="false" />
  <parameter name="enable_cra_hwtcl" value="0" />
  <parameter name="l2_async_logic_advanced_default_hwtcl" value="disable" />
  <parameter name="use_aer_hwtcl" value="1" />
  <parameter name="pcie_spec_version_hwtcl" value="2.1" />
  <parameter name="bar4_prefetchable_hwtcl" value="Disabled" />
  <parameter name="hot_plug_support_advanced_default_hwtcl" value="0" />
  <parameter name="advanced_default_hwtcl_flow_control_timeout_count" value="200" />
  <parameter name="data_pack_rx_hwtcl" value="disable" />
  <parameter name="pll_refclk_freq_hwtcl" value="100 MHz" />
  <parameter name="d1_pme_advanced_default_hwtcl" value="false" />
  <parameter name="disable_link_x2_support_hwtcl" value="false" />
  <parameter name="bar0_type_hwtcl" value="64" />
  <parameter name="l01_entry_latency_hwtcl" value="31" />
  <parameter name="msix_table_offset_hwtcl" value="0" />
  <parameter name="override_tbpartner_driver_setting_hwtcl" value="0" />
  <parameter name="av_rpre_emph_b_val_hwtcl" value="0" />
  <parameter name="single_rx_detect_hwtcl" value="4" />
  <parameter name="av_rvod_sel_b_val_hwtcl" value="30" />
  <parameter name="advanced_default_hwtcl_l01_entry_latency" value="31" />
  <parameter name="CB_P2A_AVALON_ADDR_B4" value="0x00000000" />
  <parameter name="CB_P2A_AVALON_ADDR_B5" value="0x00000000" />
  <parameter name="gen2_diffclock_nfts_count_advanced_default_hwtcl" value="255" />
  <parameter name="advanced_default_parameter_override" value="0" />
  <parameter name="d3_cold_pme_hwtcl" value="false" />
  <parameter name="advanced_default_hwtcl_set_l0s" value="0" />
  <parameter name="ei_delay_powerdown_count_hwtcl" value="10" />
  <parameter name="device_number_hwtcl" value="0" />
  <parameter name="l1_exit_latency_sameclock_advanced_default_hwtcl" value="0" />
  <parameter name="reserved_debug_advanced_default_hwtcl" value="0" />
  <parameter name="d0_pme_hwtcl" value="false" />
  <parameter name="advanced_default_hwtcl_d0_pme" value="false" />
  <parameter name="skp_os_schedule_count_hwtcl" value="0" />
  <parameter name="extended_tag_reset_hwtcl" value="false" />
  <parameter name="use_tl_cfg_sync_advanced_default_hwtcl" value="1" />
  <parameter name="advanced_default_hwtcl_hot_plug_support" value="0" />
  <parameter name="advanced_default_hwtcl_pclk_out_sel" value="pclk" />
  <parameter name="max_payload_size_hwtcl" value="256" />
  <parameter name="bar5_size_mask_hwtcl" value="0" />
  <parameter name="register_pipe_signals_hwtcl" value="true" />
  <parameter name="advanced_default_hwtcl_atomic_malformed" value="true" />
  <parameter name="pipex1_debug_sel_hwtcl" value="disable" />
  <parameter name="in_cvp_mode_hwtcl" value="0" />
  <parameter name="cv_rvod_sel_c_val_hwtcl" value="50" />
  <parameter name="advanced_default_hwtcl_atomic_op_completer_64bit" value="false" />
  <parameter name="revision_id_hwtcl" value="1" />
  <parameter name="override_rxbuffer_cred_preset" value="0" />
  <parameter name="device_id_hwtcl" value="57347" />
  <parameter name="use_ast_parity" value="0" />
  <parameter name="slot_power_scale_hwtcl" value="0" />
  <parameter name="endpoint_l1_latency_hwtcl" value="0" />
  <parameter name="millisecond_cycle_count_hwtcl" value="124250" />
  <parameter name="advanced_default_hwtcl_gen2_sameclock_nfts_count" value="255" />
  <parameter name="enable_rx_buffer_checking_hwtcl" value="false" />
  <parameter name="rx_cdc_almost_full_advanced_default_hwtcl" value="12" />
  <parameter name="ltssm_freqlocked_check_hwtcl" value="disable" />
  <parameter name="ssvid_hwtcl" value="0" />
  <parameter name="bar1_io_space_hwtcl" value="Disabled" />
  <parameter name="advanced_default_hwtcl_atomic_op_routing" value="false" />
  <parameter name="advanced_default_hwtcl_maximum_current" value="0" />
  <parameter name="advanced_default_hwtcl_l0_exit_latency_sameclock" value="6" />
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       attributes="" />
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       attributes="" />
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       attributes="" />
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   <file
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       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_pcie_sv_hip_ast_pipen1b.sdc"
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       attributes="" />
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       type="SDC"
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  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/altera_pcie/altera_pcie_hip_256_avmm/altera_pcie_256_hip_avmm_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top" as="pcie_256_hip_avmm_0" />
  <messages>
   <message level="Debug" culprit="top">queue size: 6 starting:altera_pcie_256_hip_avmm "submodules/altpcie_256_hip_avmm_hwtcl"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./sv_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_xcvr.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./sv_reconfig_bundle_to_ip.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_ip.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./sv_reconfig_bundle_merger.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_merger.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_reset_ctrl_lego.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_reset_ctrl_lego.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_reset_ctrl_tgx_cdrauto.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_reset_ctrl_tgx_cdrauto.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_csr_common_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_common_h.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_csr_common.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_common.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_csr_pcs8g_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_pcs8g_h.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_csr_pcs8g.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_pcs8g.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./alt_xcvr_mgmt2dec.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_mgmt2dec.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_avmm_csr.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_tx_pma_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_tx_pma_ch.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_tx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_tx_pma.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_rx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_rx_pma.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pma.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_pcs_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pcs_ch.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_pcs.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pcs.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_avmm.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_native.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_native.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_plls.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_plls.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_data_adapter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_data_adapter.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_8g_rx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_8g_rx_pcs_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_8g_tx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_8g_tx_pcs_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_common_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_common_pcs_pma_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_common_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_common_pld_pcs_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_pipe_gen1_2_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_pipe_gen1_2_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_rx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_rx_pcs_pma_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_rx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_rx_pld_pcs_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_tx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_tx_pcs_pma_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_hssi_tx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_tx_pld_pcs_interface_rbc.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_pipe_native.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_pipe_native.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_emsip_adapter.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_emsip_adapter.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0">add_fileset_file ./av_xcvr_pipe_native_hip.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_pipe_native_hip.sv</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0"><![CDATA["<b>top</b>" instantiated <b>altera_pcie_256_hip_avmm</b> "<b>pcie_256_hip_avmm_0</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_xcvr_functions.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_resync.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_csr_selector.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_wait_generate.v</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/av_xcvr_h.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/av_reconfig_bundle_to_basic.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/av_reconfig_bundle_to_xcvr.sv</b>]]></message>
   <message level="Warning"><![CDATA[Overwriting different file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/plain_files.txt</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_avalon_onchip_memory2:14.0:allowInSystemMemoryContentEditor=false,autoInitializationFileName=top_onchip_memory2_0,blockType=AUTO,dataWidth=128,derived_gui_ram_block_type=Automatic,derived_init_file_name=top_onchip_memory2_0.hex,derived_is_hardcopy=false,derived_set_addr_width=8,derived_set_data_width=128,deviceFamily=Arria V,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,initMemContent=true,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=4096,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true"
   instancePathKey="top:.:onchip_memory2_0"
   kind="altera_avalon_onchip_memory2"
   version="14.0"
   name="top_onchip_memory2_0">
  <parameter name="dataWidth" value="128" />
  <parameter name="ecc_enabled" value="false" />
  <parameter name="instanceID" value="NONE" />
  <parameter name="writable" value="true" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="initMemContent" value="true" />
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="dualPort" value="true" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="resetrequest_enabled" value="true" />
  <parameter name="derived_is_hardcopy" value="false" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="derived_gui_ram_block_type" value="Automatic" />
  <parameter name="derived_set_addr_width" value="8" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="memorySize" value="4096" />
  <parameter name="simMemInitOnlyFilename" value="0" />
  <parameter name="initializationFileName" value="onchip_mem.hex" />
  <parameter name="deviceFamily" value="Arria V" />
  <parameter name="singleClockOperation" value="false" />
  <parameter name="derived_set_data_width" value="128" />
  <parameter name="derived_init_file_name" value="top_onchip_memory2_0.hex" />
  <parameter
     name="deviceFeatures"
     value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
  <parameter name="blockType" value="AUTO" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="autoInitializationFileName" value="top_onchip_memory2_0" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_onchip_memory2_0.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_onchip_memory2_0.hex"
       type="HEX"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top" as="onchip_memory2_0" />
  <messages>
   <message level="Debug" culprit="top">queue size: 5 starting:altera_avalon_onchip_memory2 "submodules/top_onchip_memory2_0"</message>
   <message level="Info" culprit="onchip_memory2_0">Starting RTL generation for module 'top_onchip_memory2_0'</message>
   <message level="Info" culprit="onchip_memory2_0">  Generation command is [exec /tools_archive/acds/14.0/200/linux64/quartus/linux64/perl/bin/perl -I /tools_archive/acds/14.0/200/linux64/quartus/linux64/perl/lib -I /tools_archive/acds/14.0/200/linux64/quartus/sopc_builder/bin/europa -I /tools_archive/acds/14.0/200/linux64/quartus/sopc_builder/bin/perl_lib -I /tools_archive/acds/14.0/200/linux64/quartus/sopc_builder/bin -I /tools_archive/acds/14.0/200/linux64/quartus/../ip/altera/sopc_builder_ip/common -I /tools_archive/acds/14.0/200/linux64/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /tools_archive/acds/14.0/200/linux64/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=top_onchip_memory2_0 --dir=/build/arc/temp/217396113/alt6288_3873220473054358287.dir/0004_onchip_memory2_0_gen/ --quartus_dir=/tools_archive/acds/14.0/200/linux64/quartus --verilog --config=/build/arc/temp/217396113/alt6288_3873220473054358287.dir/0004_onchip_memory2_0_gen//top_onchip_memory2_0_component_configuration.pl  --do_build_sim=0  ]</message>
   <message level="Info" culprit="onchip_memory2_0">Done RTL generation for module 'top_onchip_memory2_0'</message>
   <message level="Info" culprit="onchip_memory2_0"><![CDATA["<b>top</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>onchip_memory2_0</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_mm_interconnect:14.0:AUTO_DEVICE=5AGXFB3H4F35C5,AUTO_DEVICE_FAMILY=Arria V,COMPOSE_CONTENTS=add_instance {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {altera_merlin_master_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_DATA_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_READDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_READ} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_ALWAYSBURSTMAXBURST} {0};add_instance {pcie_256_hip_avmm_0_dma_rd_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_DATA_W} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_BURSTCOUNT_W} {6};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_BYTEENABLE_W} {16};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {UAV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_READDATA} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_READ} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_SYMBOLS_PER_WORD} {16};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};add_instance {onchip_memory2_0_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_DATA_W} {128};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_DATA_W} {128};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_BYTEENABLE_W} {16};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_BYTEENABLE_W} {16};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_BURSTCOUNT_W} {5};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_READ} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_SYMBOLS_PER_WORD} {16};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_DATA_W} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_DATA_W} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_BURSTCOUNT_W} {5};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_BYTEENABLE_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_BYTEENABLE_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_READDATA} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_READ} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_SYMBOLS_PER_WORD} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_DATA_W} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_DATA_W} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_BURSTCOUNT_W} {5};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_BYTEENABLE_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_BYTEENABLE_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_READDATA} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_READ} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_SYMBOLS_PER_WORD} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {altera_merlin_master_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_PROTECTION_H} {133};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_PROTECTION_L} {131};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BEGIN_BURST} {124};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURSTWRAP_H} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURSTWRAP_L} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURST_SIZE_H} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURST_SIZE_L} {117};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURST_TYPE_H} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURST_TYPE_L} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BYTE_CNT_H} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BYTE_CNT_L} {106};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ADDR_H} {99};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_POSTED} {101};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_READ} {103};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_EXCLUSIVE} {105};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DATA_H} {31};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_SRC_ID_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_SRC_ID_L} {126};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DEST_ID_H} {129};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DEST_ID_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_THREAD_ID_H} {130};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_THREAD_ID_L} {130};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_CACHE_H} {137};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_CACHE_L} {134};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DATA_SIDEBAND_H} {123};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DATA_SIDEBAND_L} {123};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_QOS_H} {125};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_QOS_L} {125};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ADDR_SIDEBAND_H} {122};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ADDR_SIDEBAND_L} {122};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_RESPONSE_STATUS_H} {139};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_RESPONSE_STATUS_L} {138};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ORI_BURST_SIZE_L} {140};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ORI_BURST_SIZE_H} {142};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {ST_DATA_W} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;onchip_memory2_0_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000001000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {SUPPRESS_0_BYTEEN_RSP} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {ID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {CACHE_VALUE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_dma_rd_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_PROTECTION_H} {241};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_PROTECTION_L} {239};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_POSTED} {209};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_READ} {211};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_SRC_ID_H} {235};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_SRC_ID_L} {234};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DEST_ID_H} {237};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DEST_ID_L} {236};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_THREAD_ID_H} {238};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_THREAD_ID_L} {238};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_CACHE_H} {245};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_CACHE_L} {242};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DATA_SIDEBAND_H} {231};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DATA_SIDEBAND_L} {231};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_QOS_H} {233};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_QOS_L} {233};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ADDR_SIDEBAND_H} {230};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ADDR_SIDEBAND_L} {230};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {AV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;onchip_memory2_0_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000001000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
 &lt;slave
   id=&quot;2&quot;
   name=&quot;pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000004000&quot;
   end=&quot;0x00000000000006000&quot;
   responds=&quot;0&quot;
   user_default=&quot;0&quot; /&gt;
 &lt;slave
   id=&quot;1&quot;
   name=&quot;pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000002000&quot;
   end=&quot;0x00000000000004000&quot;
   responds=&quot;0&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {SUPPRESS_0_BYTEEN_RSP} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {ID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {USE_WRITERESPONSE} {0};add_instance {onchip_memory2_0_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DATA_H} {127};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTEEN_H} {143};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTEEN_L} {128};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ADDR_H} {207};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ADDR_L} {144};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_POSTED} {209};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_READ} {211};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_SRC_ID_H} {235};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_SRC_ID_L} {234};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DEST_ID_H} {237};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DEST_ID_L} {236};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_PROTECTION_H} {241};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_PROTECTION_L} {239};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {onchip_memory2_0_s1_agent} {ST_CHANNEL_W} {3};set_instance_parameter_value {onchip_memory2_0_s1_agent} {ST_DATA_W} {251};set_instance_parameter_value {onchip_memory2_0_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {AVS_BURSTCOUNT_W} {5};set_instance_parameter_value {onchip_memory2_0_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {onchip_memory2_0_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent} {MAX_BYTE_CNT} {16};set_instance_parameter_value {onchip_memory2_0_s1_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent} {ID} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {USE_WRITERESPONSE} {0};add_instance {onchip_memory2_0_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {252};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BEGIN_BURST} {376};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_TRANS_POSTED} {353};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_TRANS_READ} {355};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_TRANS_LOCK} {356};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_SRC_ID_H} {379};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_SRC_ID_L} {378};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_DEST_ID_H} {381};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_DEST_ID_L} {380};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_PROTECTION_H} {385};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_PROTECTION_L} {383};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {AVS_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {MAX_BYTE_CNT} {512};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {ID} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {396};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {BITS_PER_SYMBOL} {258};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {FIFO_DEPTH} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {EMPTY_LATENCY} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BEGIN_BURST} {376};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_TRANS_POSTED} {353};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_TRANS_READ} {355};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_TRANS_LOCK} {356};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_SRC_ID_H} {379};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_SRC_ID_L} {378};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_DEST_ID_H} {381};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_DEST_ID_L} {380};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_PROTECTION_H} {385};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_PROTECTION_L} {383};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {AVS_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {MAX_BYTE_CNT} {512};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {ID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {396};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {BITS_PER_SYMBOL} {258};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {FIFO_DEPTH} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {EMPTY_LATENCY} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {0 };set_instance_parameter_value {router} {CHANNEL_ID} {1 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 };set_instance_parameter_value {router} {END_ADDRESS} {0x1000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {99};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {133};set_instance_parameter_value {router} {PKT_PROTECTION_L} {131};set_instance_parameter_value {router} {PKT_DEST_ID_H} {129};set_instance_parameter_value {router} {PKT_DEST_ID_L} {128};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {router} {PKT_TRANS_READ} {103};set_instance_parameter_value {router} {ST_DATA_W} {143};set_instance_parameter_value {router} {ST_CHANNEL_W} {3};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {0 1 2 };set_instance_parameter_value {router_001} {CHANNEL_ID} {001 100 010 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both write write };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 0x2000 0x4000 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x1000 0x4000 0x6000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {207};set_instance_parameter_value {router_001} {PKT_ADDR_L} {144};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {241};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {239};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {237};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {236};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {211};set_instance_parameter_value {router_001} {ST_DATA_W} {251};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {3};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_002} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both write };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {207};set_instance_parameter_value {router_002} {PKT_ADDR_L} {144};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {241};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {239};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {237};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {236};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {211};set_instance_parameter_value {router_002} {ST_DATA_W} {251};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {3};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {1 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {write };set_instance_parameter_value {router_003} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {351};set_instance_parameter_value {router_003} {PKT_ADDR_L} {288};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {385};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {383};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {381};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {380};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {355};set_instance_parameter_value {router_003} {ST_DATA_W} {395};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {3};set_instance_parameter_value {router_003} {DECODER_TYPE} {1};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {1};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {1 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {write };set_instance_parameter_value {router_004} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {351};set_instance_parameter_value {router_004} {PKT_ADDR_L} {288};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {385};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {383};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {381};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {380};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {355};set_instance_parameter_value {router_004} {ST_DATA_W} {395};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {3};set_instance_parameter_value {router_004} {DECODER_TYPE} {1};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {1};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {onchip_memory2_0_s1_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_ADDR_H} {207};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_ADDR_L} {144};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BYTEEN_H} {143};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BYTEEN_L} {128};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURST_TYPE_H} {229};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURST_TYPE_L} {228};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_TRANS_READ} {211};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {ST_DATA_W} {251};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {OUT_BYTE_CNT_H} {218};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {OUT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {BURSTWRAP_CONST_MASK} {1};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {BURSTWRAP_CONST_VALUE} {1};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BEGIN_BURST} {376};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_TRANS_READ} {355};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {OUT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {OUT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {BURSTWRAP_CONST_MASK} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {BURSTWRAP_CONST_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BEGIN_BURST} {376};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_TRANS_READ} {355};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {OUT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {OUT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {BURSTWRAP_CONST_MASK} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {BURSTWRAP_CONST_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {143};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {3};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {251};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {3};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {3};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {251};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {3};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {395};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {3};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {356};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {395};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {3};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {356};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {251};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {3};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {395};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {3};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {395};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {3};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {143};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {3};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {251};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {3};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {3};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_ADDR_H} {99};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_ADDR_L} {36};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_DATA_H} {31};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BYTEEN_H} {35};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BYTEEN_L} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {106};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {117};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {139};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {138};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {105};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {140};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {142};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_ST_DATA_W} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {357};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {357};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_ADDR_H} {207};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_ADDR_L} {144};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_DATA_H} {127};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BYTEEN_H} {143};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BYTEEN_L} {128};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {224};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_ST_DATA_W} {251};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_ADDR_H} {99};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_ADDR_L} {36};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_DATA_H} {31};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {115};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {106};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {119};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {117};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {139};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {138};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {105};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {121};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {120};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {140};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {142};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_ST_DATA_W} {143};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {1};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {357};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {357};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {onchip_memory2_0_reset1_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {onchip_memory2_0_reset1_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {onchip_memory2_0_reset1_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {onchip_memory2_0_reset1_reset_bridge} {NUM_RESET_OUTPUTS} {1};add_instance {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {EXPLICIT_CLOCK_RATE} {125000000};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {pcie_256_hip_avmm_0_Rxm_BAR2_translator.avalon_universal_master_0} {pcie_256_hip_avmm_0_Rxm_BAR2_agent.av} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_Rxm_BAR2_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_Rxm_BAR2_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_Rxm_BAR2_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {pcie_256_hip_avmm_0_Rxm_BAR2_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/pcie_256_hip_avmm_0_Rxm_BAR2_agent.rp} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_dma_rd_master_translator.avalon_universal_master_0} {pcie_256_hip_avmm_0_dma_rd_master_agent.av} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_rd_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_rd_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_rd_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_001.src} {pcie_256_hip_avmm_0_dma_rd_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/pcie_256_hip_avmm_0_dma_rd_master_agent.rp} {qsys_mm.response};add_connection {onchip_memory2_0_s1_agent.m0} {onchip_memory2_0_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_memory2_0_s1_agent.m0/onchip_memory2_0_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_memory2_0_s1_agent.m0/onchip_memory2_0_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_memory2_0_s1_agent.m0/onchip_memory2_0_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_memory2_0_s1_agent.rf_source} {onchip_memory2_0_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_memory2_0_s1_agent_rsp_fifo.out} {onchip_memory2_0_s1_agent.rf_sink} {avalon_streaming};add_connection {onchip_memory2_0_s1_agent.rdata_fifo_src} {onchip_memory2_0_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent.m0} {pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent.m0/pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent.m0/pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent.m0/pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent.rf_source} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo.out} {pcie_256_hip_avmm_0_wr_dts_slave_agent.rf_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent.rdata_fifo_src} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo.in} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo.out} {pcie_256_hip_avmm_0_wr_dts_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent.m0} {pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent.m0/pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent.m0/pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent.m0/pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent.rf_source} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo.out} {pcie_256_hip_avmm_0_rd_dts_slave_agent.rf_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent.rdata_fifo_src} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo.in} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo.out} {pcie_256_hip_avmm_0_rd_dts_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_Rxm_BAR2_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_Rxm_BAR2_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_dma_rd_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_dma_rd_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {onchip_memory2_0_s1_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s1_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent.rp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_wr_dts_slave_agent.rp/router_003.sink} {qsys_mm.response};add_connection {router_003.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent.rp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_rd_dts_slave_agent.rp/router_004.sink} {qsys_mm.response};add_connection {router_004.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {cmd_mux.src} {onchip_memory2_0_s1_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/onchip_memory2_0_s1_burst_adapter.sink0} {qsys_mm.command};add_connection {onchip_memory2_0_s1_burst_adapter.source0} {onchip_memory2_0_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s1_burst_adapter.source0/onchip_memory2_0_s1_agent.cp} {qsys_mm.command};add_connection {cmd_mux_001.src} {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.sink0} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.source0} {pcie_256_hip_avmm_0_wr_dts_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.source0/pcie_256_hip_avmm_0_wr_dts_slave_agent.cp} {qsys_mm.command};add_connection {cmd_mux_002.src} {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.sink0} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.source0} {pcie_256_hip_avmm_0_rd_dts_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.source0/pcie_256_hip_avmm_0_rd_dts_slave_agent.cp} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux.sink1} {qsys_mm.command};add_connection {rsp_demux.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {cmd_demux.src0} {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.src} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.src/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src1} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.src} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.src/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src2} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src2/pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.src} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.src/cmd_mux_002.sink0} {qsys_mm.command};add_connection {rsp_demux.src0} {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.sink} {qsys_mm.response};add_connection {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.src} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.src/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.sink} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.src} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.src/rsp_mux_001.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.sink} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.src} {rsp_mux_001.sink2} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.src/rsp_mux_001.sink2} {qsys_mm.response};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Rxm_BAR2_translator.reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_rd_master_translator.reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {onchip_memory2_0_s1_translator.reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_translator.reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_translator.reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Rxm_BAR2_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_rd_master_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {onchip_memory2_0_s1_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {onchip_memory2_0_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {onchip_memory2_0_s1_burst_adapter.cr0_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.cr0_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.cr0_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Rxm_BAR2_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_rd_master_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s1_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Rxm_BAR2_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_rd_master_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s1_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s1_agent_rsp_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s1_burst_adapter.cr0} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.cr0} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.cr0} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_reset1_reset_bridge.clk} {clock};add_interface {pcie_256_hip_avmm_0_coreclkout} {clock} {slave};set_interface_property {pcie_256_hip_avmm_0_coreclkout} {EXPORT_OF} {pcie_256_hip_avmm_0_coreclkout_clock_bridge.in_clk};add_interface {onchip_memory2_0_reset1_reset_bridge_in_reset} {reset} {slave};set_interface_property {onchip_memory2_0_reset1_reset_bridge_in_reset} {EXPORT_OF} {onchip_memory2_0_reset1_reset_bridge.in_reset};add_interface {pcie_256_hip_avmm_0_dma_rd_master} {avalon} {slave};set_interface_property {pcie_256_hip_avmm_0_dma_rd_master} {EXPORT_OF} {pcie_256_hip_avmm_0_dma_rd_master_translator.avalon_anti_master_0};add_interface {pcie_256_hip_avmm_0_Rxm_BAR2} {avalon} {slave};set_interface_property {pcie_256_hip_avmm_0_Rxm_BAR2} {EXPORT_OF} {pcie_256_hip_avmm_0_Rxm_BAR2_translator.avalon_anti_master_0};add_interface {onchip_memory2_0_s1} {avalon} {master};set_interface_property {onchip_memory2_0_s1} {EXPORT_OF} {onchip_memory2_0_s1_translator.avalon_anti_slave_0};add_interface {pcie_256_hip_avmm_0_rd_dts_slave} {avalon} {master};set_interface_property {pcie_256_hip_avmm_0_rd_dts_slave} {EXPORT_OF} {pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_anti_slave_0};add_interface {pcie_256_hip_avmm_0_wr_dts_slave} {avalon} {master};set_interface_property {pcie_256_hip_avmm_0_wr_dts_slave} {EXPORT_OF} {pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.onchip_memory2_0.s1} {0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.Rxm_BAR2} {0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.dma_rd_master} {1};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.rd_dts_slave} {1};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.wr_dts_slave} {2};(altera_merlin_master_translator:14.0:AUTO_CLK_CLOCK_RATE=125000000,AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=64,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_translator:14.0:AUTO_CLK_CLOCK_RATE=125000000,AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=64,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=6,AV_BYTEENABLE_W=16,AV_CONSTANT_BURST_BEHAVIOR=1,AV_DATA_HOLD=0,AV_DATA_W=128,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=16,AV_WRITE_WAIT=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=10,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=1,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:14.0:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=8,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=16,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=128,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=16,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=125000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=5,UAV_BYTEENABLE_W=16,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=128,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:14.0:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=8,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=5,AV_BYTEENABLE_W=32,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=256,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=32,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=125000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=10,UAV_BYTEENABLE_W=32,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=256,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=1,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:14.0:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=8,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=5,AV_BYTEENABLE_W=32,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=256,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=32,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=125000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=10,UAV_BYTEENABLE_W=32,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=256,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=1,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_agent:14.0:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;onchip_memory2_0_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000001000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
,AUTO_CLK_CLOCK_RATE=125000000,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=1,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=122,PKT_ADDR_SIDEBAND_L=122,PKT_BEGIN_BURST=124,PKT_BURSTWRAP_H=116,PKT_BURSTWRAP_L=116,PKT_BURST_SIZE_H=119,PKT_BURST_SIZE_L=117,PKT_BURST_TYPE_H=121,PKT_BURST_TYPE_L=120,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=115,PKT_BYTE_CNT_L=106,PKT_CACHE_H=137,PKT_CACHE_L=134,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=123,PKT_DATA_SIDEBAND_L=123,PKT_DEST_ID_H=129,PKT_DEST_ID_L=128,PKT_ORI_BURST_SIZE_H=142,PKT_ORI_BURST_SIZE_L=140,PKT_PROTECTION_H=133,PKT_PROTECTION_L=131,PKT_QOS_H=125,PKT_QOS_L=125,PKT_RESPONSE_STATUS_H=139,PKT_RESPONSE_STATUS_L=138,PKT_SRC_ID_H=127,PKT_SRC_ID_L=126,PKT_THREAD_ID_H=130,PKT_THREAD_ID_L=130,PKT_TRANS_COMPRESSED_READ=100,PKT_TRANS_EXCLUSIVE=105,PKT_TRANS_LOCK=104,PKT_TRANS_POSTED=101,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=3,ST_DATA_W=143,SUPPRESS_0_BYTEEN_RSP=1,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:14.0:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;onchip_memory2_0_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000001000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
 &lt;slave
   id=&quot;2&quot;
   name=&quot;pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000004000&quot;
   end=&quot;0x00000000000006000&quot;
   responds=&quot;0&quot;
   user_default=&quot;0&quot; /&gt;
 &lt;slave
   id=&quot;1&quot;
   name=&quot;pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000002000&quot;
   end=&quot;0x00000000000004000&quot;
   responds=&quot;0&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
,AUTO_CLK_CLOCK_RATE=125000000,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=10,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=1,CACHE_VALUE=0,ID=1,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_ADDR_SIDEBAND_H=230,PKT_ADDR_SIDEBAND_L=230,PKT_BEGIN_BURST=232,PKT_BURSTWRAP_H=224,PKT_BURSTWRAP_L=224,PKT_BURST_SIZE_H=227,PKT_BURST_SIZE_L=225,PKT_BURST_TYPE_H=229,PKT_BURST_TYPE_L=228,PKT_BYTEEN_H=143,PKT_BYTEEN_L=128,PKT_BYTE_CNT_H=223,PKT_BYTE_CNT_L=214,PKT_CACHE_H=245,PKT_CACHE_L=242,PKT_DATA_H=127,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=231,PKT_DATA_SIDEBAND_L=231,PKT_DEST_ID_H=237,PKT_DEST_ID_L=236,PKT_ORI_BURST_SIZE_H=250,PKT_ORI_BURST_SIZE_L=248,PKT_PROTECTION_H=241,PKT_PROTECTION_L=239,PKT_QOS_H=233,PKT_QOS_L=233,PKT_RESPONSE_STATUS_H=247,PKT_RESPONSE_STATUS_L=246,PKT_SRC_ID_H=235,PKT_SRC_ID_L=234,PKT_THREAD_ID_H=238,PKT_THREAD_ID_L=238,PKT_TRANS_COMPRESSED_READ=208,PKT_TRANS_EXCLUSIVE=213,PKT_TRANS_LOCK=212,PKT_TRANS_POSTED=209,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=3,ST_DATA_W=251,SUPPRESS_0_BYTEEN_RSP=1,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_slave_agent:14.0:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=5,AV_LINEWRAPBURSTS=0,ID=0,MAX_BURSTWRAP=1,MAX_BYTE_CNT=16,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_BEGIN_BURST=232,PKT_BURSTWRAP_H=224,PKT_BURSTWRAP_L=224,PKT_BURST_SIZE_H=227,PKT_BURST_SIZE_L=225,PKT_BYTEEN_H=143,PKT_BYTEEN_L=128,PKT_BYTE_CNT_H=223,PKT_BYTE_CNT_L=214,PKT_DATA_H=127,PKT_DATA_L=0,PKT_DEST_ID_H=237,PKT_DEST_ID_L=236,PKT_ORI_BURST_SIZE_H=250,PKT_ORI_BURST_SIZE_L=248,PKT_PROTECTION_H=241,PKT_PROTECTION_L=239,PKT_RESPONSE_STATUS_H=247,PKT_RESPONSE_STATUS_L=246,PKT_SRC_ID_H=235,PKT_SRC_ID_L=234,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=208,PKT_TRANS_LOCK=212,PKT_TRANS_POSTED=209,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=3,ST_DATA_W=251,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:14.0:AUTO_DEVICE_FAMILY=Arria V,BITS_PER_SYMBOL=252,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:14.0:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=10,AV_LINEWRAPBURSTS=0,ID=2,MAX_BURSTWRAP=1,MAX_BYTE_CNT=512,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),PKT_ADDR_H=351,PKT_ADDR_L=288,PKT_BEGIN_BURST=376,PKT_BURSTWRAP_H=368,PKT_BURSTWRAP_L=368,PKT_BURST_SIZE_H=371,PKT_BURST_SIZE_L=369,PKT_BYTEEN_H=287,PKT_BYTEEN_L=256,PKT_BYTE_CNT_H=367,PKT_BYTE_CNT_L=358,PKT_DATA_H=255,PKT_DATA_L=0,PKT_DEST_ID_H=381,PKT_DEST_ID_L=380,PKT_ORI_BURST_SIZE_H=394,PKT_ORI_BURST_SIZE_L=392,PKT_PROTECTION_H=385,PKT_PROTECTION_L=383,PKT_RESPONSE_STATUS_H=391,PKT_RESPONSE_STATUS_L=390,PKT_SRC_ID_H=379,PKT_SRC_ID_L=378,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=352,PKT_TRANS_LOCK=356,PKT_TRANS_POSTED=353,PKT_TRANS_READ=355,PKT_TRANS_WRITE=354,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=3,ST_DATA_W=395,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:14.0:AUTO_DEVICE_FAMILY=Arria V,BITS_PER_SYMBOL=396,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_avalon_sc_fifo:14.0:AUTO_DEVICE_FAMILY=Arria V,BITS_PER_SYMBOL=258,CHANNEL_WIDTH=0,EMPTY_LATENCY=3,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=32,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=1,USE_PACKETS=0,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:14.0:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=10,AV_LINEWRAPBURSTS=0,ID=1,MAX_BURSTWRAP=1,MAX_BYTE_CNT=512,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),PKT_ADDR_H=351,PKT_ADDR_L=288,PKT_BEGIN_BURST=376,PKT_BURSTWRAP_H=368,PKT_BURSTWRAP_L=368,PKT_BURST_SIZE_H=371,PKT_BURST_SIZE_L=369,PKT_BYTEEN_H=287,PKT_BYTEEN_L=256,PKT_BYTE_CNT_H=367,PKT_BYTE_CNT_L=358,PKT_DATA_H=255,PKT_DATA_L=0,PKT_DEST_ID_H=381,PKT_DEST_ID_L=380,PKT_ORI_BURST_SIZE_H=394,PKT_ORI_BURST_SIZE_L=392,PKT_PROTECTION_H=385,PKT_PROTECTION_L=383,PKT_RESPONSE_STATUS_H=391,PKT_RESPONSE_STATUS_L=390,PKT_SRC_ID_H=379,PKT_SRC_ID_L=378,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=352,PKT_TRANS_LOCK=356,PKT_TRANS_POSTED=353,PKT_TRANS_READ=355,PKT_TRANS_WRITE=354,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=3,ST_DATA_W=395,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:14.0:AUTO_DEVICE_FAMILY=Arria V,BITS_PER_SYMBOL=396,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_avalon_sc_fifo:14.0:AUTO_DEVICE_FAMILY=Arria V,BITS_PER_SYMBOL=258,CHANNEL_WIDTH=0,EMPTY_LATENCY=3,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=32,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=1,USE_PACKETS=0,USE_STORE_FORWARD=0)(altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x1000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_DEST_ID_H=129,PKT_DEST_ID_L=128,PKT_PROTECTION_H=133,PKT_PROTECTION_L=131,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x1000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=3,ST_DATA_W=143,TYPE_OF_TRANSACTION=both)(altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=001,100,010,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,2,END_ADDRESS=0x1000,0x4000,0x6000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NON_SECURED_TAG=1,1,1,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_DEST_ID_H=237,PKT_DEST_ID_L=236,PKT_PROTECTION_H=241,PKT_PROTECTION_L=239,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,SECURED_RANGE_LIST=0,0,0,SECURED_RANGE_PAIRS=0,0,0,SLAVES_INFO=0:001:0x0:0x1000:both:1:0:0:1,1:100:0x2000:0x4000:write:1:0:0:1,2:010:0x4000:0x6000:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x2000,0x4000,ST_CHANNEL_W=3,ST_DATA_W=251,TYPE_OF_TRANSACTION=both,write,write)(altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_DEST_ID_H=237,PKT_DEST_ID_L=236,PKT_PROTECTION_H=241,PKT_PROTECTION_L=239,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=3,ST_DATA_W=251,TYPE_OF_TRANSACTION=both,write)(altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=1,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=1,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NON_SECURED_TAG=1,PKT_ADDR_H=351,PKT_ADDR_L=288,PKT_DEST_ID_H=381,PKT_DEST_ID_L=380,PKT_PROTECTION_H=385,PKT_PROTECTION_L=383,PKT_TRANS_READ=355,PKT_TRANS_WRITE=354,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=1:1:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=3,ST_DATA_W=395,TYPE_OF_TRANSACTION=write)(altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=1,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=1,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NON_SECURED_TAG=1,PKT_ADDR_H=351,PKT_ADDR_L=288,PKT_DEST_ID_H=381,PKT_DEST_ID_L=380,PKT_PROTECTION_H=385,PKT_PROTECTION_L=383,PKT_TRANS_READ=355,PKT_TRANS_WRITE=354,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=1:1:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=3,ST_DATA_W=395,TYPE_OF_TRANSACTION=write)(altera_merlin_burst_adapter:14.0:ADAPTER_VERSION=13.1,AUTO_CR0_CLOCK_RATE=125000000,BURSTWRAP_CONST_MASK=1,BURSTWRAP_CONST_VALUE=1,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=1,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=224,OUT_BYTE_CNT_H=218,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_BEGIN_BURST=232,PKT_BURSTWRAP_H=224,PKT_BURSTWRAP_L=224,PKT_BURST_SIZE_H=227,PKT_BURST_SIZE_L=225,PKT_BURST_TYPE_H=229,PKT_BURST_TYPE_L=228,PKT_BYTEEN_H=143,PKT_BYTEEN_L=128,PKT_BYTE_CNT_H=223,PKT_BYTE_CNT_L=214,PKT_TRANS_COMPRESSED_READ=208,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,ST_CHANNEL_W=3,ST_DATA_W=251)(altera_merlin_burst_adapter:14.0:ADAPTER_VERSION=13.1,AUTO_CR0_CLOCK_RATE=125000000,BURSTWRAP_CONST_MASK=1,BURSTWRAP_CONST_VALUE=1,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=1,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=368,OUT_BYTE_CNT_H=367,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=351,PKT_ADDR_L=288,PKT_BEGIN_BURST=376,PKT_BURSTWRAP_H=368,PKT_BURSTWRAP_L=368,PKT_BURST_SIZE_H=371,PKT_BURST_SIZE_L=369,PKT_BURST_TYPE_H=373,PKT_BURST_TYPE_L=372,PKT_BYTEEN_H=287,PKT_BYTEEN_L=256,PKT_BYTE_CNT_H=367,PKT_BYTE_CNT_L=358,PKT_TRANS_COMPRESSED_READ=352,PKT_TRANS_READ=355,PKT_TRANS_WRITE=354,ST_CHANNEL_W=3,ST_DATA_W=395)(altera_merlin_burst_adapter:14.0:ADAPTER_VERSION=13.1,AUTO_CR0_CLOCK_RATE=125000000,BURSTWRAP_CONST_MASK=1,BURSTWRAP_CONST_VALUE=1,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=1,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=368,OUT_BYTE_CNT_H=367,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=351,PKT_ADDR_L=288,PKT_BEGIN_BURST=376,PKT_BURSTWRAP_H=368,PKT_BURSTWRAP_L=368,PKT_BURST_SIZE_H=371,PKT_BURST_SIZE_L=369,PKT_BURST_TYPE_H=373,PKT_BURST_TYPE_L=372,PKT_BYTEEN_H=287,PKT_BYTEEN_L=256,PKT_BYTE_CNT_H=367,PKT_BYTE_CNT_L=358,PKT_TRANS_COMPRESSED_READ=352,PKT_TRANS_READ=355,PKT_TRANS_WRITE=354,ST_CHANNEL_W=3,ST_DATA_W=395)(altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=3,ST_DATA_W=143,VALID_WIDTH=1)(altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_OUTPUTS=3,ST_CHANNEL_W=3,ST_DATA_W=251,VALID_WIDTH=1)(altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=212,ST_CHANNEL_W=3,ST_DATA_W=251,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=356,ST_CHANNEL_W=3,ST_DATA_W=395,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=356,ST_CHANNEL_W=3,ST_DATA_W=395,USE_EXTERNAL_ARB=0)(altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_OUTPUTS=2,ST_CHANNEL_W=3,ST_DATA_W=251,VALID_WIDTH=1)(altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NUM_OUTPUTS=1,ST_CHANNEL_W=3,ST_DATA_W=395,VALID_WIDTH=1)(altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NUM_OUTPUTS=1,ST_CHANNEL_W=3,ST_DATA_W=395,VALID_WIDTH=1)(altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=104,ST_CHANNEL_W=3,ST_DATA_W=143,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_INPUTS=3,PIPELINE_ARB=0,PKT_TRANS_LOCK=212,ST_CHANNEL_W=3,ST_DATA_W=251,USE_EXTERNAL_ARB=0)(altera_merlin_width_adapter:14.0:AUTO_CLK_CLOCK_RATE=125000000,COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),IN_PKT_ADDR_H=99,IN_PKT_ADDR_L=36,IN_PKT_BURSTWRAP_H=116,IN_PKT_BURSTWRAP_L=116,IN_PKT_BURST_SIZE_H=119,IN_PKT_BURST_SIZE_L=117,IN_PKT_BURST_TYPE_H=121,IN_PKT_BURST_TYPE_L=120,IN_PKT_BYTEEN_H=35,IN_PKT_BYTEEN_L=32,IN_PKT_BYTE_CNT_H=115,IN_PKT_BYTE_CNT_L=106,IN_PKT_DATA_H=31,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=142,IN_PKT_ORI_BURST_SIZE_L=140,IN_PKT_RESPONSE_STATUS_H=139,IN_PKT_RESPONSE_STATUS_L=138,IN_PKT_TRANS_COMPRESSED_READ=100,IN_PKT_TRANS_EXCLUSIVE=105,IN_ST_DATA_W=143,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),OUT_PKT_ADDR_H=207,OUT_PKT_ADDR_L=144,OUT_PKT_BURST_SIZE_H=227,OUT_PKT_BURST_SIZE_L=225,OUT_PKT_BURST_TYPE_H=229,OUT_PKT_BURST_TYPE_L=228,OUT_PKT_BYTEEN_H=143,OUT_PKT_BYTEEN_L=128,OUT_PKT_BYTE_CNT_H=223,OUT_PKT_BYTE_CNT_L=214,OUT_PKT_DATA_H=127,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=250,OUT_PKT_ORI_BURST_SIZE_L=248,OUT_PKT_RESPONSE_STATUS_H=247,OUT_PKT_RESPONSE_STATUS_L=246,OUT_PKT_TRANS_COMPRESSED_READ=208,OUT_PKT_TRANS_EXCLUSIVE=213,OUT_ST_DATA_W=251,PACKING=1,RESPONSE_PATH=0,ST_CHANNEL_W=3)(altera_merlin_width_adapter:14.0:AUTO_CLK_CLOCK_RATE=125000000,COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),IN_PKT_ADDR_H=207,IN_PKT_ADDR_L=144,IN_PKT_BURSTWRAP_H=224,IN_PKT_BURSTWRAP_L=224,IN_PKT_BURST_SIZE_H=227,IN_PKT_BURST_SIZE_L=225,IN_PKT_BURST_TYPE_H=229,IN_PKT_BURST_TYPE_L=228,IN_PKT_BYTEEN_H=143,IN_PKT_BYTEEN_L=128,IN_PKT_BYTE_CNT_H=223,IN_PKT_BYTE_CNT_L=214,IN_PKT_DATA_H=127,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=250,IN_PKT_ORI_BURST_SIZE_L=248,IN_PKT_RESPONSE_STATUS_H=247,IN_PKT_RESPONSE_STATUS_L=246,IN_PKT_TRANS_COMPRESSED_READ=208,IN_PKT_TRANS_EXCLUSIVE=213,IN_ST_DATA_W=251,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),OUT_PKT_ADDR_H=351,OUT_PKT_ADDR_L=288,OUT_PKT_BURST_SIZE_H=371,OUT_PKT_BURST_SIZE_L=369,OUT_PKT_BURST_TYPE_H=373,OUT_PKT_BURST_TYPE_L=372,OUT_PKT_BYTEEN_H=287,OUT_PKT_BYTEEN_L=256,OUT_PKT_BYTE_CNT_H=367,OUT_PKT_BYTE_CNT_L=358,OUT_PKT_DATA_H=255,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=394,OUT_PKT_ORI_BURST_SIZE_L=392,OUT_PKT_RESPONSE_STATUS_H=391,OUT_PKT_RESPONSE_STATUS_L=390,OUT_PKT_TRANS_COMPRESSED_READ=352,OUT_PKT_TRANS_EXCLUSIVE=357,OUT_ST_DATA_W=395,PACKING=1,RESPONSE_PATH=0,ST_CHANNEL_W=3)(altera_merlin_width_adapter:14.0:AUTO_CLK_CLOCK_RATE=125000000,COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),IN_PKT_ADDR_H=207,IN_PKT_ADDR_L=144,IN_PKT_BURSTWRAP_H=224,IN_PKT_BURSTWRAP_L=224,IN_PKT_BURST_SIZE_H=227,IN_PKT_BURST_SIZE_L=225,IN_PKT_BURST_TYPE_H=229,IN_PKT_BURST_TYPE_L=228,IN_PKT_BYTEEN_H=143,IN_PKT_BYTEEN_L=128,IN_PKT_BYTE_CNT_H=223,IN_PKT_BYTE_CNT_L=214,IN_PKT_DATA_H=127,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=250,IN_PKT_ORI_BURST_SIZE_L=248,IN_PKT_RESPONSE_STATUS_H=247,IN_PKT_RESPONSE_STATUS_L=246,IN_PKT_TRANS_COMPRESSED_READ=208,IN_PKT_TRANS_EXCLUSIVE=213,IN_ST_DATA_W=251,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),OUT_PKT_ADDR_H=351,OUT_PKT_ADDR_L=288,OUT_PKT_BURST_SIZE_H=371,OUT_PKT_BURST_SIZE_L=369,OUT_PKT_BURST_TYPE_H=373,OUT_PKT_BURST_TYPE_L=372,OUT_PKT_BYTEEN_H=287,OUT_PKT_BYTEEN_L=256,OUT_PKT_BYTE_CNT_H=367,OUT_PKT_BYTE_CNT_L=358,OUT_PKT_DATA_H=255,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=394,OUT_PKT_ORI_BURST_SIZE_L=392,OUT_PKT_RESPONSE_STATUS_H=391,OUT_PKT_RESPONSE_STATUS_L=390,OUT_PKT_TRANS_COMPRESSED_READ=352,OUT_PKT_TRANS_EXCLUSIVE=357,OUT_ST_DATA_W=395,PACKING=1,RESPONSE_PATH=0,ST_CHANNEL_W=3)(altera_merlin_width_adapter:14.0:AUTO_CLK_CLOCK_RATE=125000000,COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),IN_PKT_ADDR_H=207,IN_PKT_ADDR_L=144,IN_PKT_BURSTWRAP_H=224,IN_PKT_BURSTWRAP_L=224,IN_PKT_BURST_SIZE_H=227,IN_PKT_BURST_SIZE_L=225,IN_PKT_BURST_TYPE_H=229,IN_PKT_BURST_TYPE_L=228,IN_PKT_BYTEEN_H=143,IN_PKT_BYTEEN_L=128,IN_PKT_BYTE_CNT_H=223,IN_PKT_BYTE_CNT_L=214,IN_PKT_DATA_H=127,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=250,IN_PKT_ORI_BURST_SIZE_L=248,IN_PKT_RESPONSE_STATUS_H=247,IN_PKT_RESPONSE_STATUS_L=246,IN_PKT_TRANS_COMPRESSED_READ=208,IN_PKT_TRANS_EXCLUSIVE=213,IN_ST_DATA_W=251,OPTIMIZE_FOR_RSP=1,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),OUT_PKT_ADDR_H=99,OUT_PKT_ADDR_L=36,OUT_PKT_BURST_SIZE_H=119,OUT_PKT_BURST_SIZE_L=117,OUT_PKT_BURST_TYPE_H=121,OUT_PKT_BURST_TYPE_L=120,OUT_PKT_BYTEEN_H=35,OUT_PKT_BYTEEN_L=32,OUT_PKT_BYTE_CNT_H=115,OUT_PKT_BYTE_CNT_L=106,OUT_PKT_DATA_H=31,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=142,OUT_PKT_ORI_BURST_SIZE_L=140,OUT_PKT_RESPONSE_STATUS_H=139,OUT_PKT_RESPONSE_STATUS_L=138,OUT_PKT_TRANS_COMPRESSED_READ=100,OUT_PKT_TRANS_EXCLUSIVE=105,OUT_ST_DATA_W=143,PACKING=1,RESPONSE_PATH=1,ST_CHANNEL_W=3)(altera_merlin_width_adapter:14.0:AUTO_CLK_CLOCK_RATE=125000000,COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),IN_PKT_ADDR_H=351,IN_PKT_ADDR_L=288,IN_PKT_BURSTWRAP_H=368,IN_PKT_BURSTWRAP_L=368,IN_PKT_BURST_SIZE_H=371,IN_PKT_BURST_SIZE_L=369,IN_PKT_BURST_TYPE_H=373,IN_PKT_BURST_TYPE_L=372,IN_PKT_BYTEEN_H=287,IN_PKT_BYTEEN_L=256,IN_PKT_BYTE_CNT_H=367,IN_PKT_BYTE_CNT_L=358,IN_PKT_DATA_H=255,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=394,IN_PKT_ORI_BURST_SIZE_L=392,IN_PKT_RESPONSE_STATUS_H=391,IN_PKT_RESPONSE_STATUS_L=390,IN_PKT_TRANS_COMPRESSED_READ=352,IN_PKT_TRANS_EXCLUSIVE=357,IN_ST_DATA_W=395,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),OUT_PKT_ADDR_H=207,OUT_PKT_ADDR_L=144,OUT_PKT_BURST_SIZE_H=227,OUT_PKT_BURST_SIZE_L=225,OUT_PKT_BURST_TYPE_H=229,OUT_PKT_BURST_TYPE_L=228,OUT_PKT_BYTEEN_H=143,OUT_PKT_BYTEEN_L=128,OUT_PKT_BYTE_CNT_H=223,OUT_PKT_BYTE_CNT_L=214,OUT_PKT_DATA_H=127,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=250,OUT_PKT_ORI_BURST_SIZE_L=248,OUT_PKT_RESPONSE_STATUS_H=247,OUT_PKT_RESPONSE_STATUS_L=246,OUT_PKT_TRANS_COMPRESSED_READ=208,OUT_PKT_TRANS_EXCLUSIVE=213,OUT_ST_DATA_W=251,PACKING=1,RESPONSE_PATH=1,ST_CHANNEL_W=3)(altera_merlin_width_adapter:14.0:AUTO_CLK_CLOCK_RATE=125000000,COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),IN_PKT_ADDR_H=351,IN_PKT_ADDR_L=288,IN_PKT_BURSTWRAP_H=368,IN_PKT_BURSTWRAP_L=368,IN_PKT_BURST_SIZE_H=371,IN_PKT_BURST_SIZE_L=369,IN_PKT_BURST_TYPE_H=373,IN_PKT_BURST_TYPE_L=372,IN_PKT_BYTEEN_H=287,IN_PKT_BYTEEN_L=256,IN_PKT_BYTE_CNT_H=367,IN_PKT_BYTE_CNT_L=358,IN_PKT_DATA_H=255,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=394,IN_PKT_ORI_BURST_SIZE_L=392,IN_PKT_RESPONSE_STATUS_H=391,IN_PKT_RESPONSE_STATUS_L=390,IN_PKT_TRANS_COMPRESSED_READ=352,IN_PKT_TRANS_EXCLUSIVE=357,IN_ST_DATA_W=395,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),OUT_PKT_ADDR_H=207,OUT_PKT_ADDR_L=144,OUT_PKT_BURST_SIZE_H=227,OUT_PKT_BURST_SIZE_L=225,OUT_PKT_BURST_TYPE_H=229,OUT_PKT_BURST_TYPE_L=228,OUT_PKT_BYTEEN_H=143,OUT_PKT_BYTEEN_L=128,OUT_PKT_BYTE_CNT_H=223,OUT_PKT_BYTE_CNT_L=214,OUT_PKT_DATA_H=127,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=250,OUT_PKT_ORI_BURST_SIZE_L=248,OUT_PKT_RESPONSE_STATUS_H=247,OUT_PKT_RESPONSE_STATUS_L=246,OUT_PKT_TRANS_COMPRESSED_READ=208,OUT_PKT_TRANS_EXCLUSIVE=213,OUT_ST_DATA_W=251,PACKING=1,RESPONSE_PATH=1,ST_CHANNEL_W=3)(altera_reset_bridge:14.0:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=125000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert)(altera_clock_bridge:14.0:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=125000000,NUM_CLOCK_OUTPUTS=1)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)"
   instancePathKey="top:.:mm_interconnect_1"
   kind="altera_mm_interconnect"
   version="14.0"
   name="top_mm_interconnect_1">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_DEVICE" value="5AGXFB3H4F35C5" />
  <parameter
     name="COMPOSE_CONTENTS"
     value="add_instance {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {altera_merlin_master_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_DATA_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_READDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_READ} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator} {AV_ALWAYSBURSTMAXBURST} {0};add_instance {pcie_256_hip_avmm_0_dma_rd_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_DATA_W} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_BURSTCOUNT_W} {6};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_BYTEENABLE_W} {16};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {UAV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_READDATA} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_READ} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_SYMBOLS_PER_WORD} {16};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};add_instance {onchip_memory2_0_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_DATA_W} {128};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_DATA_W} {128};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_BYTEENABLE_W} {16};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_BYTEENABLE_W} {16};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_BURSTCOUNT_W} {5};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_READ} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_SYMBOLS_PER_WORD} {16};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_memory2_0_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_DATA_W} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_DATA_W} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_BURSTCOUNT_W} {5};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_BYTEENABLE_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_BYTEENABLE_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_READDATA} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_READ} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_SYMBOLS_PER_WORD} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_DATA_W} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_DATA_W} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_BURSTCOUNT_W} {5};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_BYTEENABLE_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_BYTEENABLE_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_READDATA} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_READ} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_SYMBOLS_PER_WORD} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {altera_merlin_master_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_PROTECTION_H} {133};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_PROTECTION_L} {131};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BEGIN_BURST} {124};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURSTWRAP_H} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURSTWRAP_L} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURST_SIZE_H} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURST_SIZE_L} {117};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURST_TYPE_H} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BURST_TYPE_L} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BYTE_CNT_H} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BYTE_CNT_L} {106};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ADDR_H} {99};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_POSTED} {101};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_READ} {103};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_TRANS_EXCLUSIVE} {105};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DATA_H} {31};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_SRC_ID_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_SRC_ID_L} {126};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DEST_ID_H} {129};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DEST_ID_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_THREAD_ID_H} {130};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_THREAD_ID_L} {130};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_CACHE_H} {137};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_CACHE_L} {134};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DATA_SIDEBAND_H} {123};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_DATA_SIDEBAND_L} {123};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_QOS_H} {125};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_QOS_L} {125};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ADDR_SIDEBAND_H} {122};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ADDR_SIDEBAND_L} {122};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_RESPONSE_STATUS_H} {139};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_RESPONSE_STATUS_L} {138};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ORI_BURST_SIZE_L} {140};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {PKT_ORI_BURST_SIZE_H} {142};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {ST_DATA_W} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;onchip_memory2_0_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000001000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {SUPPRESS_0_BYTEEN_RSP} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {ID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {CACHE_VALUE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_dma_rd_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_PROTECTION_H} {241};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_PROTECTION_L} {239};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_POSTED} {209};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_READ} {211};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_SRC_ID_H} {235};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_SRC_ID_L} {234};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DEST_ID_H} {237};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DEST_ID_L} {236};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_THREAD_ID_H} {238};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_THREAD_ID_L} {238};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_CACHE_H} {245};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_CACHE_L} {242};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DATA_SIDEBAND_H} {231};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_DATA_SIDEBAND_L} {231};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_QOS_H} {233};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_QOS_L} {233};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ADDR_SIDEBAND_H} {230};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ADDR_SIDEBAND_L} {230};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {AV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;onchip_memory2_0_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000001000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
 &lt;slave
   id=&quot;2&quot;
   name=&quot;pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000004000&quot;
   end=&quot;0x00000000000006000&quot;
   responds=&quot;0&quot;
   user_default=&quot;0&quot; /&gt;
 &lt;slave
   id=&quot;1&quot;
   name=&quot;pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000002000&quot;
   end=&quot;0x00000000000004000&quot;
   responds=&quot;0&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {SUPPRESS_0_BYTEEN_RSP} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {ID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_agent} {USE_WRITERESPONSE} {0};add_instance {onchip_memory2_0_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DATA_H} {127};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTEEN_H} {143};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTEEN_L} {128};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ADDR_H} {207};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ADDR_L} {144};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_POSTED} {209};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_READ} {211};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_SRC_ID_H} {235};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_SRC_ID_L} {234};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DEST_ID_H} {237};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DEST_ID_L} {236};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_PROTECTION_H} {241};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_PROTECTION_L} {239};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {onchip_memory2_0_s1_agent} {ST_CHANNEL_W} {3};set_instance_parameter_value {onchip_memory2_0_s1_agent} {ST_DATA_W} {251};set_instance_parameter_value {onchip_memory2_0_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {AVS_BURSTCOUNT_W} {5};set_instance_parameter_value {onchip_memory2_0_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {onchip_memory2_0_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent} {MAX_BYTE_CNT} {16};set_instance_parameter_value {onchip_memory2_0_s1_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent} {ID} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {USE_WRITERESPONSE} {0};add_instance {onchip_memory2_0_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {252};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BEGIN_BURST} {376};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_TRANS_POSTED} {353};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_TRANS_READ} {355};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_TRANS_LOCK} {356};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_SRC_ID_H} {379};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_SRC_ID_L} {378};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_DEST_ID_H} {381};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_DEST_ID_L} {380};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_PROTECTION_H} {385};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_PROTECTION_L} {383};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {AVS_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {MAX_BYTE_CNT} {512};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {ID} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {396};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {BITS_PER_SYMBOL} {258};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {FIFO_DEPTH} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {EMPTY_LATENCY} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BEGIN_BURST} {376};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_TRANS_POSTED} {353};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_TRANS_READ} {355};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_TRANS_LOCK} {356};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_SRC_ID_H} {379};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_SRC_ID_L} {378};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_DEST_ID_H} {381};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_DEST_ID_L} {380};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_PROTECTION_H} {385};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_PROTECTION_L} {383};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {AVS_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {MAX_BYTE_CNT} {512};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {ID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {396};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {BITS_PER_SYMBOL} {258};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {FIFO_DEPTH} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {EMPTY_LATENCY} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {0 };set_instance_parameter_value {router} {CHANNEL_ID} {1 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 };set_instance_parameter_value {router} {END_ADDRESS} {0x1000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {99};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {133};set_instance_parameter_value {router} {PKT_PROTECTION_L} {131};set_instance_parameter_value {router} {PKT_DEST_ID_H} {129};set_instance_parameter_value {router} {PKT_DEST_ID_L} {128};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {router} {PKT_TRANS_READ} {103};set_instance_parameter_value {router} {ST_DATA_W} {143};set_instance_parameter_value {router} {ST_CHANNEL_W} {3};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {0 1 2 };set_instance_parameter_value {router_001} {CHANNEL_ID} {001 100 010 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both write write };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 0x2000 0x4000 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x1000 0x4000 0x6000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {207};set_instance_parameter_value {router_001} {PKT_ADDR_L} {144};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {241};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {239};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {237};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {236};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {211};set_instance_parameter_value {router_001} {ST_DATA_W} {251};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {3};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_002} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both write };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {207};set_instance_parameter_value {router_002} {PKT_ADDR_L} {144};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {241};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {239};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {237};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {236};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {211};set_instance_parameter_value {router_002} {ST_DATA_W} {251};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {3};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {1 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {write };set_instance_parameter_value {router_003} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {351};set_instance_parameter_value {router_003} {PKT_ADDR_L} {288};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {385};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {383};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {381};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {380};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {355};set_instance_parameter_value {router_003} {ST_DATA_W} {395};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {3};set_instance_parameter_value {router_003} {DECODER_TYPE} {1};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {1};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {1 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {write };set_instance_parameter_value {router_004} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {351};set_instance_parameter_value {router_004} {PKT_ADDR_L} {288};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {385};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {383};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {381};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {380};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {355};set_instance_parameter_value {router_004} {ST_DATA_W} {395};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {3};set_instance_parameter_value {router_004} {DECODER_TYPE} {1};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {1};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {onchip_memory2_0_s1_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_ADDR_H} {207};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_ADDR_L} {144};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BYTEEN_H} {143};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BYTEEN_L} {128};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURST_TYPE_H} {229};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURST_TYPE_L} {228};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PKT_TRANS_READ} {211};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {ST_DATA_W} {251};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {OUT_BYTE_CNT_H} {218};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {OUT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {BURSTWRAP_CONST_MASK} {1};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {BURSTWRAP_CONST_VALUE} {1};set_instance_parameter_value {onchip_memory2_0_s1_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BEGIN_BURST} {376};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PKT_TRANS_READ} {355};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {OUT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {OUT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {BURSTWRAP_CONST_MASK} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {BURSTWRAP_CONST_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BEGIN_BURST} {376};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_TRANS_WRITE} {354};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PKT_TRANS_READ} {355};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {OUT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {OUT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {BURSTWRAP_CONST_MASK} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {BURSTWRAP_CONST_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {143};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {3};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {251};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {3};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {3};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {251};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {3};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {395};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {3};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {356};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {395};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {3};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {356};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {251};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {3};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {395};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {3};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {395};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {3};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {143};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {3};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {251};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {3};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {3};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_ADDR_H} {99};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_ADDR_L} {36};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_DATA_H} {31};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BYTEEN_H} {35};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BYTEEN_L} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {106};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {117};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {139};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {138};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {105};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {140};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {142};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_ST_DATA_W} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {357};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {357};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_ADDR_H} {207};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_ADDR_L} {144};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_DATA_H} {127};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BYTEEN_H} {143};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BYTEEN_L} {128};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {224};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_ST_DATA_W} {251};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_ADDR_H} {99};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_ADDR_L} {36};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_DATA_H} {31};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {115};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {106};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {119};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {117};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {139};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {138};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {105};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {121};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {120};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {140};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {142};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_ST_DATA_W} {143};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {1};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {357};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ADDR_H} {351};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ADDR_L} {288};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_DATA_H} {255};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTEEN_H} {287};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTEEN_L} {256};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {367};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {358};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {352};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {368};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {371};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {369};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {391};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {390};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {357};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {373};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {372};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {392};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {394};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_ST_DATA_W} {395};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {247};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {250};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_ST_DATA_W} {251};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {ST_CHANNEL_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {onchip_memory2_0_reset1_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {onchip_memory2_0_reset1_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {onchip_memory2_0_reset1_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {onchip_memory2_0_reset1_reset_bridge} {NUM_RESET_OUTPUTS} {1};add_instance {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {EXPLICIT_CLOCK_RATE} {125000000};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {pcie_256_hip_avmm_0_Rxm_BAR2_translator.avalon_universal_master_0} {pcie_256_hip_avmm_0_Rxm_BAR2_agent.av} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_Rxm_BAR2_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_Rxm_BAR2_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_Rxm_BAR2_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_Rxm_BAR2_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {pcie_256_hip_avmm_0_Rxm_BAR2_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/pcie_256_hip_avmm_0_Rxm_BAR2_agent.rp} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_dma_rd_master_translator.avalon_universal_master_0} {pcie_256_hip_avmm_0_dma_rd_master_agent.av} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_rd_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_rd_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_rd_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_rd_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_001.src} {pcie_256_hip_avmm_0_dma_rd_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/pcie_256_hip_avmm_0_dma_rd_master_agent.rp} {qsys_mm.response};add_connection {onchip_memory2_0_s1_agent.m0} {onchip_memory2_0_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_memory2_0_s1_agent.m0/onchip_memory2_0_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_memory2_0_s1_agent.m0/onchip_memory2_0_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_memory2_0_s1_agent.m0/onchip_memory2_0_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_memory2_0_s1_agent.rf_source} {onchip_memory2_0_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_memory2_0_s1_agent_rsp_fifo.out} {onchip_memory2_0_s1_agent.rf_sink} {avalon_streaming};add_connection {onchip_memory2_0_s1_agent.rdata_fifo_src} {onchip_memory2_0_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent.m0} {pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent.m0/pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent.m0/pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dts_slave_agent.m0/pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent.rf_source} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo.out} {pcie_256_hip_avmm_0_wr_dts_slave_agent.rf_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent.rdata_fifo_src} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo.in} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo.out} {pcie_256_hip_avmm_0_wr_dts_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent.m0} {pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent.m0/pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent.m0/pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dts_slave_agent.m0/pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent.rf_source} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo.out} {pcie_256_hip_avmm_0_rd_dts_slave_agent.rf_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent.rdata_fifo_src} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo.in} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo.out} {pcie_256_hip_avmm_0_rd_dts_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_Rxm_BAR2_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_Rxm_BAR2_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_dma_rd_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_dma_rd_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {onchip_memory2_0_s1_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s1_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_agent.rp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_wr_dts_slave_agent.rp/router_003.sink} {qsys_mm.response};add_connection {router_003.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_agent.rp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_rd_dts_slave_agent.rp/router_004.sink} {qsys_mm.response};add_connection {router_004.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {cmd_mux.src} {onchip_memory2_0_s1_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/onchip_memory2_0_s1_burst_adapter.sink0} {qsys_mm.command};add_connection {onchip_memory2_0_s1_burst_adapter.source0} {onchip_memory2_0_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s1_burst_adapter.source0/onchip_memory2_0_s1_agent.cp} {qsys_mm.command};add_connection {cmd_mux_001.src} {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.sink0} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.source0} {pcie_256_hip_avmm_0_wr_dts_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.source0/pcie_256_hip_avmm_0_wr_dts_slave_agent.cp} {qsys_mm.command};add_connection {cmd_mux_002.src} {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.sink0} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.source0} {pcie_256_hip_avmm_0_rd_dts_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.source0/pcie_256_hip_avmm_0_rd_dts_slave_agent.cp} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux.sink1} {qsys_mm.command};add_connection {rsp_demux.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {cmd_demux.src0} {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.src} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.src/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src1} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.src} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.src/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src2} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src2/pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.src} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.src/cmd_mux_002.sink0} {qsys_mm.command};add_connection {rsp_demux.src0} {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.sink} {qsys_mm.response};add_connection {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.src} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.src/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.sink} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.src} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.src/rsp_mux_001.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.sink} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.src} {rsp_mux_001.sink2} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.src/rsp_mux_001.sink2} {qsys_mm.response};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Rxm_BAR2_translator.reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_rd_master_translator.reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {onchip_memory2_0_s1_translator.reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_translator.reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_translator.reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Rxm_BAR2_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_rd_master_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {onchip_memory2_0_s1_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {onchip_memory2_0_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {onchip_memory2_0_s1_burst_adapter.cr0_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.cr0_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.cr0_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.clk_reset} {reset};add_connection {onchip_memory2_0_reset1_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Rxm_BAR2_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_rd_master_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s1_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Rxm_BAR2_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_rd_master_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s1_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s1_agent_rsp_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s1_burst_adapter.cr0} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter.cr0} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter.cr0} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_reset1_reset_bridge.clk} {clock};add_interface {pcie_256_hip_avmm_0_coreclkout} {clock} {slave};set_interface_property {pcie_256_hip_avmm_0_coreclkout} {EXPORT_OF} {pcie_256_hip_avmm_0_coreclkout_clock_bridge.in_clk};add_interface {onchip_memory2_0_reset1_reset_bridge_in_reset} {reset} {slave};set_interface_property {onchip_memory2_0_reset1_reset_bridge_in_reset} {EXPORT_OF} {onchip_memory2_0_reset1_reset_bridge.in_reset};add_interface {pcie_256_hip_avmm_0_dma_rd_master} {avalon} {slave};set_interface_property {pcie_256_hip_avmm_0_dma_rd_master} {EXPORT_OF} {pcie_256_hip_avmm_0_dma_rd_master_translator.avalon_anti_master_0};add_interface {pcie_256_hip_avmm_0_Rxm_BAR2} {avalon} {slave};set_interface_property {pcie_256_hip_avmm_0_Rxm_BAR2} {EXPORT_OF} {pcie_256_hip_avmm_0_Rxm_BAR2_translator.avalon_anti_master_0};add_interface {onchip_memory2_0_s1} {avalon} {master};set_interface_property {onchip_memory2_0_s1} {EXPORT_OF} {onchip_memory2_0_s1_translator.avalon_anti_slave_0};add_interface {pcie_256_hip_avmm_0_rd_dts_slave} {avalon} {master};set_interface_property {pcie_256_hip_avmm_0_rd_dts_slave} {EXPORT_OF} {pcie_256_hip_avmm_0_rd_dts_slave_translator.avalon_anti_slave_0};add_interface {pcie_256_hip_avmm_0_wr_dts_slave} {avalon} {master};set_interface_property {pcie_256_hip_avmm_0_wr_dts_slave} {EXPORT_OF} {pcie_256_hip_avmm_0_wr_dts_slave_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.onchip_memory2_0.s1} {0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.Rxm_BAR2} {0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.dma_rd_master} {1};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.rd_dts_slave} {1};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.wr_dts_slave} {2};" />
  <generatedFiles>
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1.v"
       type="VERILOG" />
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       type="SYSTEM_VERILOG"
       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v"
       type="VERILOG" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_router.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_router_001.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_router_002.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_router_003.sv"
       type="SYSTEM_VERILOG"
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       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_address_alignment.sv"
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_incr_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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       type="SYSTEM_VERILOG"
       attributes="" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
       type="SYSTEM_VERILOG"
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_demux.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_demux_001.sv"
       type="SYSTEM_VERILOG" />
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       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_mux_001.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_demux.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_demux_001.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_mux.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
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       type="SYSTEM_VERILOG" />
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       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_width_adapter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
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       type="SYSTEM_VERILOG"
       attributes="" />
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       type="SYSTEM_VERILOG"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
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       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
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       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
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       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
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       path="/tools_archive/acds/14.0/200/linux64/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
  </childSourceFiles>
  <instantiator instantiator="top" as="mm_interconnect_1" />
  <messages>
   <message level="Debug" culprit="top">queue size: 4 starting:altera_mm_interconnect "submodules/top_mm_interconnect_1"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>41</b> modules, <b>127</b> connections]]></message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_1_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_1_router_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_1_router_002</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_1_router_003</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_1_router_003</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_1_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_1_cmd_demux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_1_cmd_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_1_cmd_mux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_1_cmd_mux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_1_rsp_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_1_rsp_demux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_1_rsp_demux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_1_rsp_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_1_rsp_mux_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Info" culprit="mm_interconnect_1"><![CDATA["<b>top</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 66 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_translator</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 64 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>onchip_memory2_0_s1_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 61 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 59 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>onchip_memory2_0_s1_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 58 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>onchip_memory2_0_s1_agent_rsp_fifo</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
   <message level="Debug" culprit="top">queue size: 51 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 50 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router_001"</message>
   <message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 49 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router_002"</message>
   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 48 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router_003"</message>
   <message level="Info" culprit="router_003"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_003</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 46 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>onchip_memory2_0_s1_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 43 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 42 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_cmd_demux_001"</message>
   <message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 41 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 40 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_cmd_mux_001"</message>
   <message level="Info" culprit="cmd_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_001</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 38 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_rsp_demux"</message>
   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 37 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_rsp_demux_001"</message>
   <message level="Info" culprit="rsp_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_001</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 35 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 34 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_rsp_mux_001"</message>
   <message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 33 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
   <message
       level="Info"
       culprit="pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_mm_interconnect:14.0:AUTO_DEVICE=5AGXFB3H4F35C5,AUTO_DEVICE_FAMILY=Arria V,COMPOSE_CONTENTS=add_instance {pcie_256_hip_avmm_0_dma_wr_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_DATA_W} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_BURSTCOUNT_W} {6};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_BYTEENABLE_W} {16};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {UAV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_READDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_READ} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_WRITE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_SYMBOLS_PER_WORD} {16};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};add_instance {onchip_memory2_0_s2_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_DATA_W} {128};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_DATA_W} {128};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_BYTEENABLE_W} {16};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_BYTEENABLE_W} {16};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_BURSTCOUNT_W} {5};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_READLATENCY} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_READ} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_SYMBOLS_PER_WORD} {16};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {pcie_256_hip_avmm_0_dma_wr_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_PROTECTION_H} {239};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_PROTECTION_L} {237};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_POSTED} {209};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_READ} {211};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_SRC_ID_H} {234};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_SRC_ID_L} {234};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DEST_ID_H} {235};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DEST_ID_L} {235};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_THREAD_ID_H} {236};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_THREAD_ID_L} {236};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_CACHE_H} {243};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_CACHE_L} {240};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DATA_SIDEBAND_H} {231};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DATA_SIDEBAND_L} {231};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_QOS_H} {233};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_QOS_L} {233};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ADDR_SIDEBAND_H} {230};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ADDR_SIDEBAND_L} {230};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_RESPONSE_STATUS_H} {245};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_RESPONSE_STATUS_L} {244};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ORI_BURST_SIZE_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ORI_BURST_SIZE_H} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {ST_DATA_W} {249};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {ST_CHANNEL_W} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {AV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;onchip_memory2_0_s2_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000001000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {ID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {USE_WRITERESPONSE} {0};add_instance {onchip_memory2_0_s2_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_DATA_H} {127};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BYTEEN_H} {143};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BYTEEN_L} {128};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_ADDR_H} {207};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_ADDR_L} {144};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_TRANS_POSTED} {209};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_TRANS_READ} {211};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_SRC_ID_H} {234};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_SRC_ID_L} {234};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_DEST_ID_H} {235};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_DEST_ID_L} {235};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_PROTECTION_H} {239};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_PROTECTION_L} {237};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_RESPONSE_STATUS_H} {245};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_RESPONSE_STATUS_L} {244};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_ORI_BURST_SIZE_L} {246};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_ORI_BURST_SIZE_H} {248};set_instance_parameter_value {onchip_memory2_0_s2_agent} {ST_CHANNEL_W} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent} {ST_DATA_W} {249};set_instance_parameter_value {onchip_memory2_0_s2_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {AVS_BURSTCOUNT_W} {5};set_instance_parameter_value {onchip_memory2_0_s2_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {onchip_memory2_0_s2_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent} {MAX_BYTE_CNT} {16};set_instance_parameter_value {onchip_memory2_0_s2_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent} {ID} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {USE_WRITERESPONSE} {0};add_instance {onchip_memory2_0_s2_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {BITS_PER_SYMBOL} {250};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {0 };set_instance_parameter_value {router} {CHANNEL_ID} {1 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 };set_instance_parameter_value {router} {END_ADDRESS} {0x1000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {207};set_instance_parameter_value {router} {PKT_ADDR_L} {144};set_instance_parameter_value {router} {PKT_PROTECTION_H} {239};set_instance_parameter_value {router} {PKT_PROTECTION_L} {237};set_instance_parameter_value {router} {PKT_DEST_ID_H} {235};set_instance_parameter_value {router} {PKT_DEST_ID_L} {235};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {router} {PKT_TRANS_READ} {211};set_instance_parameter_value {router} {ST_DATA_W} {249};set_instance_parameter_value {router} {ST_CHANNEL_W} {1};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {1 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {read };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {207};set_instance_parameter_value {router_001} {PKT_ADDR_L} {144};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {239};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {237};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {235};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {235};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {211};set_instance_parameter_value {router_001} {ST_DATA_W} {249};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {1};set_instance_parameter_value {router_001} {DECODER_TYPE} {1};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {onchip_memory2_0_s2_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_ADDR_H} {207};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_ADDR_L} {144};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BYTEEN_H} {143};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BYTEEN_L} {128};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURST_TYPE_H} {229};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURST_TYPE_L} {228};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_TRANS_READ} {211};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {ST_DATA_W} {249};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {ST_CHANNEL_W} {1};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {OUT_BYTE_CNT_H} {218};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {OUT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {BURSTWRAP_CONST_MASK} {1};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {BURSTWRAP_CONST_VALUE} {1};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {249};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {1};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {249};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {1};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {249};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {1};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {249};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {1};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {onchip_memory2_0_reset2_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {onchip_memory2_0_reset2_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {onchip_memory2_0_reset2_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {onchip_memory2_0_reset2_reset_bridge} {NUM_RESET_OUTPUTS} {1};add_instance {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {EXPLICIT_CLOCK_RATE} {125000000};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_universal_master_0} {pcie_256_hip_avmm_0_dma_wr_master_agent.av} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_wr_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_wr_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_wr_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {pcie_256_hip_avmm_0_dma_wr_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/pcie_256_hip_avmm_0_dma_wr_master_agent.rp} {qsys_mm.response};add_connection {onchip_memory2_0_s2_agent.m0} {onchip_memory2_0_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_memory2_0_s2_agent.m0/onchip_memory2_0_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_memory2_0_s2_agent.m0/onchip_memory2_0_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_memory2_0_s2_agent.m0/onchip_memory2_0_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_memory2_0_s2_agent.rf_source} {onchip_memory2_0_s2_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_memory2_0_s2_agent_rsp_fifo.out} {onchip_memory2_0_s2_agent.rf_sink} {avalon_streaming};add_connection {onchip_memory2_0_s2_agent.rdata_fifo_src} {onchip_memory2_0_s2_agent.rdata_fifo_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_dma_wr_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_dma_wr_master_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {onchip_memory2_0_s2_agent.rp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s2_agent.rp/router_001.sink} {qsys_mm.response};add_connection {router_001.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/rsp_demux.sink} {qsys_mm.response};add_connection {cmd_mux.src} {onchip_memory2_0_s2_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/onchip_memory2_0_s2_burst_adapter.sink0} {qsys_mm.command};add_connection {onchip_memory2_0_s2_burst_adapter.source0} {onchip_memory2_0_s2_agent.cp} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s2_burst_adapter.source0/onchip_memory2_0_s2_agent.cp} {qsys_mm.command};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_wr_master_translator.reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {onchip_memory2_0_s2_translator.reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_wr_master_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {onchip_memory2_0_s2_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {onchip_memory2_0_s2_agent_rsp_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {onchip_memory2_0_s2_burst_adapter.cr0_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_wr_master_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s2_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_wr_master_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s2_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s2_agent_rsp_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s2_burst_adapter.cr0} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_reset2_reset_bridge.clk} {clock};add_interface {pcie_256_hip_avmm_0_coreclkout} {clock} {slave};set_interface_property {pcie_256_hip_avmm_0_coreclkout} {EXPORT_OF} {pcie_256_hip_avmm_0_coreclkout_clock_bridge.in_clk};add_interface {onchip_memory2_0_reset2_reset_bridge_in_reset} {reset} {slave};set_interface_property {onchip_memory2_0_reset2_reset_bridge_in_reset} {EXPORT_OF} {onchip_memory2_0_reset2_reset_bridge.in_reset};add_interface {pcie_256_hip_avmm_0_dma_wr_master} {avalon} {slave};set_interface_property {pcie_256_hip_avmm_0_dma_wr_master} {EXPORT_OF} {pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_anti_master_0};add_interface {onchip_memory2_0_s2} {avalon} {master};set_interface_property {onchip_memory2_0_s2} {EXPORT_OF} {onchip_memory2_0_s2_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.onchip_memory2_0.s2} {0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.dma_wr_master} {0};(altera_merlin_master_translator:14.0:AUTO_CLK_CLOCK_RATE=125000000,AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=64,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=6,AV_BYTEENABLE_W=16,AV_CONSTANT_BURST_BEHAVIOR=1,AV_DATA_HOLD=0,AV_DATA_W=128,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=16,AV_WRITE_WAIT=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=10,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=1,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:14.0:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=8,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=16,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=128,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=16,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=125000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=5,UAV_BYTEENABLE_W=16,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=128,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_agent:14.0:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;onchip_memory2_0_s2_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000001000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
,AUTO_CLK_CLOCK_RATE=125000000,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=10,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=1,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_ADDR_SIDEBAND_H=230,PKT_ADDR_SIDEBAND_L=230,PKT_BEGIN_BURST=232,PKT_BURSTWRAP_H=224,PKT_BURSTWRAP_L=224,PKT_BURST_SIZE_H=227,PKT_BURST_SIZE_L=225,PKT_BURST_TYPE_H=229,PKT_BURST_TYPE_L=228,PKT_BYTEEN_H=143,PKT_BYTEEN_L=128,PKT_BYTE_CNT_H=223,PKT_BYTE_CNT_L=214,PKT_CACHE_H=243,PKT_CACHE_L=240,PKT_DATA_H=127,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=231,PKT_DATA_SIDEBAND_L=231,PKT_DEST_ID_H=235,PKT_DEST_ID_L=235,PKT_ORI_BURST_SIZE_H=248,PKT_ORI_BURST_SIZE_L=246,PKT_PROTECTION_H=239,PKT_PROTECTION_L=237,PKT_QOS_H=233,PKT_QOS_L=233,PKT_RESPONSE_STATUS_H=245,PKT_RESPONSE_STATUS_L=244,PKT_SRC_ID_H=234,PKT_SRC_ID_L=234,PKT_THREAD_ID_H=236,PKT_THREAD_ID_L=236,PKT_TRANS_COMPRESSED_READ=208,PKT_TRANS_EXCLUSIVE=213,PKT_TRANS_LOCK=212,PKT_TRANS_POSTED=209,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=1,ST_DATA_W=249,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_slave_agent:14.0:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=5,AV_LINEWRAPBURSTS=0,ID=0,MAX_BURSTWRAP=1,MAX_BYTE_CNT=16,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_BEGIN_BURST=232,PKT_BURSTWRAP_H=224,PKT_BURSTWRAP_L=224,PKT_BURST_SIZE_H=227,PKT_BURST_SIZE_L=225,PKT_BYTEEN_H=143,PKT_BYTEEN_L=128,PKT_BYTE_CNT_H=223,PKT_BYTE_CNT_L=214,PKT_DATA_H=127,PKT_DATA_L=0,PKT_DEST_ID_H=235,PKT_DEST_ID_L=235,PKT_ORI_BURST_SIZE_H=248,PKT_ORI_BURST_SIZE_L=246,PKT_PROTECTION_H=239,PKT_PROTECTION_L=237,PKT_RESPONSE_STATUS_H=245,PKT_RESPONSE_STATUS_L=244,PKT_SRC_ID_H=234,PKT_SRC_ID_L=234,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=208,PKT_TRANS_LOCK=212,PKT_TRANS_POSTED=209,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=1,ST_DATA_W=249,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:14.0:AUTO_DEVICE_FAMILY=Arria V,BITS_PER_SYMBOL=250,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x1000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NON_SECURED_TAG=1,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_DEST_ID_H=235,PKT_DEST_ID_L=235,PKT_PROTECTION_H=239,PKT_PROTECTION_L=237,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x1000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=1,ST_DATA_W=249,TYPE_OF_TRANSACTION=both)(altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NON_SECURED_TAG=1,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_DEST_ID_H=235,PKT_DEST_ID_L=235,PKT_PROTECTION_H=239,PKT_PROTECTION_L=237,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=1,ST_DATA_W=249,TYPE_OF_TRANSACTION=read)(altera_merlin_burst_adapter:14.0:ADAPTER_VERSION=13.1,AUTO_CR0_CLOCK_RATE=125000000,BURSTWRAP_CONST_MASK=1,BURSTWRAP_CONST_VALUE=1,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=1,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=224,OUT_BYTE_CNT_H=218,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_BEGIN_BURST=232,PKT_BURSTWRAP_H=224,PKT_BURSTWRAP_L=224,PKT_BURST_SIZE_H=227,PKT_BURST_SIZE_L=225,PKT_BURST_TYPE_H=229,PKT_BURST_TYPE_L=228,PKT_BYTEEN_H=143,PKT_BYTEEN_L=128,PKT_BYTE_CNT_H=223,PKT_BYTE_CNT_L=214,PKT_TRANS_COMPRESSED_READ=208,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,ST_CHANNEL_W=1,ST_DATA_W=249)(altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_OUTPUTS=1,ST_CHANNEL_W=1,ST_DATA_W=249,VALID_WIDTH=1)(altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=212,ST_CHANNEL_W=1,ST_DATA_W=249,USE_EXTERNAL_ARB=0)(altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_OUTPUTS=1,ST_CHANNEL_W=1,ST_DATA_W=249,VALID_WIDTH=1)(altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=212,ST_CHANNEL_W=1,ST_DATA_W=249,USE_EXTERNAL_ARB=0)(altera_reset_bridge:14.0:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=125000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert)(altera_clock_bridge:14.0:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=125000000,NUM_CLOCK_OUTPUTS=1)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)"
   instancePathKey="top:.:mm_interconnect_2"
   kind="altera_mm_interconnect"
   version="14.0"
   name="top_mm_interconnect_2">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_DEVICE" value="5AGXFB3H4F35C5" />
  <parameter
     name="COMPOSE_CONTENTS"
     value="add_instance {pcie_256_hip_avmm_0_dma_wr_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_DATA_W} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_BURSTCOUNT_W} {6};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_BYTEENABLE_W} {16};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {UAV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_READDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_READ} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_WRITE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_SYMBOLS_PER_WORD} {16};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};add_instance {onchip_memory2_0_s2_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_DATA_W} {128};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_DATA_W} {128};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_BYTEENABLE_W} {16};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_BYTEENABLE_W} {16};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_BURSTCOUNT_W} {5};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_READLATENCY} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_READ} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_SYMBOLS_PER_WORD} {16};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_memory2_0_s2_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {pcie_256_hip_avmm_0_dma_wr_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_PROTECTION_H} {239};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_PROTECTION_L} {237};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURST_TYPE_H} {229};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BURST_TYPE_L} {228};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ADDR_H} {207};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ADDR_L} {144};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_POSTED} {209};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_READ} {211};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_TRANS_EXCLUSIVE} {213};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DATA_H} {127};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BYTEEN_H} {143};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_BYTEEN_L} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_SRC_ID_H} {234};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_SRC_ID_L} {234};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DEST_ID_H} {235};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DEST_ID_L} {235};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_THREAD_ID_H} {236};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_THREAD_ID_L} {236};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_CACHE_H} {243};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_CACHE_L} {240};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DATA_SIDEBAND_H} {231};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_DATA_SIDEBAND_L} {231};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_QOS_H} {233};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_QOS_L} {233};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ADDR_SIDEBAND_H} {230};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ADDR_SIDEBAND_L} {230};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_RESPONSE_STATUS_H} {245};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_RESPONSE_STATUS_L} {244};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ORI_BURST_SIZE_L} {246};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {PKT_ORI_BURST_SIZE_H} {248};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {ST_DATA_W} {249};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {ST_CHANNEL_W} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {AV_BURSTCOUNT_W} {10};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;onchip_memory2_0_s2_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000001000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {ID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_agent} {USE_WRITERESPONSE} {0};add_instance {onchip_memory2_0_s2_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_DATA_H} {127};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BYTEEN_H} {143};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BYTEEN_L} {128};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_ADDR_H} {207};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_ADDR_L} {144};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_TRANS_POSTED} {209};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_TRANS_READ} {211};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_SRC_ID_H} {234};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_SRC_ID_L} {234};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_DEST_ID_H} {235};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_DEST_ID_L} {235};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_PROTECTION_H} {239};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_PROTECTION_L} {237};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_RESPONSE_STATUS_H} {245};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_RESPONSE_STATUS_L} {244};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_ORI_BURST_SIZE_L} {246};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PKT_ORI_BURST_SIZE_H} {248};set_instance_parameter_value {onchip_memory2_0_s2_agent} {ST_CHANNEL_W} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent} {ST_DATA_W} {249};set_instance_parameter_value {onchip_memory2_0_s2_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {AVS_BURSTCOUNT_W} {5};set_instance_parameter_value {onchip_memory2_0_s2_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {onchip_memory2_0_s2_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent} {MAX_BYTE_CNT} {16};set_instance_parameter_value {onchip_memory2_0_s2_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent} {ID} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent} {USE_WRITERESPONSE} {0};add_instance {onchip_memory2_0_s2_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {BITS_PER_SYMBOL} {250};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_memory2_0_s2_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {0 };set_instance_parameter_value {router} {CHANNEL_ID} {1 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 };set_instance_parameter_value {router} {END_ADDRESS} {0x1000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {207};set_instance_parameter_value {router} {PKT_ADDR_L} {144};set_instance_parameter_value {router} {PKT_PROTECTION_H} {239};set_instance_parameter_value {router} {PKT_PROTECTION_L} {237};set_instance_parameter_value {router} {PKT_DEST_ID_H} {235};set_instance_parameter_value {router} {PKT_DEST_ID_L} {235};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {router} {PKT_TRANS_READ} {211};set_instance_parameter_value {router} {ST_DATA_W} {249};set_instance_parameter_value {router} {ST_CHANNEL_W} {1};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {1 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {read };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {207};set_instance_parameter_value {router_001} {PKT_ADDR_L} {144};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {239};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {237};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {235};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {235};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {211};set_instance_parameter_value {router_001} {ST_DATA_W} {249};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {1};set_instance_parameter_value {router_001} {DECODER_TYPE} {1};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {onchip_memory2_0_s2_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_ADDR_H} {207};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_ADDR_L} {144};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BEGIN_BURST} {232};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BYTE_CNT_H} {223};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BYTE_CNT_L} {214};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BYTEEN_H} {143};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BYTEEN_L} {128};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURST_SIZE_H} {227};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURST_SIZE_L} {225};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURST_TYPE_H} {229};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURST_TYPE_L} {228};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_BURSTWRAP_L} {224};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {208};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_TRANS_WRITE} {210};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PKT_TRANS_READ} {211};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {ST_DATA_W} {249};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {ST_CHANNEL_W} {1};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {OUT_BYTE_CNT_H} {218};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {OUT_BURSTWRAP_H} {224};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {BURSTWRAP_CONST_MASK} {1};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {BURSTWRAP_CONST_VALUE} {1};set_instance_parameter_value {onchip_memory2_0_s2_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {249};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {1};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {249};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {1};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {249};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {1};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {249};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {1};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {212};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)};add_instance {onchip_memory2_0_reset2_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {onchip_memory2_0_reset2_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {onchip_memory2_0_reset2_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {onchip_memory2_0_reset2_reset_bridge} {NUM_RESET_OUTPUTS} {1};add_instance {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {EXPLICIT_CLOCK_RATE} {125000000};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_universal_master_0} {pcie_256_hip_avmm_0_dma_wr_master_agent.av} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_wr_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_wr_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_dma_wr_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {pcie_256_hip_avmm_0_dma_wr_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/pcie_256_hip_avmm_0_dma_wr_master_agent.rp} {qsys_mm.response};add_connection {onchip_memory2_0_s2_agent.m0} {onchip_memory2_0_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_memory2_0_s2_agent.m0/onchip_memory2_0_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_memory2_0_s2_agent.m0/onchip_memory2_0_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_memory2_0_s2_agent.m0/onchip_memory2_0_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_memory2_0_s2_agent.rf_source} {onchip_memory2_0_s2_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_memory2_0_s2_agent_rsp_fifo.out} {onchip_memory2_0_s2_agent.rf_sink} {avalon_streaming};add_connection {onchip_memory2_0_s2_agent.rdata_fifo_src} {onchip_memory2_0_s2_agent.rdata_fifo_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_dma_wr_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_dma_wr_master_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {onchip_memory2_0_s2_agent.rp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s2_agent.rp/router_001.sink} {qsys_mm.response};add_connection {router_001.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/rsp_demux.sink} {qsys_mm.response};add_connection {cmd_mux.src} {onchip_memory2_0_s2_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/onchip_memory2_0_s2_burst_adapter.sink0} {qsys_mm.command};add_connection {onchip_memory2_0_s2_burst_adapter.source0} {onchip_memory2_0_s2_agent.cp} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s2_burst_adapter.source0/onchip_memory2_0_s2_agent.cp} {qsys_mm.command};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_wr_master_translator.reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {onchip_memory2_0_s2_translator.reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {pcie_256_hip_avmm_0_dma_wr_master_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {onchip_memory2_0_s2_agent.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {onchip_memory2_0_s2_agent_rsp_fifo.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {onchip_memory2_0_s2_burst_adapter.cr0_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {onchip_memory2_0_reset2_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_wr_master_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s2_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_dma_wr_master_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s2_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s2_agent_rsp_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_s2_burst_adapter.cr0} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {onchip_memory2_0_reset2_reset_bridge.clk} {clock};add_interface {pcie_256_hip_avmm_0_coreclkout} {clock} {slave};set_interface_property {pcie_256_hip_avmm_0_coreclkout} {EXPORT_OF} {pcie_256_hip_avmm_0_coreclkout_clock_bridge.in_clk};add_interface {onchip_memory2_0_reset2_reset_bridge_in_reset} {reset} {slave};set_interface_property {onchip_memory2_0_reset2_reset_bridge_in_reset} {EXPORT_OF} {onchip_memory2_0_reset2_reset_bridge.in_reset};add_interface {pcie_256_hip_avmm_0_dma_wr_master} {avalon} {slave};set_interface_property {pcie_256_hip_avmm_0_dma_wr_master} {EXPORT_OF} {pcie_256_hip_avmm_0_dma_wr_master_translator.avalon_anti_master_0};add_interface {onchip_memory2_0_s2} {avalon} {master};set_interface_property {onchip_memory2_0_s2} {EXPORT_OF} {onchip_memory2_0_s2_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.onchip_memory2_0.s2} {0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.dma_wr_master} {0};" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v"
       type="VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2_router.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2_router_001.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_adapter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_wrap_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_incr_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_default_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_st_pipeline_base.v"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2_cmd_demux.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2_cmd_mux.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2_rsp_mux.sv"
       type="SYSTEM_VERILOG" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
  </childSourceFiles>
  <instantiator instantiator="top" as="mm_interconnect_2" />
  <messages>
   <message level="Debug" culprit="top">queue size: 42 starting:altera_mm_interconnect "submodules/top_mm_interconnect_2"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>14</b> modules, <b>39</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>14</b> modules, <b>39</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>14</b> modules, <b>39</b> connections]]></message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_2_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_2_router_001</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_2_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_2_cmd_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_2_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_2"><![CDATA["<b>mm_interconnect_2</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_2_rsp_mux</b>"]]></message>
   <message level="Info" culprit="mm_interconnect_2"><![CDATA["<b>top</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_2</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 66 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_translator</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 64 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>onchip_memory2_0_s1_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 61 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 59 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>onchip_memory2_0_s1_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 58 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>onchip_memory2_0_s1_agent_rsp_fifo</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
   <message level="Debug" culprit="top">queue size: 22 starting:altera_merlin_router "submodules/top_mm_interconnect_2_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 21 starting:altera_merlin_router "submodules/top_mm_interconnect_2_router_001"</message>
   <message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 46 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>onchip_memory2_0_s1_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 19 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_2_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 18 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_2_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 16 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_2_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_mm_interconnect:14.0:AUTO_DEVICE=5AGXFB3H4F35C5,AUTO_DEVICE_FAMILY=Arria V,COMPOSE_CONTENTS=add_instance {pcie_256_hip_avmm_0_wr_dcm_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_READDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_READ} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};add_instance {pcie_256_hip_avmm_0_rd_dcm_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_READDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_READ} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};add_instance {pcie_256_hip_avmm_0_Txs_translator} {altera_merlin_slave_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_ADDRESS_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_DATA_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_DATA_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_READDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_READ} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {pcie_256_hip_avmm_0_wr_dcm_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_PROTECTION_H} {124};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_PROTECTION_L} {122};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BEGIN_BURST} {117};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURSTWRAP_H} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURSTWRAP_L} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURST_SIZE_H} {112};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURST_SIZE_L} {110};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURST_TYPE_H} {114};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURST_TYPE_L} {113};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BYTE_CNT_H} {108};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BYTE_CNT_L} {106};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ADDR_H} {99};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_POSTED} {101};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_READ} {103};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_EXCLUSIVE} {105};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_SRC_ID_H} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_SRC_ID_L} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DEST_ID_H} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DEST_ID_L} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_THREAD_ID_H} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_THREAD_ID_L} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_CACHE_H} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_CACHE_L} {125};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DATA_SIDEBAND_H} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DATA_SIDEBAND_L} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_QOS_H} {118};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_QOS_L} {118};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ADDR_SIDEBAND_H} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ADDR_SIDEBAND_L} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_RESPONSE_STATUS_H} {130};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_RESPONSE_STATUS_L} {129};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ORI_BURST_SIZE_L} {131};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ORI_BURST_SIZE_H} {133};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {ST_DATA_W} {134};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000100000000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {ID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_rd_dcm_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_PROTECTION_H} {124};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_PROTECTION_L} {122};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BEGIN_BURST} {117};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURSTWRAP_H} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURSTWRAP_L} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURST_SIZE_H} {112};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURST_SIZE_L} {110};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURST_TYPE_H} {114};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURST_TYPE_L} {113};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BYTE_CNT_H} {108};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BYTE_CNT_L} {106};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ADDR_H} {99};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_POSTED} {101};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_READ} {103};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_EXCLUSIVE} {105};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_SRC_ID_H} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_SRC_ID_L} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DEST_ID_H} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DEST_ID_L} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_THREAD_ID_H} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_THREAD_ID_L} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_CACHE_H} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_CACHE_L} {125};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DATA_SIDEBAND_H} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DATA_SIDEBAND_L} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_QOS_H} {118};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_QOS_L} {118};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ADDR_SIDEBAND_H} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ADDR_SIDEBAND_L} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_RESPONSE_STATUS_H} {130};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_RESPONSE_STATUS_L} {129};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ORI_BURST_SIZE_L} {131};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ORI_BURST_SIZE_H} {133};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {ST_DATA_W} {134};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000100000000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {ID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_Txs_agent} {altera_merlin_slave_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_DATA_H} {31};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BEGIN_BURST} {117};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_ADDR_H} {99};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_TRANS_POSTED} {101};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_TRANS_READ} {103};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_SRC_ID_H} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_SRC_ID_L} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_DEST_ID_H} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_DEST_ID_L} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BURSTWRAP_H} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BURSTWRAP_L} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BYTE_CNT_H} {108};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BYTE_CNT_L} {106};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_PROTECTION_H} {124};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_PROTECTION_L} {122};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_RESPONSE_STATUS_H} {130};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_RESPONSE_STATUS_L} {129};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BURST_SIZE_H} {112};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BURST_SIZE_L} {110};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_ORI_BURST_SIZE_L} {131};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_ORI_BURST_SIZE_H} {133};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {ST_DATA_W} {134};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {ID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {BITS_PER_SYMBOL} {135};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {FIFO_DEPTH} {9};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {0 };set_instance_parameter_value {router} {CHANNEL_ID} {1 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 };set_instance_parameter_value {router} {END_ADDRESS} {0x100000000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {99};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {124};set_instance_parameter_value {router} {PKT_PROTECTION_L} {122};set_instance_parameter_value {router} {PKT_DEST_ID_H} {120};set_instance_parameter_value {router} {PKT_DEST_ID_L} {120};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {router} {PKT_TRANS_READ} {103};set_instance_parameter_value {router} {ST_DATA_W} {134};set_instance_parameter_value {router} {ST_CHANNEL_W} {2};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {1 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x100000000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {99};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {124};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {122};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {120};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {120};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {103};set_instance_parameter_value {router_001} {ST_DATA_W} {134};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {1 0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {99};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {124};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {122};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {120};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {120};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {103};set_instance_parameter_value {router_002} {ST_DATA_W} {134};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {1};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {134};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {134};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {134};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {134};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {134};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {134};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};add_instance {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {EXPLICIT_CLOCK_RATE} {125000000};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_universal_master_0} {pcie_256_hip_avmm_0_wr_dcm_master_agent.av} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_wr_dcm_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_wr_dcm_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_wr_dcm_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {pcie_256_hip_avmm_0_wr_dcm_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/pcie_256_hip_avmm_0_wr_dcm_master_agent.rp} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_universal_master_0} {pcie_256_hip_avmm_0_rd_dcm_master_agent.av} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_rd_dcm_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_rd_dcm_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_rd_dcm_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_001.src} {pcie_256_hip_avmm_0_rd_dcm_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/pcie_256_hip_avmm_0_rd_dcm_master_agent.rp} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_Txs_agent.m0} {pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_Txs_agent.m0/pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_Txs_agent.m0/pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_Txs_agent.m0/pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {pcie_256_hip_avmm_0_Txs_agent.rf_source} {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo.in} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo.out} {pcie_256_hip_avmm_0_Txs_agent.rf_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_Txs_agent.rdata_fifo_src} {pcie_256_hip_avmm_0_Txs_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {pcie_256_hip_avmm_0_Txs_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/pcie_256_hip_avmm_0_Txs_agent.cp} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_wr_dcm_master_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_rd_dcm_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_rd_dcm_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_Txs_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_Txs_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux.sink1} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dcm_master_translator.reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dcm_master_translator.reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Txs_translator.reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dcm_master_agent.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dcm_master_agent.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Txs_agent.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dcm_master_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dcm_master_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Txs_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dcm_master_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dcm_master_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Txs_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.clk} {clock};add_interface {pcie_256_hip_avmm_0_coreclkout} {clock} {slave};set_interface_property {pcie_256_hip_avmm_0_coreclkout} {EXPORT_OF} {pcie_256_hip_avmm_0_coreclkout_clock_bridge.in_clk};add_interface {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge_in_reset} {EXPORT_OF} {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.in_reset};add_interface {pcie_256_hip_avmm_0_rd_dcm_master} {avalon} {slave};set_interface_property {pcie_256_hip_avmm_0_rd_dcm_master} {EXPORT_OF} {pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_anti_master_0};add_interface {pcie_256_hip_avmm_0_wr_dcm_master} {avalon} {slave};set_interface_property {pcie_256_hip_avmm_0_wr_dcm_master} {EXPORT_OF} {pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_anti_master_0};add_interface {pcie_256_hip_avmm_0_Txs} {avalon} {master};set_interface_property {pcie_256_hip_avmm_0_Txs} {EXPORT_OF} {pcie_256_hip_avmm_0_Txs_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.Txs} {0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.rd_dcm_master} {0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.wr_dcm_master} {1};(altera_merlin_master_translator:14.0:AUTO_CLK_CLOCK_RATE=125000000,AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=64,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_translator:14.0:AUTO_CLK_CLOCK_RATE=125000000,AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=64,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:14.0:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=32,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=8,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=1,AV_WRITE_WAIT_CYCLES=1,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=125000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_agent:14.0:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000100000000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
,AUTO_CLK_CLOCK_RATE=125000000,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=1,CACHE_VALUE=0,ID=1,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=115,PKT_ADDR_SIDEBAND_L=115,PKT_BEGIN_BURST=117,PKT_BURSTWRAP_H=109,PKT_BURSTWRAP_L=109,PKT_BURST_SIZE_H=112,PKT_BURST_SIZE_L=110,PKT_BURST_TYPE_H=114,PKT_BURST_TYPE_L=113,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=108,PKT_BYTE_CNT_L=106,PKT_CACHE_H=128,PKT_CACHE_L=125,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=116,PKT_DATA_SIDEBAND_L=116,PKT_DEST_ID_H=120,PKT_DEST_ID_L=120,PKT_ORI_BURST_SIZE_H=133,PKT_ORI_BURST_SIZE_L=131,PKT_PROTECTION_H=124,PKT_PROTECTION_L=122,PKT_QOS_H=118,PKT_QOS_L=118,PKT_RESPONSE_STATUS_H=130,PKT_RESPONSE_STATUS_L=129,PKT_SRC_ID_H=119,PKT_SRC_ID_L=119,PKT_THREAD_ID_H=121,PKT_THREAD_ID_L=121,PKT_TRANS_COMPRESSED_READ=100,PKT_TRANS_EXCLUSIVE=105,PKT_TRANS_LOCK=104,PKT_TRANS_POSTED=101,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=2,ST_DATA_W=134,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:14.0:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000100000000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
,AUTO_CLK_CLOCK_RATE=125000000,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=1,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=115,PKT_ADDR_SIDEBAND_L=115,PKT_BEGIN_BURST=117,PKT_BURSTWRAP_H=109,PKT_BURSTWRAP_L=109,PKT_BURST_SIZE_H=112,PKT_BURST_SIZE_L=110,PKT_BURST_TYPE_H=114,PKT_BURST_TYPE_L=113,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=108,PKT_BYTE_CNT_L=106,PKT_CACHE_H=128,PKT_CACHE_L=125,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=116,PKT_DATA_SIDEBAND_L=116,PKT_DEST_ID_H=120,PKT_DEST_ID_L=120,PKT_ORI_BURST_SIZE_H=133,PKT_ORI_BURST_SIZE_L=131,PKT_PROTECTION_H=124,PKT_PROTECTION_L=122,PKT_QOS_H=118,PKT_QOS_L=118,PKT_RESPONSE_STATUS_H=130,PKT_RESPONSE_STATUS_L=129,PKT_SRC_ID_H=119,PKT_SRC_ID_L=119,PKT_THREAD_ID_H=121,PKT_THREAD_ID_L=121,PKT_TRANS_COMPRESSED_READ=100,PKT_TRANS_EXCLUSIVE=105,PKT_TRANS_LOCK=104,PKT_TRANS_POSTED=101,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=2,ST_DATA_W=134,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_slave_agent:14.0:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ID=0,MAX_BURSTWRAP=1,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_BEGIN_BURST=117,PKT_BURSTWRAP_H=109,PKT_BURSTWRAP_L=109,PKT_BURST_SIZE_H=112,PKT_BURST_SIZE_L=110,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=108,PKT_BYTE_CNT_L=106,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=120,PKT_DEST_ID_L=120,PKT_ORI_BURST_SIZE_H=133,PKT_ORI_BURST_SIZE_L=131,PKT_PROTECTION_H=124,PKT_PROTECTION_L=122,PKT_RESPONSE_STATUS_H=130,PKT_RESPONSE_STATUS_L=129,PKT_SRC_ID_H=119,PKT_SRC_ID_L=119,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=100,PKT_TRANS_LOCK=104,PKT_TRANS_POSTED=101,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=2,ST_DATA_W=134,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:14.0:AUTO_DEVICE_FAMILY=Arria V,BITS_PER_SYMBOL=135,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=9,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x100000000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_DEST_ID_H=120,PKT_DEST_ID_L=120,PKT_PROTECTION_H=124,PKT_PROTECTION_L=122,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x100000000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=2,ST_DATA_W=134,TYPE_OF_TRANSACTION=both)(altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x100000000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_DEST_ID_H=120,PKT_DEST_ID_L=120,PKT_PROTECTION_H=124,PKT_PROTECTION_L=122,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x100000000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=2,ST_DATA_W=134,TYPE_OF_TRANSACTION=both)(altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=1,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=1,0,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_DEST_ID_H=120,PKT_DEST_ID_L=120,PKT_PROTECTION_H=124,PKT_PROTECTION_L=122,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=1:01:0x0:0x0:both:1:0:0:1,0:10:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=2,ST_DATA_W=134,TYPE_OF_TRANSACTION=both,both)(altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=2,ST_DATA_W=134,VALID_WIDTH=1)(altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=2,ST_DATA_W=134,VALID_WIDTH=1)(altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=104,ST_CHANNEL_W=2,ST_DATA_W=134,USE_EXTERNAL_ARB=0)(altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=2,ST_DATA_W=134,VALID_WIDTH=1)(altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=104,ST_CHANNEL_W=2,ST_DATA_W=134,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=104,ST_CHANNEL_W=2,ST_DATA_W=134,USE_EXTERNAL_ARB=0)(altera_reset_bridge:14.0:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=125000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert)(altera_clock_bridge:14.0:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=125000000,NUM_CLOCK_OUTPUTS=1)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(avalon_streaming:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)"
   instancePathKey="top:.:mm_interconnect_3"
   kind="altera_mm_interconnect"
   version="14.0"
   name="top_mm_interconnect_3">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_DEVICE" value="5AGXFB3H4F35C5" />
  <parameter
     name="COMPOSE_CONTENTS"
     value="add_instance {pcie_256_hip_avmm_0_wr_dcm_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_READDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_READ} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};add_instance {pcie_256_hip_avmm_0_rd_dcm_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_READDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_READ} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};add_instance {pcie_256_hip_avmm_0_Txs_translator} {altera_merlin_slave_translator};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_ADDRESS_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_DATA_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_DATA_W} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_ADDRESS_W} {64};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_READLATENCY} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_READDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_READ} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_WRITE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_ADDRESS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_LOCK} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {pcie_256_hip_avmm_0_wr_dcm_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_PROTECTION_H} {124};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_PROTECTION_L} {122};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BEGIN_BURST} {117};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURSTWRAP_H} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURSTWRAP_L} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURST_SIZE_H} {112};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURST_SIZE_L} {110};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURST_TYPE_H} {114};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BURST_TYPE_L} {113};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BYTE_CNT_H} {108};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BYTE_CNT_L} {106};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ADDR_H} {99};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_POSTED} {101};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_READ} {103};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_TRANS_EXCLUSIVE} {105};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_SRC_ID_H} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_SRC_ID_L} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DEST_ID_H} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DEST_ID_L} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_THREAD_ID_H} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_THREAD_ID_L} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_CACHE_H} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_CACHE_L} {125};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DATA_SIDEBAND_H} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_DATA_SIDEBAND_L} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_QOS_H} {118};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_QOS_L} {118};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ADDR_SIDEBAND_H} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ADDR_SIDEBAND_L} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_RESPONSE_STATUS_H} {130};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_RESPONSE_STATUS_L} {129};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ORI_BURST_SIZE_L} {131};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {PKT_ORI_BURST_SIZE_H} {133};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {ST_DATA_W} {134};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000100000000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {ID} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_rd_dcm_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_PROTECTION_H} {124};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_PROTECTION_L} {122};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BEGIN_BURST} {117};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURSTWRAP_H} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURSTWRAP_L} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURST_SIZE_H} {112};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURST_SIZE_L} {110};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURST_TYPE_H} {114};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BURST_TYPE_L} {113};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BYTE_CNT_H} {108};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BYTE_CNT_L} {106};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ADDR_H} {99};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_POSTED} {101};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_READ} {103};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_TRANS_EXCLUSIVE} {105};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_SRC_ID_H} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_SRC_ID_L} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DEST_ID_H} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DEST_ID_L} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_THREAD_ID_H} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_THREAD_ID_L} {121};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_CACHE_H} {128};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_CACHE_L} {125};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DATA_SIDEBAND_H} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_DATA_SIDEBAND_L} {116};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_QOS_H} {118};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_QOS_L} {118};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ADDR_SIDEBAND_H} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ADDR_SIDEBAND_L} {115};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_RESPONSE_STATUS_H} {130};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_RESPONSE_STATUS_L} {129};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ORI_BURST_SIZE_L} {131};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {PKT_ORI_BURST_SIZE_H} {133};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {ST_DATA_W} {134};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000100000000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {ID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_Txs_agent} {altera_merlin_slave_agent};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_DATA_H} {31};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_DATA_L} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BEGIN_BURST} {117};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_ADDR_H} {99};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_TRANS_COMPRESSED_READ} {100};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_TRANS_POSTED} {101};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_TRANS_READ} {103};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_SRC_ID_H} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_SRC_ID_L} {119};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_DEST_ID_H} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_DEST_ID_L} {120};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BURSTWRAP_H} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BURSTWRAP_L} {109};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BYTE_CNT_H} {108};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BYTE_CNT_L} {106};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_PROTECTION_H} {124};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_PROTECTION_L} {122};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_RESPONSE_STATUS_H} {130};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_RESPONSE_STATUS_L} {129};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BURST_SIZE_H} {112};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_BURST_SIZE_L} {110};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_ORI_BURST_SIZE_L} {131};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PKT_ORI_BURST_SIZE_H} {133};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {ST_DATA_W} {134};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {ID} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent} {USE_WRITERESPONSE} {0};add_instance {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {BITS_PER_SYMBOL} {135};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {FIFO_DEPTH} {9};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {0 };set_instance_parameter_value {router} {CHANNEL_ID} {1 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 };set_instance_parameter_value {router} {END_ADDRESS} {0x100000000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {99};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {124};set_instance_parameter_value {router} {PKT_PROTECTION_L} {122};set_instance_parameter_value {router} {PKT_DEST_ID_H} {120};set_instance_parameter_value {router} {PKT_DEST_ID_L} {120};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {router} {PKT_TRANS_READ} {103};set_instance_parameter_value {router} {ST_DATA_W} {134};set_instance_parameter_value {router} {ST_CHANNEL_W} {2};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {1 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x100000000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {99};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {124};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {122};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {120};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {120};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {103};set_instance_parameter_value {router_001} {ST_DATA_W} {134};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {1 0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {99};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {124};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {122};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {120};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {120};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {102};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {103};set_instance_parameter_value {router_002} {ST_DATA_W} {134};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {1};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {134};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {134};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {134};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {134};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {134};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {134};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {104};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)};add_instance {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};add_instance {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {EXPLICIT_CLOCK_RATE} {125000000};set_instance_parameter_value {pcie_256_hip_avmm_0_coreclkout_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_universal_master_0} {pcie_256_hip_avmm_0_wr_dcm_master_agent.av} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_wr_dcm_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_wr_dcm_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_wr_dcm_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {pcie_256_hip_avmm_0_wr_dcm_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/pcie_256_hip_avmm_0_wr_dcm_master_agent.rp} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_universal_master_0} {pcie_256_hip_avmm_0_rd_dcm_master_agent.av} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_rd_dcm_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_rd_dcm_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_universal_master_0/pcie_256_hip_avmm_0_rd_dcm_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_001.src} {pcie_256_hip_avmm_0_rd_dcm_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/pcie_256_hip_avmm_0_rd_dcm_master_agent.rp} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_Txs_agent.m0} {pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {pcie_256_hip_avmm_0_Txs_agent.m0/pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {pcie_256_hip_avmm_0_Txs_agent.m0/pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {pcie_256_hip_avmm_0_Txs_agent.m0/pcie_256_hip_avmm_0_Txs_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {pcie_256_hip_avmm_0_Txs_agent.rf_source} {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo.in} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo.out} {pcie_256_hip_avmm_0_Txs_agent.rf_sink} {avalon_streaming};add_connection {pcie_256_hip_avmm_0_Txs_agent.rdata_fifo_src} {pcie_256_hip_avmm_0_Txs_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {pcie_256_hip_avmm_0_Txs_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/pcie_256_hip_avmm_0_Txs_agent.cp} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_wr_dcm_master_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_rd_dcm_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_rd_dcm_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {pcie_256_hip_avmm_0_Txs_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {pcie_256_hip_avmm_0_Txs_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux.sink1} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dcm_master_translator.reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dcm_master_translator.reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Txs_translator.reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_wr_dcm_master_agent.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_rd_dcm_master_agent.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Txs_agent.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dcm_master_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dcm_master_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Txs_translator.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dcm_master_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_rd_dcm_master_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Txs_agent.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_Txs_agent_rsp_fifo.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {pcie_256_hip_avmm_0_coreclkout_clock_bridge.out_clk} {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.clk} {clock};add_interface {pcie_256_hip_avmm_0_coreclkout} {clock} {slave};set_interface_property {pcie_256_hip_avmm_0_coreclkout} {EXPORT_OF} {pcie_256_hip_avmm_0_coreclkout_clock_bridge.in_clk};add_interface {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge_in_reset} {EXPORT_OF} {pcie_256_hip_avmm_0_wr_dcm_master_translator_reset_reset_bridge.in_reset};add_interface {pcie_256_hip_avmm_0_rd_dcm_master} {avalon} {slave};set_interface_property {pcie_256_hip_avmm_0_rd_dcm_master} {EXPORT_OF} {pcie_256_hip_avmm_0_rd_dcm_master_translator.avalon_anti_master_0};add_interface {pcie_256_hip_avmm_0_wr_dcm_master} {avalon} {slave};set_interface_property {pcie_256_hip_avmm_0_wr_dcm_master} {EXPORT_OF} {pcie_256_hip_avmm_0_wr_dcm_master_translator.avalon_anti_master_0};add_interface {pcie_256_hip_avmm_0_Txs} {avalon} {master};set_interface_property {pcie_256_hip_avmm_0_Txs} {EXPORT_OF} {pcie_256_hip_avmm_0_Txs_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.Txs} {0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.rd_dcm_master} {0};set_module_assignment {interconnect_id.pcie_256_hip_avmm_0.wr_dcm_master} {1};" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v"
       type="VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_router.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_router_002.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_cmd_demux.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_cmd_mux.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_rsp_demux.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_rsp_mux.sv"
       type="SYSTEM_VERILOG" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
  </childSourceFiles>
  <instantiator instantiator="top" as="mm_interconnect_3" />
  <messages>
   <message level="Debug" culprit="top">queue size: 53 starting:altera_mm_interconnect "submodules/top_mm_interconnect_3"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>18</b> modules, <b>52</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>18</b> modules, <b>52</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>18</b> modules, <b>52</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>18</b> modules, <b>52</b> connections]]></message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_3_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_3_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_router</b> "<b>submodules/top_mm_interconnect_3_router_002</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_3_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_3_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_3_cmd_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/top_mm_interconnect_3_rsp_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_3_rsp_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_3"><![CDATA["<b>mm_interconnect_3</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/top_mm_interconnect_3_rsp_mux</b>"]]></message>
   <message level="Info" culprit="mm_interconnect_3"><![CDATA["<b>top</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_3</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 66 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_translator</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 64 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>onchip_memory2_0_s1_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 61 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 59 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>onchip_memory2_0_s1_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 58 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>onchip_memory2_0_s1_agent_rsp_fifo</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
   <message level="Debug" culprit="top">queue size: 8 starting:altera_merlin_router "submodules/top_mm_interconnect_3_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 6 starting:altera_merlin_router "submodules/top_mm_interconnect_3_router_002"</message>
   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 5 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_3_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 3 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_3_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="top">queue size: 2 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_3_rsp_demux"</message>
   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
   <message level="Debug" culprit="top">queue size: 1 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_3_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_reset_controller:14.0:ADAPT_RESET_REQUEST=0,AUTO_CLK_CLOCK_RATE=-1,MIN_RST_ASSERTION_TIME=3,NUM_RESET_INPUTS=1,OUTPUT_RESET_SYNC_EDGES=deassert,RESET_REQUEST_PRESENT=0,RESET_REQ_EARLY_DSRT_TIME=1,RESET_REQ_WAIT_TIME=1,SYNC_DEPTH=2,USE_RESET_REQUEST_IN0=0,USE_RESET_REQUEST_IN1=0,USE_RESET_REQUEST_IN10=0,USE_RESET_REQUEST_IN11=0,USE_RESET_REQUEST_IN12=0,USE_RESET_REQUEST_IN13=0,USE_RESET_REQUEST_IN14=0,USE_RESET_REQUEST_IN15=0,USE_RESET_REQUEST_IN2=0,USE_RESET_REQUEST_IN3=0,USE_RESET_REQUEST_IN4=0,USE_RESET_REQUEST_IN5=0,USE_RESET_REQUEST_IN6=0,USE_RESET_REQUEST_IN7=0,USE_RESET_REQUEST_IN8=0,USE_RESET_REQUEST_IN9=0,USE_RESET_REQUEST_INPUT=0"
   instancePathKey="top:.:rst_controller"
   kind="altera_reset_controller"
   version="14.0"
   name="altera_reset_controller">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_controller.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_synchronizer.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_controller.sdc"
       type="SDC"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top" as="rst_controller,rst_controller_001" />
  <messages>
   <message level="Debug" culprit="top">queue size: 68 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
   <message level="Info" culprit="rst_controller"><![CDATA["<b>top</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_controller.v</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_synchronizer.v</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_controller.sdc</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_master_translator:14.0:AUTO_CLK_CLOCK_RATE=125000000,AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=64,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=0"
   instancePathKey="top:.:mm_interconnect_1:.:pcie_256_hip_avmm_0_Rxm_BAR2_translator"
   kind="altera_merlin_master_translator"
   version="14.0"
   name="altera_merlin_master_translator">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="top_mm_interconnect_1"
     as="pcie_256_hip_avmm_0_Rxm_BAR2_translator,pcie_256_hip_avmm_0_dma_rd_master_translator" />
  <instantiator
     instantiator="top_mm_interconnect_2"
     as="pcie_256_hip_avmm_0_dma_wr_master_translator" />
  <instantiator
     instantiator="top_mm_interconnect_3"
     as="pcie_256_hip_avmm_0_wr_dcm_master_translator,pcie_256_hip_avmm_0_rd_dcm_master_translator" />
  <messages>
   <message level="Debug" culprit="top">queue size: 66 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_translator</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_slave_translator:14.0:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=8,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=16,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=128,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=16,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=125000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=64,UAV_BURSTCOUNT_W=5,UAV_BYTEENABLE_W=16,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=128,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0"
   instancePathKey="top:.:mm_interconnect_1:.:onchip_memory2_0_s1_translator"
   kind="altera_merlin_slave_translator"
   version="14.0"
   name="altera_merlin_slave_translator">
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="top_mm_interconnect_1"
     as="onchip_memory2_0_s1_translator,pcie_256_hip_avmm_0_wr_dts_slave_translator,pcie_256_hip_avmm_0_rd_dts_slave_translator" />
  <instantiator
     instantiator="top_mm_interconnect_2"
     as="onchip_memory2_0_s2_translator" />
  <instantiator
     instantiator="top_mm_interconnect_3"
     as="pcie_256_hip_avmm_0_Txs_translator" />
  <messages>
   <message level="Debug" culprit="top">queue size: 64 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_translator"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>onchip_memory2_0_s1_translator</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_master_agent:14.0:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;onchip_memory2_0_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000001000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
,AUTO_CLK_CLOCK_RATE=125000000,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=1,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=122,PKT_ADDR_SIDEBAND_L=122,PKT_BEGIN_BURST=124,PKT_BURSTWRAP_H=116,PKT_BURSTWRAP_L=116,PKT_BURST_SIZE_H=119,PKT_BURST_SIZE_L=117,PKT_BURST_TYPE_H=121,PKT_BURST_TYPE_L=120,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=115,PKT_BYTE_CNT_L=106,PKT_CACHE_H=137,PKT_CACHE_L=134,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=123,PKT_DATA_SIDEBAND_L=123,PKT_DEST_ID_H=129,PKT_DEST_ID_L=128,PKT_ORI_BURST_SIZE_H=142,PKT_ORI_BURST_SIZE_L=140,PKT_PROTECTION_H=133,PKT_PROTECTION_L=131,PKT_QOS_H=125,PKT_QOS_L=125,PKT_RESPONSE_STATUS_H=139,PKT_RESPONSE_STATUS_L=138,PKT_SRC_ID_H=127,PKT_SRC_ID_L=126,PKT_THREAD_ID_H=130,PKT_THREAD_ID_L=130,PKT_TRANS_COMPRESSED_READ=100,PKT_TRANS_EXCLUSIVE=105,PKT_TRANS_LOCK=104,PKT_TRANS_POSTED=101,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=3,ST_DATA_W=143,SUPPRESS_0_BYTEEN_RSP=1,USE_READRESPONSE=0,USE_WRITERESPONSE=0"
   instancePathKey="top:.:mm_interconnect_1:.:pcie_256_hip_avmm_0_Rxm_BAR2_agent"
   kind="altera_merlin_master_agent"
   version="14.0"
   name="altera_merlin_master_agent">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="top_mm_interconnect_1"
     as="pcie_256_hip_avmm_0_Rxm_BAR2_agent,pcie_256_hip_avmm_0_dma_rd_master_agent" />
  <instantiator
     instantiator="top_mm_interconnect_2"
     as="pcie_256_hip_avmm_0_dma_wr_master_agent" />
  <instantiator
     instantiator="top_mm_interconnect_3"
     as="pcie_256_hip_avmm_0_wr_dcm_master_agent,pcie_256_hip_avmm_0_rd_dcm_master_agent" />
  <messages>
   <message level="Debug" culprit="top">queue size: 61 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
   <message level="Info" culprit="pcie_256_hip_avmm_0_Rxm_BAR2_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_slave_agent:14.0:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=5,AV_LINEWRAPBURSTS=0,ID=0,MAX_BURSTWRAP=1,MAX_BYTE_CNT=16,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_BEGIN_BURST=232,PKT_BURSTWRAP_H=224,PKT_BURSTWRAP_L=224,PKT_BURST_SIZE_H=227,PKT_BURST_SIZE_L=225,PKT_BYTEEN_H=143,PKT_BYTEEN_L=128,PKT_BYTE_CNT_H=223,PKT_BYTE_CNT_L=214,PKT_DATA_H=127,PKT_DATA_L=0,PKT_DEST_ID_H=237,PKT_DEST_ID_L=236,PKT_ORI_BURST_SIZE_H=250,PKT_ORI_BURST_SIZE_L=248,PKT_PROTECTION_H=241,PKT_PROTECTION_L=239,PKT_RESPONSE_STATUS_H=247,PKT_RESPONSE_STATUS_L=246,PKT_SRC_ID_H=235,PKT_SRC_ID_L=234,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=208,PKT_TRANS_LOCK=212,PKT_TRANS_POSTED=209,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=3,ST_DATA_W=251,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0"
   instancePathKey="top:.:mm_interconnect_1:.:onchip_memory2_0_s1_agent"
   kind="altera_merlin_slave_agent"
   version="14.0"
   name="altera_merlin_slave_agent">
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="top_mm_interconnect_1"
     as="onchip_memory2_0_s1_agent,pcie_256_hip_avmm_0_wr_dts_slave_agent,pcie_256_hip_avmm_0_rd_dts_slave_agent" />
  <instantiator instantiator="top_mm_interconnect_2" as="onchip_memory2_0_s2_agent" />
  <instantiator
     instantiator="top_mm_interconnect_3"
     as="pcie_256_hip_avmm_0_Txs_agent" />
  <messages>
   <message level="Debug" culprit="top">queue size: 59 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>onchip_memory2_0_s1_agent</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_avalon_sc_fifo:14.0:AUTO_DEVICE_FAMILY=Arria V,BITS_PER_SYMBOL=252,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0"
   instancePathKey="top:.:mm_interconnect_1:.:onchip_memory2_0_s1_agent_rsp_fifo"
   kind="altera_avalon_sc_fifo"
   version="14.0"
   name="altera_avalon_sc_fifo">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="top_mm_interconnect_1"
     as="onchip_memory2_0_s1_agent_rsp_fifo,pcie_256_hip_avmm_0_wr_dts_slave_agent_rsp_fifo,pcie_256_hip_avmm_0_wr_dts_slave_agent_rdata_fifo,pcie_256_hip_avmm_0_rd_dts_slave_agent_rsp_fifo,pcie_256_hip_avmm_0_rd_dts_slave_agent_rdata_fifo" />
  <instantiator
     instantiator="top_mm_interconnect_2"
     as="onchip_memory2_0_s2_agent_rsp_fifo" />
  <instantiator
     instantiator="top_mm_interconnect_3"
     as="pcie_256_hip_avmm_0_Txs_agent_rsp_fifo" />
  <messages>
   <message level="Debug" culprit="top">queue size: 58 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>onchip_memory2_0_s1_agent_rsp_fifo</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x1000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_DEST_ID_H=129,PKT_DEST_ID_L=128,PKT_PROTECTION_H=133,PKT_PROTECTION_L=131,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x1000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=3,ST_DATA_W=143,TYPE_OF_TRANSACTION=both"
   instancePathKey="top:.:mm_interconnect_1:.:router"
   kind="altera_merlin_router"
   version="14.0"
   name="top_mm_interconnect_1_router">
  <parameter name="END_ADDRESS" value="0x1000" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter name="CHANNEL_ID" value="1" />
  <parameter name="PKT_ADDR_L" value="36" />
  <parameter name="START_ADDRESS" value="0x0" />
  <parameter name="PKT_ADDR_H" value="99" />
  <parameter name="SECURED_RANGE_LIST" value="0" />
  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter name="TYPE_OF_TRANSACTION" value="both" />
  <parameter name="PKT_TRANS_READ" value="103" />
  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
  <parameter name="PKT_PROTECTION_L" value="131" />
  <parameter name="DEFAULT_CHANNEL" value="0" />
  <parameter name="PKT_PROTECTION_H" value="133" />
  <parameter name="SECURED_RANGE_PAIRS" value="0" />
  <parameter name="ST_DATA_W" value="143" />
  <parameter name="PKT_DEST_ID_L" value="128" />
  <parameter name="PKT_TRANS_WRITE" value="102" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="PKT_DEST_ID_H" value="129" />
  <parameter name="SLAVES_INFO" value="0:1:0x0:0x1000:both:1:0:0:1" />
  <parameter name="DESTINATION_ID" value="0" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="NON_SECURED_TAG" value="1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <parameter name="DECODER_TYPE" value="0" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_router.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="router" />
  <messages>
   <message level="Debug" culprit="top">queue size: 51 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=001,100,010,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,2,END_ADDRESS=0x1000,0x4000,0x6000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NON_SECURED_TAG=1,1,1,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_DEST_ID_H=237,PKT_DEST_ID_L=236,PKT_PROTECTION_H=241,PKT_PROTECTION_L=239,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,SECURED_RANGE_LIST=0,0,0,SECURED_RANGE_PAIRS=0,0,0,SLAVES_INFO=0:001:0x0:0x1000:both:1:0:0:1,1:100:0x2000:0x4000:write:1:0:0:1,2:010:0x4000:0x6000:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x2000,0x4000,ST_CHANNEL_W=3,ST_DATA_W=251,TYPE_OF_TRANSACTION=both,write,write"
   instancePathKey="top:.:mm_interconnect_1:.:router_001"
   kind="altera_merlin_router"
   version="14.0"
   name="top_mm_interconnect_1_router_001">
  <parameter name="END_ADDRESS" value="0x1000,0x4000,0x6000" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter name="CHANNEL_ID" value="001,100,010" />
  <parameter name="PKT_ADDR_L" value="144" />
  <parameter name="START_ADDRESS" value="0x0,0x2000,0x4000" />
  <parameter name="PKT_ADDR_H" value="207" />
  <parameter name="SECURED_RANGE_LIST" value="0,0,0" />
  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter name="TYPE_OF_TRANSACTION" value="both,write,write" />
  <parameter name="PKT_TRANS_READ" value="211" />
  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
  <parameter name="PKT_PROTECTION_L" value="239" />
  <parameter name="DEFAULT_CHANNEL" value="0" />
  <parameter name="PKT_PROTECTION_H" value="241" />
  <parameter name="SECURED_RANGE_PAIRS" value="0,0,0" />
  <parameter name="ST_DATA_W" value="251" />
  <parameter name="PKT_DEST_ID_L" value="236" />
  <parameter name="PKT_TRANS_WRITE" value="210" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="PKT_DEST_ID_H" value="237" />
  <parameter
     name="SLAVES_INFO"
     value="0:001:0x0:0x1000:both:1:0:0:1,1:100:0x2000:0x4000:write:1:0:0:1,2:010:0x4000:0x6000:write:1:0:0:1" />
  <parameter name="DESTINATION_ID" value="0,1,2" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="NON_SECURED_TAG" value="1,1,1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <parameter name="DECODER_TYPE" value="0" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_router_001.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="router_001" />
  <messages>
   <message level="Debug" culprit="top">queue size: 50 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router_001"</message>
   <message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_DEST_ID_H=237,PKT_DEST_ID_L=236,PKT_PROTECTION_H=241,PKT_PROTECTION_L=239,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=3,ST_DATA_W=251,TYPE_OF_TRANSACTION=both,write"
   instancePathKey="top:.:mm_interconnect_1:.:router_002"
   kind="altera_merlin_router"
   version="14.0"
   name="top_mm_interconnect_1_router_002">
  <parameter name="END_ADDRESS" value="0x0,0x0" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter name="CHANNEL_ID" value="01,10" />
  <parameter name="PKT_ADDR_L" value="144" />
  <parameter name="START_ADDRESS" value="0x0,0x0" />
  <parameter name="PKT_ADDR_H" value="207" />
  <parameter name="SECURED_RANGE_LIST" value="0,0" />
  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter name="TYPE_OF_TRANSACTION" value="both,write" />
  <parameter name="PKT_TRANS_READ" value="211" />
  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
  <parameter name="PKT_PROTECTION_L" value="239" />
  <parameter name="DEFAULT_CHANNEL" value="0" />
  <parameter name="PKT_PROTECTION_H" value="241" />
  <parameter name="SECURED_RANGE_PAIRS" value="0,0" />
  <parameter name="ST_DATA_W" value="251" />
  <parameter name="PKT_DEST_ID_L" value="236" />
  <parameter name="PKT_TRANS_WRITE" value="210" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="PKT_DEST_ID_H" value="237" />
  <parameter
     name="SLAVES_INFO"
     value="0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:write:1:0:0:1" />
  <parameter name="DESTINATION_ID" value="0,1" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="NON_SECURED_TAG" value="1,1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <parameter name="DECODER_TYPE" value="1" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_router_002.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="router_002" />
  <messages>
   <message level="Debug" culprit="top">queue size: 49 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router_002"</message>
   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=1,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=1,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NON_SECURED_TAG=1,PKT_ADDR_H=351,PKT_ADDR_L=288,PKT_DEST_ID_H=381,PKT_DEST_ID_L=380,PKT_PROTECTION_H=385,PKT_PROTECTION_L=383,PKT_TRANS_READ=355,PKT_TRANS_WRITE=354,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=1:1:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=3,ST_DATA_W=395,TYPE_OF_TRANSACTION=write"
   instancePathKey="top:.:mm_interconnect_1:.:router_003"
   kind="altera_merlin_router"
   version="14.0"
   name="top_mm_interconnect_1_router_003">
  <parameter name="END_ADDRESS" value="0x0" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter name="CHANNEL_ID" value="1" />
  <parameter name="PKT_ADDR_L" value="288" />
  <parameter name="START_ADDRESS" value="0x0" />
  <parameter name="PKT_ADDR_H" value="351" />
  <parameter name="SECURED_RANGE_LIST" value="0" />
  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter name="TYPE_OF_TRANSACTION" value="write" />
  <parameter name="PKT_TRANS_READ" value="355" />
  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
  <parameter name="PKT_PROTECTION_L" value="383" />
  <parameter name="DEFAULT_CHANNEL" value="0" />
  <parameter name="PKT_PROTECTION_H" value="385" />
  <parameter name="SECURED_RANGE_PAIRS" value="0" />
  <parameter name="ST_DATA_W" value="395" />
  <parameter name="PKT_DEST_ID_L" value="380" />
  <parameter name="PKT_TRANS_WRITE" value="354" />
  <parameter name="DEFAULT_DESTID" value="1" />
  <parameter name="PKT_DEST_ID_H" value="381" />
  <parameter name="SLAVES_INFO" value="1:1:0x0:0x0:write:1:0:0:1" />
  <parameter name="DESTINATION_ID" value="1" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="NON_SECURED_TAG" value="1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <parameter name="DECODER_TYPE" value="1" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_router_003.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="router_003,router_004" />
  <messages>
   <message level="Debug" culprit="top">queue size: 48 starting:altera_merlin_router "submodules/top_mm_interconnect_1_router_003"</message>
   <message level="Info" culprit="router_003"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_003</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_burst_adapter:14.0:ADAPTER_VERSION=13.1,AUTO_CR0_CLOCK_RATE=125000000,BURSTWRAP_CONST_MASK=1,BURSTWRAP_CONST_VALUE=1,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=1,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=224,OUT_BYTE_CNT_H=218,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_BEGIN_BURST=232,PKT_BURSTWRAP_H=224,PKT_BURSTWRAP_L=224,PKT_BURST_SIZE_H=227,PKT_BURST_SIZE_L=225,PKT_BURST_TYPE_H=229,PKT_BURST_TYPE_L=228,PKT_BYTEEN_H=143,PKT_BYTEEN_L=128,PKT_BYTE_CNT_H=223,PKT_BYTE_CNT_L=214,PKT_TRANS_COMPRESSED_READ=208,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,ST_CHANNEL_W=3,ST_DATA_W=251"
   instancePathKey="top:.:mm_interconnect_1:.:onchip_memory2_0_s1_burst_adapter"
   kind="altera_merlin_burst_adapter"
   version="14.0"
   name="altera_merlin_burst_adapter">
  <parameter name="PKT_TRANS_COMPRESSED_READ" value="208" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="AUTO_CR0_CLOCK_RATE" value="125000000" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_adapter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_wrap_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_incr_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_default_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_st_pipeline_base.v"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="top_mm_interconnect_1"
     as="onchip_memory2_0_s1_burst_adapter,pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter,pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter" />
  <instantiator
     instantiator="top_mm_interconnect_2"
     as="onchip_memory2_0_s2_burst_adapter" />
  <messages>
   <message level="Debug" culprit="top">queue size: 46 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
   <message level="Info" culprit="onchip_memory2_0_s1_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>onchip_memory2_0_s1_burst_adapter</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=3,ST_DATA_W=143,VALID_WIDTH=1"
   instancePathKey="top:.:mm_interconnect_1:.:cmd_demux"
   kind="altera_merlin_demultiplexer"
   version="14.0"
   name="top_mm_interconnect_1_cmd_demux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)" />
  <parameter name="NUM_OUTPUTS" value="1" />
  <parameter name="ST_DATA_W" value="143" />
  <parameter name="VALID_WIDTH" value="1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_demux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="cmd_demux" />
  <messages>
   <message level="Debug" culprit="top">queue size: 43 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_OUTPUTS=3,ST_CHANNEL_W=3,ST_DATA_W=251,VALID_WIDTH=1"
   instancePathKey="top:.:mm_interconnect_1:.:cmd_demux_001"
   kind="altera_merlin_demultiplexer"
   version="14.0"
   name="top_mm_interconnect_1_cmd_demux_001">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="NUM_OUTPUTS" value="3" />
  <parameter name="ST_DATA_W" value="251" />
  <parameter name="VALID_WIDTH" value="1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_demux_001.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="cmd_demux_001" />
  <messages>
   <message level="Debug" culprit="top">queue size: 42 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_cmd_demux_001"</message>
   <message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=212,ST_CHANNEL_W=3,ST_DATA_W=251,USE_EXTERNAL_ARB=0"
   instancePathKey="top:.:mm_interconnect_1:.:cmd_mux"
   kind="altera_merlin_multiplexer"
   version="14.0"
   name="top_mm_interconnect_1_cmd_mux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="PIPELINE_ARB" value="0" />
  <parameter name="NUM_INPUTS" value="2" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="ARBITRATION_SCHEME" value="round-robin" />
  <parameter name="ST_DATA_W" value="251" />
  <parameter name="PKT_TRANS_LOCK" value="212" />
  <parameter name="ARBITRATION_SHARES" value="1,1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_mux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="cmd_mux" />
  <messages>
   <message level="Debug" culprit="top">queue size: 41 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=356,ST_CHANNEL_W=3,ST_DATA_W=395,USE_EXTERNAL_ARB=0"
   instancePathKey="top:.:mm_interconnect_1:.:cmd_mux_001"
   kind="altera_merlin_multiplexer"
   version="14.0"
   name="top_mm_interconnect_1_cmd_mux_001">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="PIPELINE_ARB" value="0" />
  <parameter name="NUM_INPUTS" value="1" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="ARBITRATION_SCHEME" value="round-robin" />
  <parameter name="ST_DATA_W" value="395" />
  <parameter name="PKT_TRANS_LOCK" value="356" />
  <parameter name="ARBITRATION_SHARES" value="1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_mux_001.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="cmd_mux_001,cmd_mux_002" />
  <messages>
   <message level="Debug" culprit="top">queue size: 40 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_cmd_mux_001"</message>
   <message level="Info" culprit="cmd_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_001</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_OUTPUTS=2,ST_CHANNEL_W=3,ST_DATA_W=251,VALID_WIDTH=1"
   instancePathKey="top:.:mm_interconnect_1:.:rsp_demux"
   kind="altera_merlin_demultiplexer"
   version="14.0"
   name="top_mm_interconnect_1_rsp_demux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="NUM_OUTPUTS" value="2" />
  <parameter name="ST_DATA_W" value="251" />
  <parameter name="VALID_WIDTH" value="1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_demux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="rsp_demux" />
  <messages>
   <message level="Debug" culprit="top">queue size: 38 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_rsp_demux"</message>
   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0),NUM_OUTPUTS=1,ST_CHANNEL_W=3,ST_DATA_W=395,VALID_WIDTH=1"
   instancePathKey="top:.:mm_interconnect_1:.:rsp_demux_001"
   kind="altera_merlin_demultiplexer"
   version="14.0"
   name="top_mm_interconnect_1_rsp_demux_001">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(394:392) response_status(391:390) cache(389:386) protection(385:383) thread_id(382) dest_id(381:380) src_id(379:378) qos(377) begin_burst(376) data_sideband(375) addr_sideband(374) burst_type(373:372) burst_size(371:369) burstwrap(368) byte_cnt(367:358) trans_exclusive(357) trans_lock(356) trans_read(355) trans_write(354) trans_posted(353) trans_compressed_read(352) addr(351:288) byteen(287:256) data(255:0)" />
  <parameter name="NUM_OUTPUTS" value="1" />
  <parameter name="ST_DATA_W" value="395" />
  <parameter name="VALID_WIDTH" value="1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_demux_001.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="rsp_demux_001,rsp_demux_002" />
  <messages>
   <message level="Debug" culprit="top">queue size: 37 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_1_rsp_demux_001"</message>
   <message level="Info" culprit="rsp_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_001</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=104,ST_CHANNEL_W=3,ST_DATA_W=143,USE_EXTERNAL_ARB=0"
   instancePathKey="top:.:mm_interconnect_1:.:rsp_mux"
   kind="altera_merlin_multiplexer"
   version="14.0"
   name="top_mm_interconnect_1_rsp_mux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="PIPELINE_ARB" value="0" />
  <parameter name="NUM_INPUTS" value="1" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="ARBITRATION_SCHEME" value="no-arb" />
  <parameter name="ST_DATA_W" value="143" />
  <parameter name="PKT_TRANS_LOCK" value="104" />
  <parameter name="ARBITRATION_SHARES" value="1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_mux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="rsp_mux" />
  <messages>
   <message level="Debug" culprit="top">queue size: 35 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_INPUTS=3,PIPELINE_ARB=0,PKT_TRANS_LOCK=212,ST_CHANNEL_W=3,ST_DATA_W=251,USE_EXTERNAL_ARB=0"
   instancePathKey="top:.:mm_interconnect_1:.:rsp_mux_001"
   kind="altera_merlin_multiplexer"
   version="14.0"
   name="top_mm_interconnect_1_rsp_mux_001">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="PIPELINE_ARB" value="0" />
  <parameter name="NUM_INPUTS" value="3" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="ARBITRATION_SCHEME" value="no-arb" />
  <parameter name="ST_DATA_W" value="251" />
  <parameter name="PKT_TRANS_LOCK" value="212" />
  <parameter name="ARBITRATION_SHARES" value="1,1,1" />
  <parameter name="ST_CHANNEL_W" value="3" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_mux_001.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_1" as="rsp_mux_001" />
  <messages>
   <message level="Debug" culprit="top">queue size: 34 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_1_rsp_mux_001"</message>
   <message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_width_adapter:14.0:AUTO_CLK_CLOCK_RATE=125000000,COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),IN_PKT_ADDR_H=99,IN_PKT_ADDR_L=36,IN_PKT_BURSTWRAP_H=116,IN_PKT_BURSTWRAP_L=116,IN_PKT_BURST_SIZE_H=119,IN_PKT_BURST_SIZE_L=117,IN_PKT_BURST_TYPE_H=121,IN_PKT_BURST_TYPE_L=120,IN_PKT_BYTEEN_H=35,IN_PKT_BYTEEN_L=32,IN_PKT_BYTE_CNT_H=115,IN_PKT_BYTE_CNT_L=106,IN_PKT_DATA_H=31,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=142,IN_PKT_ORI_BURST_SIZE_L=140,IN_PKT_RESPONSE_STATUS_H=139,IN_PKT_RESPONSE_STATUS_L=138,IN_PKT_TRANS_COMPRESSED_READ=100,IN_PKT_TRANS_EXCLUSIVE=105,IN_ST_DATA_W=143,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),OUT_PKT_ADDR_H=207,OUT_PKT_ADDR_L=144,OUT_PKT_BURST_SIZE_H=227,OUT_PKT_BURST_SIZE_L=225,OUT_PKT_BURST_TYPE_H=229,OUT_PKT_BURST_TYPE_L=228,OUT_PKT_BYTEEN_H=143,OUT_PKT_BYTEEN_L=128,OUT_PKT_BYTE_CNT_H=223,OUT_PKT_BYTE_CNT_L=214,OUT_PKT_DATA_H=127,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=250,OUT_PKT_ORI_BURST_SIZE_L=248,OUT_PKT_RESPONSE_STATUS_H=247,OUT_PKT_RESPONSE_STATUS_L=246,OUT_PKT_TRANS_COMPRESSED_READ=208,OUT_PKT_TRANS_EXCLUSIVE=213,OUT_ST_DATA_W=251,PACKING=1,RESPONSE_PATH=0,ST_CHANNEL_W=3"
   instancePathKey="top:.:mm_interconnect_1:.:pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter"
   kind="altera_merlin_width_adapter"
   version="14.0"
   name="altera_merlin_width_adapter">
  <parameter name="OUT_PKT_ORI_BURST_SIZE_H" value="250" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="OUT_MERLIN_PACKET_FORMAT"
     value="ori_burst_size(250:248) response_status(247:246) cache(245:242) protection(241:239) thread_id(238) dest_id(237:236) src_id(235:234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="OUT_PKT_ORI_BURST_SIZE_L" value="248" />
  <parameter
     name="IN_MERLIN_PACKET_FORMAT"
     value="ori_burst_size(142:140) response_status(139:138) cache(137:134) protection(133:131) thread_id(130) dest_id(129:128) src_id(127:126) qos(125) begin_burst(124) data_sideband(123) addr_sideband(122) burst_type(121:120) burst_size(119:117) burstwrap(116) byte_cnt(115:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)" />
  <parameter name="IN_PKT_ORI_BURST_SIZE_H" value="142" />
  <parameter name="IN_PKT_ORI_BURST_SIZE_L" value="140" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_width_adapter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="top_mm_interconnect_1"
     as="pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter,pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter,pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter,onchip_memory2_0_s1_to_pcie_256_hip_avmm_0_Rxm_BAR2_rsp_width_adapter,pcie_256_hip_avmm_0_wr_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter,pcie_256_hip_avmm_0_rd_dts_slave_to_pcie_256_hip_avmm_0_dma_rd_master_rsp_width_adapter" />
  <messages>
   <message level="Debug" culprit="top">queue size: 33 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
   <message
       level="Info"
       culprit="pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x1000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NON_SECURED_TAG=1,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_DEST_ID_H=235,PKT_DEST_ID_L=235,PKT_PROTECTION_H=239,PKT_PROTECTION_L=237,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x1000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=1,ST_DATA_W=249,TYPE_OF_TRANSACTION=both"
   instancePathKey="top:.:mm_interconnect_2:.:router"
   kind="altera_merlin_router"
   version="14.0"
   name="top_mm_interconnect_2_router">
  <parameter name="END_ADDRESS" value="0x1000" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter name="CHANNEL_ID" value="1" />
  <parameter name="PKT_ADDR_L" value="144" />
  <parameter name="START_ADDRESS" value="0x0" />
  <parameter name="PKT_ADDR_H" value="207" />
  <parameter name="SECURED_RANGE_LIST" value="0" />
  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter name="TYPE_OF_TRANSACTION" value="both" />
  <parameter name="PKT_TRANS_READ" value="211" />
  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
  <parameter name="PKT_PROTECTION_L" value="237" />
  <parameter name="DEFAULT_CHANNEL" value="0" />
  <parameter name="PKT_PROTECTION_H" value="239" />
  <parameter name="SECURED_RANGE_PAIRS" value="0" />
  <parameter name="ST_DATA_W" value="249" />
  <parameter name="PKT_DEST_ID_L" value="235" />
  <parameter name="PKT_TRANS_WRITE" value="210" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="PKT_DEST_ID_H" value="235" />
  <parameter name="SLAVES_INFO" value="0:1:0x0:0x1000:both:1:0:0:1" />
  <parameter name="DESTINATION_ID" value="0" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="NON_SECURED_TAG" value="1" />
  <parameter name="ST_CHANNEL_W" value="1" />
  <parameter name="DECODER_TYPE" value="0" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2_router.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_2" as="router" />
  <messages>
   <message level="Debug" culprit="top">queue size: 22 starting:altera_merlin_router "submodules/top_mm_interconnect_2_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NON_SECURED_TAG=1,PKT_ADDR_H=207,PKT_ADDR_L=144,PKT_DEST_ID_H=235,PKT_DEST_ID_L=235,PKT_PROTECTION_H=239,PKT_PROTECTION_L=237,PKT_TRANS_READ=211,PKT_TRANS_WRITE=210,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=1,ST_DATA_W=249,TYPE_OF_TRANSACTION=read"
   instancePathKey="top:.:mm_interconnect_2:.:router_001"
   kind="altera_merlin_router"
   version="14.0"
   name="top_mm_interconnect_2_router_001">
  <parameter name="END_ADDRESS" value="0x0" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter name="CHANNEL_ID" value="1" />
  <parameter name="PKT_ADDR_L" value="144" />
  <parameter name="START_ADDRESS" value="0x0" />
  <parameter name="PKT_ADDR_H" value="207" />
  <parameter name="SECURED_RANGE_LIST" value="0" />
  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter name="TYPE_OF_TRANSACTION" value="read" />
  <parameter name="PKT_TRANS_READ" value="211" />
  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
  <parameter name="PKT_PROTECTION_L" value="237" />
  <parameter name="DEFAULT_CHANNEL" value="0" />
  <parameter name="PKT_PROTECTION_H" value="239" />
  <parameter name="SECURED_RANGE_PAIRS" value="0" />
  <parameter name="ST_DATA_W" value="249" />
  <parameter name="PKT_DEST_ID_L" value="235" />
  <parameter name="PKT_TRANS_WRITE" value="210" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="PKT_DEST_ID_H" value="235" />
  <parameter name="SLAVES_INFO" value="0:1:0x0:0x0:read:1:0:0:1" />
  <parameter name="DESTINATION_ID" value="0" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="NON_SECURED_TAG" value="1" />
  <parameter name="ST_CHANNEL_W" value="1" />
  <parameter name="DECODER_TYPE" value="1" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2_router_001.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_2" as="router_001" />
  <messages>
   <message level="Debug" culprit="top">queue size: 21 starting:altera_merlin_router "submodules/top_mm_interconnect_2_router_001"</message>
   <message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_OUTPUTS=1,ST_CHANNEL_W=1,ST_DATA_W=249,VALID_WIDTH=1"
   instancePathKey="top:.:mm_interconnect_2:.:cmd_demux"
   kind="altera_merlin_demultiplexer"
   version="14.0"
   name="top_mm_interconnect_2_cmd_demux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="NUM_OUTPUTS" value="1" />
  <parameter name="ST_DATA_W" value="249" />
  <parameter name="VALID_WIDTH" value="1" />
  <parameter name="ST_CHANNEL_W" value="1" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2_cmd_demux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_2" as="cmd_demux,rsp_demux" />
  <messages>
   <message level="Debug" culprit="top">queue size: 19 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_2_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=212,ST_CHANNEL_W=1,ST_DATA_W=249,USE_EXTERNAL_ARB=0"
   instancePathKey="top:.:mm_interconnect_2:.:cmd_mux"
   kind="altera_merlin_multiplexer"
   version="14.0"
   name="top_mm_interconnect_2_cmd_mux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="PIPELINE_ARB" value="0" />
  <parameter name="NUM_INPUTS" value="1" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="ARBITRATION_SCHEME" value="round-robin" />
  <parameter name="ST_DATA_W" value="249" />
  <parameter name="PKT_TRANS_LOCK" value="212" />
  <parameter name="ARBITRATION_SHARES" value="1" />
  <parameter name="ST_CHANNEL_W" value="1" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2_cmd_mux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_2" as="cmd_mux" />
  <messages>
   <message level="Debug" culprit="top">queue size: 18 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_2_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=212,ST_CHANNEL_W=1,ST_DATA_W=249,USE_EXTERNAL_ARB=0"
   instancePathKey="top:.:mm_interconnect_2:.:rsp_mux"
   kind="altera_merlin_multiplexer"
   version="14.0"
   name="top_mm_interconnect_2_rsp_mux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="PIPELINE_ARB" value="0" />
  <parameter name="NUM_INPUTS" value="1" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(248:246) response_status(245:244) cache(243:240) protection(239:237) thread_id(236) dest_id(235) src_id(234) qos(233) begin_burst(232) data_sideband(231) addr_sideband(230) burst_type(229:228) burst_size(227:225) burstwrap(224) byte_cnt(223:214) trans_exclusive(213) trans_lock(212) trans_read(211) trans_write(210) trans_posted(209) trans_compressed_read(208) addr(207:144) byteen(143:128) data(127:0)" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="ARBITRATION_SCHEME" value="no-arb" />
  <parameter name="ST_DATA_W" value="249" />
  <parameter name="PKT_TRANS_LOCK" value="212" />
  <parameter name="ARBITRATION_SHARES" value="1" />
  <parameter name="ST_CHANNEL_W" value="1" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_2_rsp_mux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_2" as="rsp_mux" />
  <messages>
   <message level="Debug" culprit="top">queue size: 16 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_2_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x100000000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_DEST_ID_H=120,PKT_DEST_ID_L=120,PKT_PROTECTION_H=124,PKT_PROTECTION_L=122,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x100000000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=2,ST_DATA_W=134,TYPE_OF_TRANSACTION=both"
   instancePathKey="top:.:mm_interconnect_3:.:router"
   kind="altera_merlin_router"
   version="14.0"
   name="top_mm_interconnect_3_router">
  <parameter name="END_ADDRESS" value="0x100000000" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter name="CHANNEL_ID" value="1" />
  <parameter name="PKT_ADDR_L" value="36" />
  <parameter name="START_ADDRESS" value="0x0" />
  <parameter name="PKT_ADDR_H" value="99" />
  <parameter name="SECURED_RANGE_LIST" value="0" />
  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter name="TYPE_OF_TRANSACTION" value="both" />
  <parameter name="PKT_TRANS_READ" value="103" />
  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
  <parameter name="PKT_PROTECTION_L" value="122" />
  <parameter name="DEFAULT_CHANNEL" value="0" />
  <parameter name="PKT_PROTECTION_H" value="124" />
  <parameter name="SECURED_RANGE_PAIRS" value="0" />
  <parameter name="ST_DATA_W" value="134" />
  <parameter name="PKT_DEST_ID_L" value="120" />
  <parameter name="PKT_TRANS_WRITE" value="102" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="PKT_DEST_ID_H" value="120" />
  <parameter name="SLAVES_INFO" value="0:1:0x0:0x100000000:both:1:0:0:1" />
  <parameter name="DESTINATION_ID" value="0" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="NON_SECURED_TAG" value="1" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="DECODER_TYPE" value="0" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_router.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_3" as="router,router_001" />
  <messages>
   <message level="Debug" culprit="top">queue size: 8 starting:altera_merlin_router "submodules/top_mm_interconnect_3_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:14.0:AUTO_CLK_CLOCK_RATE=125000000,CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=1,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=1,0,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=99,PKT_ADDR_L=36,PKT_DEST_ID_H=120,PKT_DEST_ID_L=120,PKT_PROTECTION_H=124,PKT_PROTECTION_L=122,PKT_TRANS_READ=103,PKT_TRANS_WRITE=102,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=1:01:0x0:0x0:both:1:0:0:1,0:10:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=2,ST_DATA_W=134,TYPE_OF_TRANSACTION=both,both"
   instancePathKey="top:.:mm_interconnect_3:.:router_002"
   kind="altera_merlin_router"
   version="14.0"
   name="top_mm_interconnect_3_router_002">
  <parameter name="END_ADDRESS" value="0x0,0x0" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter name="CHANNEL_ID" value="01,10" />
  <parameter name="PKT_ADDR_L" value="36" />
  <parameter name="START_ADDRESS" value="0x0,0x0" />
  <parameter name="PKT_ADDR_H" value="99" />
  <parameter name="SECURED_RANGE_LIST" value="0,0" />
  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter name="TYPE_OF_TRANSACTION" value="both,both" />
  <parameter name="PKT_TRANS_READ" value="103" />
  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
  <parameter name="PKT_PROTECTION_L" value="122" />
  <parameter name="DEFAULT_CHANNEL" value="0" />
  <parameter name="PKT_PROTECTION_H" value="124" />
  <parameter name="SECURED_RANGE_PAIRS" value="0,0" />
  <parameter name="ST_DATA_W" value="134" />
  <parameter name="PKT_DEST_ID_L" value="120" />
  <parameter name="PKT_TRANS_WRITE" value="102" />
  <parameter name="DEFAULT_DESTID" value="1" />
  <parameter name="PKT_DEST_ID_H" value="120" />
  <parameter
     name="SLAVES_INFO"
     value="1:01:0x0:0x0:both:1:0:0:1,0:10:0x0:0x0:both:1:0:0:1" />
  <parameter name="DESTINATION_ID" value="1,0" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="NON_SECURED_TAG" value="1,1" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="DECODER_TYPE" value="1" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_router_002.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_3" as="router_002" />
  <messages>
   <message level="Debug" culprit="top">queue size: 6 starting:altera_merlin_router "submodules/top_mm_interconnect_3_router_002"</message>
   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=2,ST_DATA_W=134,VALID_WIDTH=1"
   instancePathKey="top:.:mm_interconnect_3:.:cmd_demux"
   kind="altera_merlin_demultiplexer"
   version="14.0"
   name="top_mm_interconnect_3_cmd_demux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)" />
  <parameter name="NUM_OUTPUTS" value="1" />
  <parameter name="ST_DATA_W" value="134" />
  <parameter name="VALID_WIDTH" value="1" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_cmd_demux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_3" as="cmd_demux,cmd_demux_001" />
  <messages>
   <message level="Debug" culprit="top">queue size: 5 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_3_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=104,ST_CHANNEL_W=2,ST_DATA_W=134,USE_EXTERNAL_ARB=0"
   instancePathKey="top:.:mm_interconnect_3:.:cmd_mux"
   kind="altera_merlin_multiplexer"
   version="14.0"
   name="top_mm_interconnect_3_cmd_mux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="PIPELINE_ARB" value="0" />
  <parameter name="NUM_INPUTS" value="2" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="ARBITRATION_SCHEME" value="round-robin" />
  <parameter name="ST_DATA_W" value="134" />
  <parameter name="PKT_TRANS_LOCK" value="104" />
  <parameter name="ARBITRATION_SHARES" value="1,1" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_cmd_mux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_3" as="cmd_mux" />
  <messages>
   <message level="Debug" culprit="top">queue size: 3 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_3_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_demultiplexer:14.0:AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=2,ST_DATA_W=134,VALID_WIDTH=1"
   instancePathKey="top:.:mm_interconnect_3:.:rsp_demux"
   kind="altera_merlin_demultiplexer"
   version="14.0"
   name="top_mm_interconnect_3_rsp_demux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)" />
  <parameter name="NUM_OUTPUTS" value="2" />
  <parameter name="ST_DATA_W" value="134" />
  <parameter name="VALID_WIDTH" value="1" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_rsp_demux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_3" as="rsp_demux" />
  <messages>
   <message level="Debug" culprit="top">queue size: 2 starting:altera_merlin_demultiplexer "submodules/top_mm_interconnect_3_rsp_demux"</message>
   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_multiplexer:14.0:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,AUTO_CLK_CLOCK_RATE=125000000,AUTO_DEVICE_FAMILY=Arria V,MERLIN_PACKET_FORMAT=ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=104,ST_CHANNEL_W=2,ST_DATA_W=134,USE_EXTERNAL_ARB=0"
   instancePathKey="top:.:mm_interconnect_3:.:rsp_mux"
   kind="altera_merlin_multiplexer"
   version="14.0"
   name="top_mm_interconnect_3_rsp_mux">
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
  <parameter name="PIPELINE_ARB" value="0" />
  <parameter name="NUM_INPUTS" value="1" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(133:131) response_status(130:129) cache(128:125) protection(124:122) thread_id(121) dest_id(120) src_id(119) qos(118) begin_burst(117) data_sideband(116) addr_sideband(115) burst_type(114:113) burst_size(112:110) burstwrap(109) byte_cnt(108:106) trans_exclusive(105) trans_lock(104) trans_read(103) trans_write(102) trans_posted(101) trans_compressed_read(100) addr(99:36) byteen(35:32) data(31:0)" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="ARBITRATION_SCHEME" value="no-arb" />
  <parameter name="ST_DATA_W" value="134" />
  <parameter name="PKT_TRANS_LOCK" value="104" />
  <parameter name="ARBITRATION_SHARES" value="1" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <generatedFiles>
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG" />
   <file
       path="/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/top_mm_interconnect_3_rsp_mux.sv"
       type="SYSTEM_VERILOG" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools_archive/acds/14.0/200/linux64/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="top_mm_interconnect_3" as="rsp_mux,rsp_mux_001" />
  <messages>
   <message level="Debug" culprit="top">queue size: 1 starting:altera_merlin_multiplexer "submodules/top_mm_interconnect_3_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
</deploy>
