Archive Project report for top
Wed Aug  6 13:20:40 2014
Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Archive Project Summary
  3. Archive Project Messages
  4. Files Archived



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+----------------------------------------------------------------+
; Archive Project Summary                                        ;
+------------------------+---------------------------------------+
; Archive Project Status ; Successful - Wed Aug  6 13:20:40 2014 ;
; Revision Name          ; top                                   ;
; Top-level Entity Name  ; top_hw                                ;
; Family                 ; Arria V                               ;
+------------------------+---------------------------------------+


+--------------------------+
; Archive Project Messages ;
+--------------------------+
Info: File Set 'Custom' contains:
    Info: Programming output files
    Info: Automatically detected source files
    Info: Project source and settings files
Info: Archive will store files relative to the closest common parent directory
Info (13213): Using common directory /data/kichan/Builds/14.0/b200/av_x4_g2_5AGXFB3H4F35C5_avmm_dma_stkit/
Info: ----------------------------------------------------------
Info: ----------------------------------------------------------
Info: Generated archive '/data/kichan/Builds/14.0/b200/av_x4_g2_5AGXFB3H4F35C5_avmm_dma_stkit/top.qar'
Info: ----------------------------------------------------------
Info: ----------------------------------------------------------
Info: Generated report 'top.archive.rpt'
Info (23030): Evaluation of Tcl script /tools/altera/14.0/200/linux64/quartus/common/tcl/apps/qpm/qar.tcl was successful
Info: Quartus II 64-Bit Shell was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 902 megabytes
    Info: Processing ended: Wed Aug  6 13:20:40 2014
    Info: Elapsed time: 00:00:13
    Info: Total CPU time (on all processors): 00:00:09


+----------------------------------------------------------------------------------------+
; Files Archived                                                                         ;
+----------------------------------------------------------------------------------------+
; File Name                                                                              ;
+----------------------------------------------------------------------------------------+
; /data/kichan/Builds/14.0/b200/cv_x4_g2_5CGTFD9E5F35C7_avmm_dma/quartus.ini             ;
; assignment_defaults.qdf                                                                ;
; hip_status_av_hw.tcl                                                                   ;
; pcie_lib/synthesis/../../top.qsys                                                      ;
; pcie_lib/synthesis/../../top.sopcinfo                                                  ;
; pcie_lib/synthesis/../top.cmp                                                          ;
; pcie_lib/synthesis/submodules/alt_arbiter_acq.sv                                       ;
; pcie_lib/synthesis/submodules/alt_reset_ctrl_lego.sv                                   ;
; pcie_lib/synthesis/submodules/alt_reset_ctrl_tgx_cdrauto.sv                            ;
; pcie_lib/synthesis/submodules/alt_xcvr_arbiter.sv                                      ;
; pcie_lib/synthesis/submodules/alt_xcvr_csr_common.sv                                   ;
; pcie_lib/synthesis/submodules/alt_xcvr_csr_common_h.sv                                 ;
; pcie_lib/synthesis/submodules/alt_xcvr_csr_pcs8g.sv                                    ;
; pcie_lib/synthesis/submodules/alt_xcvr_csr_pcs8g_h.sv                                  ;
; pcie_lib/synthesis/submodules/alt_xcvr_csr_selector.sv                                 ;
; pcie_lib/synthesis/submodules/alt_xcvr_m2s.sv                                          ;
; pcie_lib/synthesis/submodules/alt_xcvr_mgmt2dec.sv                                     ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig.sv                                     ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_adce.sv                                ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_analog.sv                              ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_analog_av.sv                           ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_basic.sv                               ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cal_seq.sv                             ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu.v                                  ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_irq_mapper.sv                      ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0.v                ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux.sv     ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux_001.sv ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux.sv       ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux_001.sv   ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv        ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv    ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv    ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv    ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux.sv       ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux_001.sv   ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_ram.hex                            ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_ram.sv                             ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu.v                     ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif          ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif          ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench.v          ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_dcd.sv                                 ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_dcd_av.sv                              ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_dcd_cal_av.sv                          ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_dcd_control_av.sv                      ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_dfe.sv                                 ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_direct.sv                              ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_eyemon.sv                              ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_h.sv                                   ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_mif.sv                                 ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_offset_cancellation.sv                 ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_offset_cancellation_av.sv              ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_pll.sv                                 ;
; pcie_lib/synthesis/submodules/alt_xcvr_reconfig_soc.sv                                 ;
; pcie_lib/synthesis/submodules/alt_xcvr_resync.sv                                       ;
; pcie_lib/synthesis/submodules/alt_xreconf_analog_ctrlsm.sv                             ;
; pcie_lib/synthesis/submodules/alt_xreconf_analog_datactrl_av.sv                        ;
; pcie_lib/synthesis/submodules/alt_xreconf_analog_rmw_av.sv                             ;
; pcie_lib/synthesis/submodules/alt_xreconf_basic_acq.sv                                 ;
; pcie_lib/synthesis/submodules/alt_xreconf_cif.sv                                       ;
; pcie_lib/synthesis/submodules/alt_xreconf_uif.sv                                       ;
; pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v                                  ;
; pcie_lib/synthesis/submodules/altera_avalon_st_pipeline_base.v                         ;
; pcie_lib/synthesis/submodules/altera_avalon_st_pipeline_stage.sv                       ;
; pcie_lib/synthesis/submodules/altera_default_burst_converter.sv                        ;
; pcie_lib/synthesis/submodules/altera_incr_burst_converter.sv                           ;
; pcie_lib/synthesis/submodules/altera_merlin_address_alignment.sv                       ;
; pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv                              ;
; pcie_lib/synthesis/submodules/altera_merlin_burst_adapter.sv                           ;
; pcie_lib/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv                      ;
; pcie_lib/synthesis/submodules/altera_merlin_burst_adapter_new.sv                       ;
; pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv                      ;
; pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv                            ;
; pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv                       ;
; pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv                             ;
; pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv                        ;
; pcie_lib/synthesis/submodules/altera_merlin_width_adapter.sv                           ;
; pcie_lib/synthesis/submodules/altera_pcie_sv_hip_ast_pipen1b.sdc                       ;
; pcie_lib/synthesis/submodules/altera_pcie_sv_hip_ast_rs_serdes.sdc                     ;
; pcie_lib/synthesis/submodules/altera_reset_controller.sdc                              ;
; pcie_lib/synthesis/submodules/altera_reset_controller.v                                ;
; pcie_lib/synthesis/submodules/altera_reset_synchronizer.v                              ;
; pcie_lib/synthesis/submodules/altera_wait_generate.v                                   ;
; pcie_lib/synthesis/submodules/altera_wrap_burst_converter.sv                           ;
; pcie_lib/synthesis/submodules/altera_xcvr_functions.sv                                 ;
; pcie_lib/synthesis/submodules/altpcie_256_hip_avmm_hwtcl.v                             ;
; pcie_lib/synthesis/submodules/altpcie_av_hip_128bit_atom.v                             ;
; pcie_lib/synthesis/submodules/altpcie_av_hip_ast_hwtcl.v                               ;
; pcie_lib/synthesis/submodules/altpcie_cv_hip_ast_hwtcl.v                               ;
; pcie_lib/synthesis/submodules/altpcie_dynamic_control.sv                               ;
; pcie_lib/synthesis/submodules/altpcie_fifo.sv                                          ;
; pcie_lib/synthesis/submodules/altpcie_reconfig_driver.sv                               ;
; pcie_lib/synthesis/submodules/altpcie_rs_hip.v                                         ;
; pcie_lib/synthesis/submodules/altpcie_rs_serdes.v                                      ;
; pcie_lib/synthesis/submodules/altpcieav_256_app.sv                                     ;
; pcie_lib/synthesis/submodules/altpcieav_arbiter.sv                                     ;
; pcie_lib/synthesis/submodules/altpcieav_cra.sv                                         ;
; pcie_lib/synthesis/submodules/altpcieav_dma_hprxm.sv                                   ;
; pcie_lib/synthesis/submodules/altpcieav_dma_hprxm_cpl.sv                               ;
; pcie_lib/synthesis/submodules/altpcieav_dma_hprxm_rdwr.sv                              ;
; pcie_lib/synthesis/submodules/altpcieav_dma_hprxm_txctrl.sv                            ;
; pcie_lib/synthesis/submodules/altpcieav_dma_rd.sv                                      ;
; pcie_lib/synthesis/submodules/altpcieav_dma_rxm.sv                                     ;
; pcie_lib/synthesis/submodules/altpcieav_dma_txs.sv                                     ;
; pcie_lib/synthesis/submodules/altpcieav_dma_wr.sv                                      ;
; pcie_lib/synthesis/submodules/altpcieav_hip_interface.sv                               ;
; pcie_lib/synthesis/submodules/altpcied_sriov_cfg_vf_mux.v                              ;
; pcie_lib/synthesis/submodules/altpcierd_hip_rs.v                                       ;
; pcie_lib/synthesis/submodules/av_hssi_8g_rx_pcs_rbc.sv                                 ;
; pcie_lib/synthesis/submodules/av_hssi_8g_tx_pcs_rbc.sv                                 ;
; pcie_lib/synthesis/submodules/av_hssi_common_pcs_pma_interface_rbc.sv                  ;
; pcie_lib/synthesis/submodules/av_hssi_common_pld_pcs_interface_rbc.sv                  ;
; pcie_lib/synthesis/submodules/av_hssi_pipe_gen1_2_rbc.sv                               ;
; pcie_lib/synthesis/submodules/av_hssi_rx_pcs_pma_interface_rbc.sv                      ;
; pcie_lib/synthesis/submodules/av_hssi_rx_pld_pcs_interface_rbc.sv                      ;
; pcie_lib/synthesis/submodules/av_hssi_tx_pcs_pma_interface_rbc.sv                      ;
; pcie_lib/synthesis/submodules/av_hssi_tx_pld_pcs_interface_rbc.sv                      ;
; pcie_lib/synthesis/submodules/av_pcs.sv                                                ;
; pcie_lib/synthesis/submodules/av_pcs_ch.sv                                             ;
; pcie_lib/synthesis/submodules/av_pma.sv                                                ;
; pcie_lib/synthesis/submodules/av_reconfig_bundle_to_basic.sv                           ;
; pcie_lib/synthesis/submodules/av_reconfig_bundle_to_xcvr.sv                            ;
; pcie_lib/synthesis/submodules/av_rx_pma.sv                                             ;
; pcie_lib/synthesis/submodules/av_tx_pma.sv                                             ;
; pcie_lib/synthesis/submodules/av_tx_pma_ch.sv                                          ;
; pcie_lib/synthesis/submodules/av_xcvr_avmm.sv                                          ;
; pcie_lib/synthesis/submodules/av_xcvr_avmm_csr.sv                                      ;
; pcie_lib/synthesis/submodules/av_xcvr_data_adapter.sv                                  ;
; pcie_lib/synthesis/submodules/av_xcvr_emsip_adapter.sv                                 ;
; pcie_lib/synthesis/submodules/av_xcvr_h.sv                                             ;
; pcie_lib/synthesis/submodules/av_xcvr_native.sv                                        ;
; pcie_lib/synthesis/submodules/av_xcvr_pipe_native.sv                                   ;
; pcie_lib/synthesis/submodules/av_xcvr_pipe_native_hip.sv                               ;
; pcie_lib/synthesis/submodules/av_xcvr_plls.sv                                          ;
; pcie_lib/synthesis/submodules/av_xcvr_reconfig.sdc                                     ;
; pcie_lib/synthesis/submodules/av_xcvr_reconfig_basic.sv                                ;
; pcie_lib/synthesis/submodules/av_xcvr_reconfig_mif.sv                                  ;
; pcie_lib/synthesis/submodules/av_xcvr_reconfig_mif_avmm.sv                             ;
; pcie_lib/synthesis/submodules/av_xcvr_reconfig_mif_ctrl.sv                             ;
; pcie_lib/synthesis/submodules/av_xcvr_reconfig_pll.sv                                  ;
; pcie_lib/synthesis/submodules/av_xcvr_reconfig_pll_ctrl.sv                             ;
; pcie_lib/synthesis/submodules/av_xrbasic_l2p_addr.sv                                   ;
; pcie_lib/synthesis/submodules/av_xrbasic_l2p_ch.sv                                     ;
; pcie_lib/synthesis/submodules/av_xrbasic_l2p_rom.sv                                    ;
; pcie_lib/synthesis/submodules/av_xrbasic_lif.sv                                        ;
; pcie_lib/synthesis/submodules/av_xrbasic_lif_csr.sv                                    ;
; pcie_lib/synthesis/submodules/dma_controller.sv                                        ;
; pcie_lib/synthesis/submodules/plain_files.txt                                          ;
; pcie_lib/synthesis/submodules/qencrypt_files.txt                                       ;
; pcie_lib/synthesis/submodules/sv_reconfig_bundle_merger.sv                             ;
; pcie_lib/synthesis/submodules/sv_reconfig_bundle_to_basic.sv                           ;
; pcie_lib/synthesis/submodules/sv_reconfig_bundle_to_ip.sv                              ;
; pcie_lib/synthesis/submodules/sv_reconfig_bundle_to_xcvr.sv                            ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1.v                                  ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_demux.sv                       ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_demux_001.sv                   ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_mux.sv                         ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_cmd_mux_001.sv                     ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_router.sv                          ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_router_001.sv                      ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_router_002.sv                      ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_router_003.sv                      ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_demux.sv                       ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_demux_001.sv                   ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_mux.sv                         ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_1_rsp_mux_001.sv                     ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_2.v                                  ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_2_cmd_demux.sv                       ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_2_cmd_mux.sv                         ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_2_router.sv                          ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_2_router_001.sv                      ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_2_rsp_mux.sv                         ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_3.v                                  ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_3_cmd_demux.sv                       ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_3_cmd_mux.sv                         ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_3_router.sv                          ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_3_router_002.sv                      ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_3_rsp_demux.sv                       ;
; pcie_lib/synthesis/submodules/top_mm_interconnect_3_rsp_mux.sv                         ;
; pcie_lib/synthesis/submodules/top_onchip_memory2_0.hex                                 ;
; pcie_lib/synthesis/submodules/top_onchip_memory2_0.v                                   ;
; pcie_lib/synthesis/top.debuginfo                                                       ;
; pcie_lib/synthesis/top.qip                                                             ;
; pcie_lib/synthesis/top.v                                                               ;
; pcie_quartus_files/top.jdi                                                             ;
; pcie_quartus_files/top.sof                                                             ;
; qii_av_cvp.tcl                                                                         ;
; qii_pinout.tcl                                                                         ;
; qii_pinout_5AGTFD7K3F40I3.tcl                                                          ;
; qii_pinout_revb_board.tcl                                                              ;
; qii_pinout_stkit.tcl                                                                   ;
; qii_seed_sweep.tcl                                                                     ;
; qsys_script.tcl                                                                        ;
; sv_qsys_upd.tcl                                                                        ;
; top.cof                                                                                ;
; top.qpf                                                                                ;
; top.qsf                                                                                ;
; top_hw.sdc                                                                             ;
; top_hw.v                                                                               ;
+----------------------------------------------------------------------------------------+


