Info: Starting: Create block symbol file (.bsf)
Info: ip-generate --project-directory=/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit --output-directory=/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib --report-file=bsf:/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/top.bsf --system-info=DEVICE_FAMILY="Arria V" --system-info=DEVICE=5AGXFB3H4F35C5 --system-info=DEVICE_SPEEDGRADE=5_H4 --component-file=/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/top.qsys
Progress: Loading av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/top.qsys
Progress: Reading input file
Progress: Adding pcie_reconfig_driver_0 [altera_pcie_reconfig_driver 14.0]
Progress: Parameterizing module pcie_reconfig_driver_0
Progress: Adding alt_xcvr_reconfig_0 [alt_xcvr_reconfig 14.0]
Progress: Parameterizing module alt_xcvr_reconfig_0
Progress: Adding clk_0 [clock_source 14.0]
Progress: Parameterizing module clk_0
Progress: Adding pcie_256_hip_avmm_0 [altera_pcie_256_hip_avmm 14.0]
Progress: Parameterizing module pcie_256_hip_avmm_0
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 14.0]
Progress: Parameterizing module onchip_memory2_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: top.top: There are recommended upgrades for: pcie_256_hip_avmm_0
Info: top.alt_xcvr_reconfig_0: reconfig_from_xcvr port width is 5*46 bits
Info: top.alt_xcvr_reconfig_0: reconfig_to_xcvr port width is 5*70 bits
Warning: top.pcie_256_hip_avmm_0: PRELIMINARY SUPPORT: Component 'V-Series Avalon-MM DMA for PCI Express'
Info: top.pcie_256_hip_avmm_0: The application clock frequency (pld_clk) is 125 Mhz
Info: top.pcie_256_hip_avmm_0: Hard Reset Controller enabled
Warning: top.pcie_256_hip_avmm_0: BAR1 is disabled as BAR0 is set to 64-bit prefetchable memory
Warning: top.pcie_256_hip_avmm_0: BAR3 is disabled as BAR2 is set to 64-bit prefetchable memory
Info: top.pcie_256_hip_avmm_0: Family: Arria V
Info: top.pcie_256_hip_avmm_0: 5 reconfiguration interfaces are required for connection to the external reconfiguration controller and the reconfig driver
Info: top.pcie_256_hip_avmm_0:  BAR 2 size mask is 13
Info: top.pcie_256_hip_avmm_0: Credit allocation in the 16 KBytes receive buffer:
Info: top.pcie_256_hip_avmm_0: Posted    : header=16  data=16
Info: top.pcie_256_hip_avmm_0: Non posted: header=16  data=0
Info: top.pcie_256_hip_avmm_0: Completion: header=195 data=781
Warning: top.pcie_256_hip_avmm_0.dma_rd_master/pcie_256_hip_avmm_0.wr_dts_slave: pcie_256_hip_avmm_0.wr_dts_slave does not have byteenables. Writes from narrow master pcie_256_hip_avmm_0.dma_rd_master may result in data corruption.
Warning: top.pcie_256_hip_avmm_0.dma_rd_master/pcie_256_hip_avmm_0.rd_dts_slave: pcie_256_hip_avmm_0.rd_dts_slave does not have byteenables. Writes from narrow master pcie_256_hip_avmm_0.dma_rd_master may result in data corruption.
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.Cra must be connected to an Avalon-MM master
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.MSI_Interface must be exported, or connected to a matching conduit.
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.MSIX_Interface must be exported, or connected to a matching conduit.
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.reconfig_clk_locked must be exported, or connected to a matching conduit.
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.hip_pipe must be exported, or connected to a matching conduit.
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.config_tl must be exported, or connected to a matching conduit.
Info: ip-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: ip-generate --project-directory=/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit --output-directory=/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis --file-set=QUARTUS_SYNTH --report-file=html:/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/top.html --report-file=sopcinfo:/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/top.sopcinfo --report-file=cmp:/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/top.cmp --report-file=qip:/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/top.qip --report-file=svd:/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/top.svd --report-file=regmap:/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/top.regmap --report-file=xml:/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/top.xml --report-file=debuginfo:/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/top.debuginfo --system-info=DEVICE_FAMILY="Arria V" --system-info=DEVICE=5AGXFB3H4F35C5 --system-info=DEVICE_SPEEDGRADE=5_H4 --component-file=/data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/top.qsys --language=VERILOG
Progress: Loading av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/top.qsys
Progress: Reading input file
Progress: Adding pcie_reconfig_driver_0 [altera_pcie_reconfig_driver 14.0]
Progress: Parameterizing module pcie_reconfig_driver_0
Progress: Adding alt_xcvr_reconfig_0 [alt_xcvr_reconfig 14.0]
Progress: Parameterizing module alt_xcvr_reconfig_0
Progress: Adding clk_0 [clock_source 14.0]
Progress: Parameterizing module clk_0
Progress: Adding pcie_256_hip_avmm_0 [altera_pcie_256_hip_avmm 14.0]
Progress: Parameterizing module pcie_256_hip_avmm_0
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 14.0]
Progress: Parameterizing module onchip_memory2_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: top.top: There are recommended upgrades for: pcie_256_hip_avmm_0
Info: top.alt_xcvr_reconfig_0: reconfig_from_xcvr port width is 5*46 bits
Info: top.alt_xcvr_reconfig_0: reconfig_to_xcvr port width is 5*70 bits
Warning: top.pcie_256_hip_avmm_0: PRELIMINARY SUPPORT: Component 'V-Series Avalon-MM DMA for PCI Express'
Info: top.pcie_256_hip_avmm_0: The application clock frequency (pld_clk) is 125 Mhz
Info: top.pcie_256_hip_avmm_0: Hard Reset Controller enabled
Warning: top.pcie_256_hip_avmm_0: BAR1 is disabled as BAR0 is set to 64-bit prefetchable memory
Warning: top.pcie_256_hip_avmm_0: BAR3 is disabled as BAR2 is set to 64-bit prefetchable memory
Info: top.pcie_256_hip_avmm_0: Family: Arria V
Info: top.pcie_256_hip_avmm_0: 5 reconfiguration interfaces are required for connection to the external reconfiguration controller and the reconfig driver
Info: top.pcie_256_hip_avmm_0:  BAR 2 size mask is 13
Info: top.pcie_256_hip_avmm_0: Credit allocation in the 16 KBytes receive buffer:
Info: top.pcie_256_hip_avmm_0: Posted    : header=16  data=16
Info: top.pcie_256_hip_avmm_0: Non posted: header=16  data=0
Info: top.pcie_256_hip_avmm_0: Completion: header=195 data=781
Warning: top.pcie_256_hip_avmm_0.dma_rd_master/pcie_256_hip_avmm_0.wr_dts_slave: pcie_256_hip_avmm_0.wr_dts_slave does not have byteenables. Writes from narrow master pcie_256_hip_avmm_0.dma_rd_master may result in data corruption.
Warning: top.pcie_256_hip_avmm_0.dma_rd_master/pcie_256_hip_avmm_0.rd_dts_slave: pcie_256_hip_avmm_0.rd_dts_slave does not have byteenables. Writes from narrow master pcie_256_hip_avmm_0.dma_rd_master may result in data corruption.
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.Cra must be connected to an Avalon-MM master
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.MSI_Interface must be exported, or connected to a matching conduit.
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.MSIX_Interface must be exported, or connected to a matching conduit.
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.reconfig_clk_locked must be exported, or connected to a matching conduit.
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.hip_pipe must be exported, or connected to a matching conduit.
Warning: top.pcie_256_hip_avmm_0: pcie_256_hip_avmm_0.config_tl must be exported, or connected to a matching conduit.
Info: top: Generating top "top" for QUARTUS_SYNTH
Info: Interconnect is inserted between master pcie_256_hip_avmm_0.dma_wr_master and slave onchip_memory2_0.s2 because the master has address signal 64 bit wide, but the slave is 9 bit wide.
Info: Interconnect is inserted between master pcie_256_hip_avmm_0.dma_wr_master and slave onchip_memory2_0.s2 because the master has read signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master pcie_256_hip_avmm_0.dma_wr_master and slave onchip_memory2_0.s2 because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master pcie_256_hip_avmm_0.dma_wr_master and slave onchip_memory2_0.s2 because the master has burstcount signal 6 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master pcie_256_hip_avmm_0.dma_wr_master and slave onchip_memory2_0.s2 because the master has readdatavalid signal 1 bit wide, but the slave is 0 bit wide.
Info: pcie_reconfig_driver_0: "top" instantiated altera_pcie_reconfig_driver "pcie_reconfig_driver_0"
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_h.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_h.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cal_seq.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_cal_seq.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_cif.sv SYSTEM_VERILOG PATH .//alt_xreconf_cif.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_uif.sv SYSTEM_VERILOG PATH .//alt_xreconf_uif.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_basic_acq.sv SYSTEM_VERILOG PATH .//alt_xreconf_basic_acq.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_analog.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_analog_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_analog_datactrl_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_datactrl_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_analog_rmw_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_rmw_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_analog_ctrlsm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_ctrlsm.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_offset_cancellation.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_offset_cancellation_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_eyemon.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_eyemon/alt_xcvr_reconfig_eyemon.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_dfe.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dfe/alt_xcvr_reconfig_dfe.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_adce.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_adce/alt_xcvr_reconfig_adce.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_dcd.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_dcd_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_dcd_cal_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_cal_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_dcd_control_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_control_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/alt_xcvr_reconfig_mif.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_mif_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_ctrl.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_mif_avmm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_avmm.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/alt_xcvr_reconfig_pll.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_pll_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll_ctrl.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_soc.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_soc/alt_xcvr_reconfig_soc.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_ram.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_soc/alt_xcvr_reconfig_cpu_ram.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_ram.hex OTHER PATH ../alt_xcvr_reconfig_soc/software/alt_xcvr_reconfig_av/mem_init/alt_xcvr_reconfig_cpu_ram.hex
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_direct.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_direct/alt_xcvr_reconfig_direct.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_arbiter_acq.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_arbiter_acq.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_xcvr_reconfig_basic.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xrbasic_l2p_addr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_addr.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xrbasic_l2p_ch.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_ch.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xrbasic_l2p_rom.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_rom.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xrbasic_lif_csr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif_csr.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xrbasic_lif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xcvr_reconfig_basic.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig.sdc OTHER PATH .//av_xcvr_reconfig.sdc
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_m2s.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_m2s.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./sv_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_basic.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu.v VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/alt_xcvr_reconfig_cpu.v
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif OTHER PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif OTHER PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu.v VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu.v
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench.v VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench.v
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0.v VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0.v
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_irq_mapper.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_irq_mapper.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_reset_controller.v VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_reset_controller.v
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_reset_synchronizer.v VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_reset_synchronizer.v
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_reset_controller.sdc OTHER PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_reset_controller.sdc
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_merlin_master_translator.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_master_translator.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_merlin_slave_translator.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_slave_translator.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_merlin_master_agent.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_master_agent.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_merlin_slave_agent.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_slave_agent.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_merlin_burst_uncompressor.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_burst_uncompressor.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_avalon_sc_fifo.v VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_avalon_sc_fifo.v
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux_001.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_merlin_arbitrator.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/altera_merlin_arbitrator.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux_001.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux_001.sv SYSTEM_VERILOG PATH ../../../../../../../../../build/arc/temp/217363223/alt6287_3781857270985611724.dir/0002_alt_xcvr_reconfig_0_gen/QUARTUS_SYNTH/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux_001.sv
Info: alt_xcvr_reconfig_0: "top" instantiated alt_xcvr_reconfig "alt_xcvr_reconfig_0"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_reconfig_h.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./sv_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_xcvr.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./sv_reconfig_bundle_to_ip.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_ip.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./sv_reconfig_bundle_merger.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_merger.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./alt_reset_ctrl_lego.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_reset_ctrl_lego.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./alt_reset_ctrl_tgx_cdrauto.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_reset_ctrl_tgx_cdrauto.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./alt_xcvr_csr_common_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_common_h.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./alt_xcvr_csr_common.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_common.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./alt_xcvr_csr_pcs8g_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_pcs8g_h.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./alt_xcvr_csr_pcs8g.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_pcs8g.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./alt_xcvr_mgmt2dec.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_mgmt2dec.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_xcvr_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_avmm_csr.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_tx_pma_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_tx_pma_ch.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_tx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_tx_pma.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_rx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_rx_pma.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pma.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_pcs_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pcs_ch.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_pcs.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pcs.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_avmm.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_xcvr_native.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_native.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_xcvr_plls.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_plls.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_xcvr_data_adapter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_data_adapter.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_hssi_8g_rx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_8g_rx_pcs_rbc.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_hssi_8g_tx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_8g_tx_pcs_rbc.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_hssi_common_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_common_pcs_pma_interface_rbc.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_hssi_common_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_common_pld_pcs_interface_rbc.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_hssi_pipe_gen1_2_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_pipe_gen1_2_rbc.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_hssi_rx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_rx_pcs_pma_interface_rbc.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_hssi_rx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_rx_pld_pcs_interface_rbc.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_hssi_tx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_tx_pcs_pma_interface_rbc.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_hssi_tx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_tx_pld_pcs_interface_rbc.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_xcvr_pipe_native.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_pipe_native.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_xcvr_emsip_adapter.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_emsip_adapter.sv
Info: pcie_256_hip_avmm_0: add_fileset_file ./av_xcvr_pipe_native_hip.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_pipe_native_hip.sv
Info: pcie_256_hip_avmm_0: "top" instantiated altera_pcie_256_hip_avmm "pcie_256_hip_avmm_0"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_xcvr_functions.sv
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_resync.sv
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/alt_xcvr_csr_selector.sv
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_wait_generate.v
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/av_xcvr_h.sv
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/av_reconfig_bundle_to_basic.sv
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/av_reconfig_bundle_to_xcvr.sv
Warning: Overwriting different file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/plain_files.txt
Info: onchip_memory2_0: Starting RTL generation for module 'top_onchip_memory2_0'
Info: onchip_memory2_0:   Generation command is [exec /tools_archive/acds/14.0/200/linux64/quartus/linux64/perl/bin/perl -I /tools_archive/acds/14.0/200/linux64/quartus/linux64/perl/lib -I /tools_archive/acds/14.0/200/linux64/quartus/sopc_builder/bin/europa -I /tools_archive/acds/14.0/200/linux64/quartus/sopc_builder/bin/perl_lib -I /tools_archive/acds/14.0/200/linux64/quartus/sopc_builder/bin -I /tools_archive/acds/14.0/200/linux64/quartus/../ip/altera/sopc_builder_ip/common -I /tools_archive/acds/14.0/200/linux64/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /tools_archive/acds/14.0/200/linux64/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=top_onchip_memory2_0 --dir=/build/arc/temp/217363223/alt6287_3781857270985611724.dir/0004_onchip_memory2_0_gen/ --quartus_dir=/tools_archive/acds/14.0/200/linux64/quartus --verilog --config=/build/arc/temp/217363223/alt6287_3781857270985611724.dir/0004_onchip_memory2_0_gen//top_onchip_memory2_0_component_configuration.pl  --do_build_sim=0  ]
Info: onchip_memory2_0: Done RTL generation for module 'top_onchip_memory2_0'
Info: onchip_memory2_0: "top" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"
Info: mm_interconnect_1: "top" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: mm_interconnect_2: "top" instantiated altera_mm_interconnect "mm_interconnect_2"
Info: mm_interconnect_3: "top" instantiated altera_mm_interconnect "mm_interconnect_3"
Info: rst_controller: "top" instantiated altera_reset_controller "rst_controller"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_controller.v
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_synchronizer.v
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_reset_controller.sdc
Info: pcie_256_hip_avmm_0_Rxm_BAR2_translator: "mm_interconnect_1" instantiated altera_merlin_master_translator "pcie_256_hip_avmm_0_Rxm_BAR2_translator"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_translator.sv
Info: onchip_memory2_0_s1_translator: "mm_interconnect_1" instantiated altera_merlin_slave_translator "onchip_memory2_0_s1_translator"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_translator.sv
Info: pcie_256_hip_avmm_0_Rxm_BAR2_agent: "mm_interconnect_1" instantiated altera_merlin_master_agent "pcie_256_hip_avmm_0_Rxm_BAR2_agent"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_master_agent.sv
Info: onchip_memory2_0_s1_agent: "mm_interconnect_1" instantiated altera_merlin_slave_agent "onchip_memory2_0_s1_agent"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_slave_agent.sv
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: onchip_memory2_0_s1_agent_rsp_fifo: "mm_interconnect_1" instantiated altera_avalon_sc_fifo "onchip_memory2_0_s1_agent_rsp_fifo"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_avalon_sc_fifo.v
Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_1" instantiated altera_merlin_router "router_001"
Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002"
Info: router_003: "mm_interconnect_1" instantiated altera_merlin_router "router_003"
Info: onchip_memory2_0_s1_burst_adapter: "mm_interconnect_1" instantiated altera_merlin_burst_adapter "onchip_memory2_0_s1_burst_adapter"
Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_demux_001: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv
Info: cmd_mux_001: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_001"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_demux_001: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_001"
Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux_001: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux_001"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv
Info: pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter: "mm_interconnect_1" instantiated altera_merlin_width_adapter "pcie_256_hip_avmm_0_Rxm_BAR2_to_onchip_memory2_0_s1_cmd_width_adapter"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: router: "mm_interconnect_2" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_2" instantiated altera_merlin_router "router_001"
Info: cmd_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "cmd_mux"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv
Info: router: "mm_interconnect_3" instantiated altera_merlin_router "router"
Info: router_002: "mm_interconnect_3" instantiated altera_merlin_router "router_002"
Info: cmd_demux: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file /data/kichan/Builds/14.0/b200/av_x4_g2_ast128_5AGXFB3H4F35C5_g2_x4_avmm_dma_stkit/pcie_lib/synthesis/submodules/altera_merlin_arbitrator.sv
Info: top: Done "top" with 39 modules, 178 files
Info: ip-generate succeeded.
Info: Finished: Create HDL design files for synthesis
