Info (10281): Verilog HDL Declaration information at top_mm_interconnect_3_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_3_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_3_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_3_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(265): object "BYTE_TO_WORD_SHIFT" differs only in case from object "byte_to_word_shift" in the same scope
Info (10281): Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object "addr_incr" differs only in case from object "ADDR_INCR" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_2_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_2_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_2_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_2_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_1_router_003.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_1_router_003.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_1_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_1_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_1_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_1_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_1_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at top_mm_interconnect_1_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at altpcie_dynamic_control.sv(78): object "DTS_IDLE" differs only in case from object "dts_idle" in the same scope
Warning (10720): Verilog HDL or VHDL warning at pcie_lib/synthesis/submodules/sv_reconfig_bundle_to_xcvr.sv(26): MESSAGE_ON or MESSAGE_OFF directive cannot process the non-HDL message ID 13024.
Warning (10720): Verilog HDL or VHDL warning at pcie_lib/synthesis/submodules/sv_reconfig_bundle_to_xcvr.sv(26): MESSAGE_ON or MESSAGE_OFF directive cannot process the non-HDL message ID 21074.
Warning (10720): Verilog HDL or VHDL warning at pcie_lib/synthesis/submodules/av_reconfig_bundle_to_xcvr.sv(26): MESSAGE_ON or MESSAGE_OFF directive cannot process the non-HDL message ID 13024.
Warning (10720): Verilog HDL or VHDL warning at pcie_lib/synthesis/submodules/av_reconfig_bundle_to_xcvr.sv(26): MESSAGE_ON or MESSAGE_OFF directive cannot process the non-HDL message ID 21074.
Info (10281): Verilog HDL Declaration information at alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at altpcie_reconfig_driver.sv(298): object "ADCE_TRIG_DONE" differs only in case from object "adce_trig_done" in the same scope
Warning (13024): Output pins are stuck at VCC or GND
