Design Assistant report for top
Tue Aug  5 17:48:42 2014
Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Full Version


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; Table of Contents ;
---------------------
  1. Legal Notice
  2. Design Assistant Summary
  3. Parallel Compilation
  4. Design Assistant Settings
  5. Medium Violations
  6. Information only Violations
  7. Design Assistant Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+-------------------------------------------------------------------------+
; Design Assistant Summary                                                ;
+-----------------------------------+-------------------------------------+
; Design Assistant Status           ; Analyzed - Tue Aug  5 17:48:42 2014 ;
; Revision Name                     ; top                                 ;
; Top-level Entity Name             ; top_hw                              ;
; Family                            ; Arria V                             ;
; Total Critical Violations         ; 0                                   ;
; Total High Violations             ; 0                                   ;
; Total Medium Violations           ; 1                                   ;
; - Rule R105                       ; 1                                   ;
; Total Information only Violations ; 322                                 ;
; - Rule T101                       ; 272                                 ;
; - Rule T102                       ; 50                                  ;
+-----------------------------------+-------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 24          ;
; Maximum allowed            ; 12          ;
;                            ;             ;
; Average used               ; 2.57        ;
; Maximum used               ; 12          ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-12        ;  14.3%      ;
;     Processors 13-24       ;   0.0%      ;
+----------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----------------------------+
; Option                                                                                                                                                                                                                                                                                                                                                                                                                      ; Setting      ; To                         ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----------------------------+
; Design Assistant mode                                                                                                                                                                                                                                                                                                                                                                                                       ; Post-Fitting ;                            ;
; Threshold value for clock net not mapped to clock spines rule                                                                                                                                                                                                                                                                                                                                                               ; 25           ;                            ;
; Minimum number of clock port feed by gated clocks                                                                                                                                                                                                                                                                                                                                                                           ; 30           ;                            ;
; Minimum number of node fan-out                                                                                                                                                                                                                                                                                                                                                                                              ; 30           ;                            ;
; Maximum number of nodes to report                                                                                                                                                                                                                                                                                                                                                                                           ; 50           ;                            ;
; Rule C101: Gated clock should be implemented according to the Altera standard scheme                                                                                                                                                                                                                                                                                                                                        ; On           ;                            ;
; Rule C102: Logic cell should not be used to generate an inverted clock signal                                                                                                                                                                                                                                                                                                                                               ; On           ;                            ;
; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power                                                                                                                                                                                                                                                                                                                 ; On           ;                            ;
; Rule C104: Clock signal source should drive only clock input ports                                                                                                                                                                                                                                                                                                                                                          ; On           ;                            ;
; Rule C105: Clock signal should be a global signal (You set a Design Assistant configuration rule to check for clocks with a certain number of fanouts. You specified a reporting threshold of <number> fanouts. The following clocks all contain more than <number> fanouts. You can either adjust the reporting threshold in the Design Assistant Settings page, or change the following clock signals to global signals.) ; On           ;                            ;
; Rule C106: Clock signal source should not drive registers triggered by different clock edges                                                                                                                                                                                                                                                                                                                                ; On           ;                            ;
; Rule R101: Combinational logic used as a reset signal should be synchronized                                                                                                                                                                                                                                                                                                                                                ; On           ;                            ;
; Rule R102: External reset signals should be synchronized using two cascaded registers                                                                                                                                                                                                                                                                                                                                       ; On           ;                            ;
; Rule R103: External reset signal should be correctly synchronized                                                                                                                                                                                                                                                                                                                                                           ; On           ;                            ;
; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized                                                                                                                                                                                                                                                                                         ; On           ;                            ;
; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized                                                                                                                                                                                                                                                                                                   ; On           ;                            ;
; Rule T101: Nodes with more than the specified number of fan-outs                                                                                                                                                                                                                                                                                                                                                            ; On           ;                            ;
; Rule T102: Top nodes with the highest number of fan-outs                                                                                                                                                                                                                                                                                                                                                                    ; On           ;                            ;
; Rule A101: Design should not contain combinational loops                                                                                                                                                                                                                                                                                                                                                                    ; On           ;                            ;
; Rule A102: Register output should not drive its own control signal directly or through combinational logic                                                                                                                                                                                                                                                                                                                  ; On           ;                            ;
; Rule A103: Design should not contain delay chains                                                                                                                                                                                                                                                                                                                                                                           ; On           ;                            ;
; Rule A104: Design should not contain ripple clock structures                                                                                                                                                                                                                                                                                                                                                                ; On           ;                            ;
; Rule A105: Pulses should not be implemented asynchronously                                                                                                                                                                                                                                                                                                                                                                  ; On           ;                            ;
; Rule A106: Multiple pulses should not be generated in design                                                                                                                                                                                                                                                                                                                                                                ; On           ;                            ;
; Rule A107: Design should not contain SR latches                                                                                                                                                                                                                                                                                                                                                                             ; On           ;                            ;
; Rule A108: Design should not contain latches                                                                                                                                                                                                                                                                                                                                                                                ; On           ;                            ;
; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source                                                                                                                                                                                                                                                                                                                    ; On           ;                            ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                                                                                                                                                                                                                                                                       ; On           ;                            ;
; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source                                                                                                                                                                                                                                                                                                                     ; On           ;                            ;
; Rule S104: Clock port and any other port of a register should not be driven by the same signal source                                                                                                                                                                                                                                                                                                                       ; On           ;                            ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains                                                                                                                                                                                                                                                                                                                               ; On           ;                            ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain                                                                                                                                                                                                                                                        ; On           ;                            ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                                                                                                                                                                     ; On           ;                            ;
; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains                                                                                                                                                                                                                                                                                                               ; Off          ;                            ;
; Rule M102: No reset signal defined to initialize the state machine                                                                                                                                                                                                                                                                                                                                                          ; Off          ;                            ;
; Rule M103: State machine should not contain an unreachable state                                                                                                                                                                                                                                                                                                                                                            ; Off          ;                            ;
; Rule M104: State machine should not contain a deadlock state                                                                                                                                                                                                                                                                                                                                                                ; Off          ;                            ;
; Rule M105: State machine should not contain a dead transition                                                                                                                                                                                                                                                                                                                                                               ; Off          ;                            ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                                                                                                                                                                     ; Off          ; resync_chains[0].sync_r[1] ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                                                                                                                                                                     ; Off          ; resync_chains[0].sync_r[0] ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Medium Violations                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Rule name                                                                                                                                                                                                                                                                                  ; Name                                                                                                                                                                                                                           ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized                                                                                                                                                                  ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|state.DPRIO_WRITE                 ;
;  Reset signal destination node(s) from clock "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd180_det|alt_edge_det_ff1" ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd180_det|ff2 ;
;  Reset signal destination node(s) from clock "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd90_det|alt_edge_det_ff1"  ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd90_det|ff2  ;
;  Reset signal destination node(s) from clock "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd0_det|alt_edge_det_ff1"   ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd0_det|ff2   ;
;  Reset signal destination node(s) from clock "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd270_det|alt_edge_det_ff1" ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd270_det|ff2 ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Information only Violations                                                                                                                                                                                                                                                                                                                                                                                        ;
+------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Rule name                                                        ; Name                                                                                                                                                                                                                                                                                                                                  ; Fan-Out ;
+------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Rule T101: Nodes with more than the specified number of fan-outs ; reconfig_xcvr_clk~inputCLKENA0                                                                                                                                                                                                                                                                                                        ; 739     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_resync:inst_reconfig_reset_sync|resync_chains[0].sync_r[1]                                                                                                                                                                                                                     ; 178     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|basic_address[1]~1                                                                                                                                                                                                                                                                      ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|ifsel_notdone_resync                                                                                                                                                                                                                                                                    ; 330     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|basic_reconfig_waitrequest~2                                                                                                                                        ; 54      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|basic_reconfig_waitrequest~1                                                                                                                                        ; 54      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|basic_reconfig_waitrequest~0                                                                                                                                        ; 54      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_dcd:dcd.sc_dcd|alt_xcvr_reconfig_dcd_av:inst_alt_xcvr_reconfig_dcd_av|alt_xcvr_reconfig_dcd_cal_av:inst_alt_xcvr_reconfig_dcd_cal|state_done.STATE_DONE2                                                                                                              ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_dcd:dcd.sc_dcd|alt_xcvr_reconfig_dcd_av:inst_alt_xcvr_reconfig_dcd_av|alt_xcvr_reconfig_dcd_cal_av:inst_alt_xcvr_reconfig_dcd_cal|alt_xcvr_reconfig_dcd_control_av:inst_alt_xcvr_reconfig_dcd_control|ctrl_addr~0                                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|coreclkout~CLKENA0                                                                                                                                                                   ; 13804   ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcierd_hip_rs:rs_hip|app_rstn~CLKENA0                                                                                                                                                                                                                                       ; 11733   ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcierd_hip_rs:rs_hip|app_rstn                                                                                                                                                                                                                                               ; 305     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcierd_hip_rs:rs_hip|npor_sync_pld_clk                                                                                                                                                                                                                                      ; 47      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; any_rstn_rr                                                                                                                                                                                                                                                                                                                           ; 46      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND                                                                                                                                                                                                                                                                                                                                  ; 497     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|fifo_transmit~0                                                                                                                                                                                            ; 133     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|tlp_val                                                                                                                                                                                                  ; 114     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|tlp_file_num[7]~0                                                                                                                                                                                        ; 113     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|data_fifo_rdreq                                                                                                                                                                                          ; 120     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|hdr_address[52]~0                                                                                                                                                                                        ; 82      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|tx_side_fifo_rdreq                                                                                                                                                                                                                         ; 168     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[0][4]~0                                                                                                                                                                                                 ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[0]~1                                                                                                                                                                                                  ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_txs:txs_slave|txs_wait_cnt~DUPLICATE                                                                                                                                                                                         ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_3:mm_interconnect_3|top_mm_interconnect_3_cmd_mux:cmd_mux|WideOr1                                                                                                                                                                                                                                         ; 51      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|dcm_state[1]                                                                                                                                                                                                   ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[127]~1                                                                                                                                                                    ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ep_last_data[8]                                                                                                                                                                                                ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|RxFifoRdReq_o~1                                                                                                                                                                                               ; 121     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|avmm_burst_cntr[5]~0                                                                                                                                                                                      ; 105     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[0][104]~0                                                                                                                                                              ; 149     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[0]~2                                                                                                                                                                 ; 150     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|RxFifoRdReq_o~3                                                                                                                                                                                           ; 168     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[1][11]~1                                                                                                                                                               ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[1]~4                                                                                                                                                                 ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[2][7]~2                                                                                                                                                                ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[2]~5                                                                                                                                                                 ; 133     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[3][6]~3                                                                                                                                                                ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[3]~6                                                                                                                                                                 ; 133     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[4][8]~4                                                                                                                                                                ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[4]~8                                                                                                                                                                 ; 133     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[5][102]~5                                                                                                                                                              ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[5]~9                                                                                                                                                                 ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[6][66]~6                                                                                                                                                               ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[6]~10                                                                                                                                                                ; 133     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[7][56]~7                                                                                                                                                               ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[7]~12                                                                                                                                                                ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[8][73]~8                                                                                                                                                               ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[8]~14                                                                                                                                                                ; 133     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[9]~15                                                                                                                                                                ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|rd_dma_state[3]                                                                                                                                                                                           ; 152     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|rd_dma_state[6]                                                                                                                                                                                           ; 53      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|rd_pop_desc_state                                                                                                                                                                                         ; 198     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|rstn_rr                                                                                                                                                                                                    ; 118     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|altpcie_tl_cfg_pipe:g_tl_cfg_sync.altpcie_tl_cfg_pipe_inst|o_tl_cfg_ctl[18]~0                                                                                                        ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|altpcie_rs_serdes:g_soft_reset.altpcie_rs_serdes|srst_r                                                                                                                              ; 41      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|altpcie_rs_serdes:g_soft_reset.altpcie_rs_serdes|any_rstn_rr                                                                                                                         ; 59      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|altpcie_rs_serdes:g_soft_reset.altpcie_rs_serdes|arst_r[2]                                                                                                                           ; 175     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|dma_tx_state[5]                                                                                                                                                                                                 ; 122     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altera_reset_controller:rst_controller_001|r_sync_rst                                                                                                                                                                                                                                                                         ; 807     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_burst_adapter:pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|load_next_out_cmd                  ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_width_adapter:pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter|always10~0                                                                                                                                                        ; 162     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|avmmwr_cmd_fifo_rdreq~1                                                                                                                                                                                   ; 60      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|NON_PIPELINED_INPUTS.load_next_cmd              ; 148     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|top_mm_interconnect_1_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|grant[1]~1                                                                                                                                                                                                         ; 155     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:rxm_cmd_fifo|fifo_count[0]                                                                                                                                                                   ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|latch_header_reg                                                                                                                                                                                          ; 60      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[0][73]                                                                                                                                                                 ; 68      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[0][72]                                                                                                                                                                 ; 64      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[0][74]                                                                                                                                                                 ; 65      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[0][75]                                                                                                                                                                 ; 65      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|tag_fifo_rdreq                                                                                                                                                                                            ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_burst_adapter:pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|load_next_out_cmd                  ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_burst_adapter:pcie_256_hip_avmm_0_wr_dts_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|NON_PIPELINED_INPUTS.load_next_cmd ; 106     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|cur_src_addr_reg[2]~0                                                                                                                                                                                     ; 93      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_reg[0][145]~0                                                                                                                                                            ; 106     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_wrreq[0]~0                                                                                                                                                               ; 107     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|dt_low_dest_addr_wen                                                                                                                                                                                           ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|reg_read_data_reg[24]~4                                                                                                                                                                                         ; 70      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|addr_bit2_reg                                                                                                                                                                                                 ; 66      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_burst_adapter:pcie_256_hip_avmm_0_rd_dts_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|NON_PIPELINED_INPUTS.load_next_cmd ; 108     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|Selector32~0                                                                                                                                                                                                  ; 50      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|dt_low_dest_addr_wen                                                                                                                                                                                            ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|dma_tx_state[4]                                                                                                                                                                                                 ; 122     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|Selector31~0                                                                                                                                                                                                  ; 31      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|table_id_size_wen                                                                                                                                                                                              ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|Decoder0~1                                                                                                                                                                                                     ; 50      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|Selector34~0                                                                                                                                                                                                  ; 46      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|Selector35~0                                                                                                                                                                                                  ; 46      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|Selector36~0                                                                                                                                                                                                  ; 40      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|Selector33~0                                                                                                                                                                                                  ; 54      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|table_id_size_wen                                                                                                                                                                                               ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_reg[1][128]~1                                                                                                                                                            ; 105     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_wrreq[1]~2                                                                                                                                                               ; 106     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_reg[2][135]~2                                                                                                                                                            ; 105     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_wrreq[2]~3                                                                                                                                                               ; 106     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_reg[3][78]~3                                                                                                                                                             ; 105     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_wrreq[3]~4                                                                                                                                                               ; 106     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_reg[4][147]~4                                                                                                                                                            ; 105     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_wrreq[4]~5                                                                                                                                                               ; 106     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo|fifo_wrreq[5]~6                                                                                                                                                               ; 105     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:avmmwr_data_fifo|scfifo_1f91:auto_generated|a_dpfifo_8l91:dpfifo|valid_wreq                                                                                                                        ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|avmmwr_data_reg[3]~1                                                                                                                                                                                      ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|cpl_addr_bit2_reg                                                                                                                                                                                         ; 130     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|current_dt_address_reg[9]~1                                                                                                                                                                                    ; 59      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|current_dt_address_reg[9]~0                                                                                                                                                                                    ; 59      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|dt_low_src_addr_wen                                                                                                                                                                                            ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|current_dt_address_reg[50]~1                                                                                                                                                                                    ; 59      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|current_dt_address_reg[50]~0                                                                                                                                                                                    ; 59      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|dt_low_src_addr_wen                                                                                                                                                                                             ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|avmmwr_data_reg[3]~0                                                                                                                                                                                      ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|avmmwr_data_reg[3]~2                                                                                                                                                                                      ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|always131~1                                                                                                                                                                                               ; 100     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:pcie_256_hip_avmm_0_dma_rd_master_translator|uav_address[4]~1                                                                                                                                                                                         ; 185     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_width_adapter:pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter|always9~1                                                                                                                                                         ; 79      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|Equal89~2                                                                                                                                                                                                 ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|desc_fifo_rdreq                                                                                                                                                                                          ; 134     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|curr_addr[14]~1                                                                                                                                                                                          ; 59      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_reg[0][127]~0                                                                                                                                                          ; 102     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_wrreq[0]~1                                                                                                                                                             ; 103     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_width_adapter:pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_wr_dts_slave_cmd_width_adapter|always9~1                                                                                                                                                         ; 76      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_reg[1][127]~1                                                                                                                                                          ; 102     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_wrreq[1]~2                                                                                                                                                             ; 103     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_reg[2][127]~2                                                                                                                                                          ; 102     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_wrreq[2]~3                                                                                                                                                             ; 103     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_reg[3][127]~3                                                                                                                                                          ; 102     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_wrreq[3]~4                                                                                                                                                             ; 103     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_reg[4][127]~4                                                                                                                                                          ; 102     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_wrreq[4]~5                                                                                                                                                             ; 103     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|altpcie_fifo:write_desc_fifo|fifo_wrreq[5]~6                                                                                                                                                             ; 102     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|hdr_gen_sm.CONT_FILE                                                                                                                                                                                     ; 158     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|Decoder1~0                                                                                                                                                                                               ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|WideOr12                                                                                                                                                                                                 ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|curr_addr[14]~0                                                                                                                                                                                          ; 52      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|scfifo:write_data_fifo|scfifo_51f1:auto_generated|a_dpfifo_ece1:dpfifo|valid_wreq                                                                                                                        ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|file_size_reg[6]~1                                                                                                                                                                                       ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|WrDmaReadDataValid_reg                                                                                                                                                                                   ; 141     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_2:mm_interconnect_2|altera_merlin_burst_adapter:onchip_memory2_0_s2_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|load_next_out_cmd                               ; 50      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_2:mm_interconnect_2|altera_merlin_burst_adapter:onchip_memory2_0_s2_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|new_burst_reg                                   ; 56      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_2:mm_interconnect_2|altera_merlin_burst_adapter:onchip_memory2_0_s2_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|in_eop_reg                                      ; 49      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|rdmem_sm.RD_CONT                                                                                                                                                                                         ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_sm.AVST_START_STATE                                                                                                                                                                                 ; 83      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|payld_shift_n.011~0                                                                                                                                                                                      ; 41      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|payld_shift_n.100~0                                                                                                                                                                                      ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_arbiter:arbiter_inst|arb_state[4]                                                                                                                                                                                                ; 67      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_arbiter:arbiter_inst|arb_state[1]                                                                                                                                                                                                ; 66      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|load_next_out_cmd                               ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|WideOr6~0                                                                                                                                                                                                      ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_file_num[3]                                                                                                                                                                                         ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_file_num[2]                                                                                                                                                                                         ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ep_last_fifo_wrreq_array~0                                                                                                                                                                                     ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_file_num[1]                                                                                                                                                                                         ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_file_num[0]                                                                                                                                                                                         ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_file_num[5]~DUPLICATE                                                                                                                                                                               ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|msi_array[112]~1                                                                                                                                                                                               ; 40      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|WideOr5~0                                                                                                                                                                                                      ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|msi_array[48]~0                                                                                                                                                                                                ; 40      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ctrl_wen                                                                                                                                                                                                       ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|Decoder0~0                                                                                                                                                                                                     ; 50      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[0]~0                                                                                                                                                                      ; 263     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|dcm_state[1]~DUPLICATE                                                                                                                                                                                          ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[0]~0                                                                                                                                                                       ; 263     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo|fifo_count[0]~DUPLICATE                                                                                                                                                               ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ep_last_data[8]                                                                                                                                                                                                 ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|msi_array[48]~0                                                                                                                                                                                                 ; 40      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|RdDmaTxData_o[6]                                                                                                                                                                                          ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|RdDmaTxData_o[5]                                                                                                                                                                                          ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|RdDmaTxData_o[3]                                                                                                                                                                                          ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|RdDmaTxData_o[1]                                                                                                                                                                                          ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|RdDmaTxData_o[4]                                                                                                                                                                                          ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ep_last_fifo_wrreq_array~0                                                                                                                                                                                      ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|RdDmaTxData_o[2]                                                                                                                                                                                          ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|RdDmaTxData_o[0]                                                                                                                                                                                          ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|WideOr5~0                                                                                                                                                                                                       ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|WideOr6~0                                                                                                                                                                                                       ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|msi_array[112]~1                                                                                                                                                                                                ; 40      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ctrl_wen                                                                                                                                                                                                        ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo|fifo_count[7]                                                                                                                                                                         ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[127]~1                                                                                                                                                                     ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo|fifo_count[3]~DUPLICATE                                                                                                                                                               ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[31]~33                                                                                                                                                                     ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[63]~66                                                                                                                                                                     ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[95]~99                                                                                                                                                                     ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_3:mm_interconnect_3|top_mm_interconnect_3_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|grant[1]~1                                                                                                                                                                                                         ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_3:mm_interconnect_3|top_mm_interconnect_3_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|grant[0]~3                                                                                                                                                                                                         ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|altpcie_fifo:ep_last_fifo|fifo_count[3]                                                                                                                                                                        ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|altpcie_fifo:ep_last_fifo|fifo_count[2]                                                                                                                                                                        ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[31]~33                                                                                                                                                                    ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[63]~66                                                                                                                                                                    ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[95]~99                                                                                                                                                                    ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ep_last_from_dma_r[0]                                                                                                                                                                                          ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ep_last_from_dma_r[0]                                                                                                                                                                                           ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[1][2]~1                                                                                                                                                                                                 ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[1]~3                                                                                                                                                                                                  ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[2][7]~2                                                                                                                                                                                                 ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[2]~4                                                                                                                                                                                                  ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[3][3]~3                                                                                                                                                                                                 ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[3]~6                                                                                                                                                                                                  ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[4][70]~4                                                                                                                                                                                                ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[4]~7                                                                                                                                                                                                  ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[5][128]~5                                                                                                                                                                                               ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[5]~9                                                                                                                                                                                                  ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[6][2]~6                                                                                                                                                                                                 ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[6]~10                                                                                                                                                                                                 ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[7][117]~7                                                                                                                                                                                               ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[7]~11                                                                                                                                                                                                 ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[8][2]~8                                                                                                                                                                                                 ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[8]~12                                                                                                                                                                                                 ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[9][130]~9                                                                                                                                                                                               ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[9]~13                                                                                                                                                                                                 ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[10][2]~10                                                                                                                                                                                               ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[10]~14                                                                                                                                                                                                ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[11][101]~11                                                                                                                                                                                             ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[11]~15                                                                                                                                                                                                ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[12][1]~12                                                                                                                                                                                               ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[12]~16                                                                                                                                                                                                ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[13][64]~13                                                                                                                                                                                              ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[13]~17                                                                                                                                                                                                ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[14][81]~14                                                                                                                                                                                              ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[14]~18                                                                                                                                                                                                ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[15]~20                                                                                                                                                                                                ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|always5~0                                                                                                                                                                                                     ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|top_mm_interconnect_1_cmd_mux:cmd_mux|src_payload~3                                                                                                                                                                                                                                   ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|top_mm_interconnect_1_cmd_mux:cmd_mux|src_payload~4                                                                                                                                                                                                                                   ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|top_mm_interconnect_1_cmd_mux:cmd_mux|src_payload~5                                                                                                                                                                                                                                   ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|top_mm_interconnect_1:mm_interconnect_1|top_mm_interconnect_1_cmd_mux:cmd_mux|src_payload~2                                                                                                                                                                                                                                   ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|Selector613~0                                                                                                                                                                                            ; 129     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|rx_addr_reg[8]                                                                                                                                                                                                ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|data_fifo_wdata_reg[107]~1                                                                                                                                                                               ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|data_fifo_wdata_reg[107]~0                                                                                                                                                                               ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|hdr_partial_word_en[0]                                                                                                                                                                                   ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|hdr_partial_word_en[1]                                                                                                                                                                                   ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_data[106]~14                                                                                                                                                                                        ; 86      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_data[106]~12                                                                                                                                                                                        ; 83      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_data[106]~11                                                                                                                                                                                        ; 83      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_data[87]~10                                                                                                                                                                                         ; 55      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|tx_side_fifo_input[130]~2                                                                                                                                                                                                                  ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|dt_hi_src_addr_wen                                                                                                                                                                                              ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|dt_hi_src_addr_wen                                                                                                                                                                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ep_last_from_dma_r[6]                                                                                                                                                                                          ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ep_last_from_dma_r[5]                                                                                                                                                                                          ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ep_last_from_dma_r[4]                                                                                                                                                                                          ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ep_last_from_dma_r[3]                                                                                                                                                                                          ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ep_last_from_dma_r[2]                                                                                                                                                                                          ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ep_last_from_dma_r[1]                                                                                                                                                                                          ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ep_last_from_dma_r[6]                                                                                                                                                                                           ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ep_last_from_dma_r[5]                                                                                                                                                                                           ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ep_last_from_dma_r[4]                                                                                                                                                                                           ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ep_last_from_dma_r[3]                                                                                                                                                                                           ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ep_last_from_dma_r[2]                                                                                                                                                                                           ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ep_last_from_dma_r[1]                                                                                                                                                                                           ; 128     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|tx_side_fifo_input_r[99]~20                                                                                                                                                                                                                ; 41      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|reg_read_data_reg[24]~2                                                                                                                                                                                         ; 65      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|dt_hi_dest_addr_wen                                                                                                                                                                                            ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|dt_hi_dest_addr_wen                                                                                                                                                                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|Decoder1~1                                                                                                                                                                                                    ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_data[106]~19                                                                                                                                                                                        ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|avst_data[96]~18                                                                                                                                                                                         ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_arbiter_acq:mutex_inst|mutex_grant~0                                                                                                                         ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|state.TEST_INPUT                                                                                                                         ; 54      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|alt_xcvr_arbiter:pif[0].pif_arb|grant[0]                                                                                                                                                                                        ; 31      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|pif_ena[0]                                                                                                                                                                                     ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|pif_ena[1]                                                                                                                                                                                     ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|alt_xcvr_arbiter:pif[1].pif_arb|grant[0]                                                                                                                                                                                        ; 31      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reg_rwdata[31]~1                                                                                                                                                    ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|basic_address[0]~0                                                                                                                                                                                                                                                                      ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reco_addr[11]                                                                                                                                                       ; 70      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|always2~2                                                                                                                                                           ; 56      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|upper_16_sel                                                                                                                                                                                   ; 64      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|sel_enabled_and_granted[1]~2                                                                                                                                                                   ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|sel_enabled_and_granted[0]~1                                                                                                                                                                   ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|always2~3                                                                                                                                                           ; 38      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|coreclkout~CLKENA0                                                                                                                                                                   ; 13804   ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcierd_hip_rs:rs_hip|app_rstn~CLKENA0                                                                                                                                                                                                                                       ; 11733   ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altera_reset_controller:rst_controller_001|r_sync_rst                                                                                                                                                                                                                                                                         ; 807     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; reconfig_xcvr_clk~inputCLKENA0                                                                                                                                                                                                                                                                                                        ; 739     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; ~GND                                                                                                                                                                                                                                                                                                                                  ; 497     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|ifsel_notdone_resync                                                                                                                                                                                                                                                                    ; 330     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcierd_hip_rs:rs_hip|app_rstn                                                                                                                                                                                                                                               ; 305     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[0]~0                                                                                                                                                                      ; 263     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[0]~0                                                                                                                                                                       ; 263     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|rd_pop_desc_state                                                                                                                                                                                         ; 198     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:pcie_256_hip_avmm_0_dma_rd_master_translator|uav_address[4]~1                                                                                                                                                                                         ; 185     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_resync:inst_reconfig_reset_sync|resync_chains[0].sync_r[1]                                                                                                                                                                                                                     ; 178     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|altpcie_rs_serdes:g_soft_reset.altpcie_rs_serdes|arst_r[2]                                                                                                                           ; 175     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|tx_side_fifo_rdreq                                                                                                                                                                                                                         ; 168     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|RxFifoRdReq_o~3                                                                                                                                                                                           ; 168     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_width_adapter:pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter|always10~0                                                                                                                                                        ; 162     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|hdr_gen_sm.CONT_FILE                                                                                                                                                                                     ; 158     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|top_mm_interconnect_1:mm_interconnect_1|top_mm_interconnect_1_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|grant[1]~1                                                                                                                                                                                                         ; 155     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|rd_dma_state[3]                                                                                                                                                                                           ; 152     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[0]~2                                                                                                                                                                 ; 150     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[0][104]~0                                                                                                                                                              ; 149     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|NON_PIPELINED_INPUTS.load_next_cmd              ; 148     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|WrDmaReadDataValid_reg                                                                                                                                                                                   ; 141     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|desc_fifo_rdreq                                                                                                                                                                                          ; 134     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|fifo_transmit~0                                                                                                                                                                                            ; 133     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[8]~14                                                                                                                                                                ; 133     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[2]~5                                                                                                                                                                 ; 133     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[6]~10                                                                                                                                                                ; 133     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[4]~8                                                                                                                                                                 ; 133     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[3]~6                                                                                                                                                                 ; 133     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[2][7]~2                                                                                                                                                                ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[1]~4                                                                                                                                                                 ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[8][73]~8                                                                                                                                                               ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[1][11]~1                                                                                                                                                               ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[7]~12                                                                                                                                                                ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[9]~15                                                                                                                                                                ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[7][56]~7                                                                                                                                                               ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[6][66]~6                                                                                                                                                               ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[5]~9                                                                                                                                                                 ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[4][8]~4                                                                                                                                                                ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[3][6]~3                                                                                                                                                                ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[5][102]~5                                                                                                                                                              ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|cpl_addr_bit2_reg                                                                                                                                                                                         ; 130     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|ep_last_data[8]                                                                                                                                                                                                 ; 129     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|Selector613~0                                                                                                                                                                                            ; 129     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[14]~18                                                                                                                                                                                                ; 129     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[0]~1                                                                                                                                                                                                  ; 129     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[5]~9                                                                                                                                                                                                  ; 129     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[13]~17                                                                                                                                                                                                ; 129     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[12]~16                                                                                                                                                                                                ; 129     ;
+------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+---------------------------+
; Design Assistant Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Design Assistant
    Info: Version 14.0.0 Build 200 06/17/2014 SJ Full Version
    Info: Processing started: Tue Aug  5 17:48:23 2014
Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off top -c top
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity alt_cal_av
        Info (332166): set_disable_timing [get_cells -compatibility_mode *|alt_cal_channel[*]] -to q 
        Info (332166): set_disable_timing [get_cells -compatibility_mode *|alt_cal_busy] -to q 
    Info (332165): Entity alt_cal_edge_detect
        Info (332166): create_clock -name alt_cal_av_edge_detect_clk -period 10 [get_registers *alt_cal_av*|*pd*_det|alt_edge_det_ff?]
        Info (332166): set_clock_groups -exclusive -group [get_clocks {alt_cal_av_edge_detect_clk}]
    Info (332165): Entity alt_xcvr_resync
        Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}
Info (332104): Reading SDC File: 'pcie_lib/synthesis/submodules/altera_reset_controller.sdc'
Info (332104): Reading SDC File: 'pcie_lib/synthesis/submodules/altera_pcie_sv_hip_ast_pipen1b.sdc'
Warning (332174): Ignored filter at altera_pcie_sv_hip_ast_pipen1b.sdc(22): *stratixv_hssi_gen3_pcie_hip|testinhip[*] could not be matched with a pin
Warning (332049): Ignored set_false_path at altera_pcie_sv_hip_ast_pipen1b.sdc(22): Argument <from> is an empty collection
    Info (332050): set_false_path -from [ get_pins -compatibility {*stratixv_hssi_gen3_pcie_hip|testinhip[*]}]
Warning (332174): Ignored filter at altera_pcie_sv_hip_ast_pipen1b.sdc(23): *stratixv_hssi_gen3_pcie_hip|testin1hip[*] could not be matched with a pin
Warning (332049): Ignored set_false_path at altera_pcie_sv_hip_ast_pipen1b.sdc(23): Argument <from> is an empty collection
    Info (332050): set_false_path -from [ get_pins -compatibility {*stratixv_hssi_gen3_pcie_hip|testin1hip[*]}]
Info (332104): Reading SDC File: 'pcie_lib/synthesis/submodules/altera_pcie_sv_hip_ast_rs_serdes.sdc'
Warning (332174): Ignored filter at altera_pcie_sv_hip_ast_rs_serdes.sdc(22): *sv_xcvr_pipe_native* could not be matched with a register
Warning (332049): Ignored set_false_path at altera_pcie_sv_hip_ast_rs_serdes.sdc(22): Argument <from> is an empty collection
    Info (332050): set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers *altpcie_rs_serdes|*]
Info (332104): Reading SDC File: 'pcie_lib/synthesis/submodules/av_xcvr_reconfig.sdc'
Info (332104): Reading SDC File: 'top_hw.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|refclk} -multiply_by 25 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_tx_pll_inst|pll[0].pll.cmu_pll.tx_pll|clkcdr}
    Info (332110): create_clock -period 0.400 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes}
    Info (332110): create_clock -period 0.400 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes}
    Info (332110): create_clock -period 0.400 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes}
    Info (332110): create_clock -period 0.400 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|clkcdr1t} -divide_by 5 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulseout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|clkcdr1t} -divide_by 5 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|clkcdr1t} -divide_by 10 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulsex6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|cpulse}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|hfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[0]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclkx6up} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[2]}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.cdr_refclk_mux0|refiqclk5} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.cdr_refclk_mux0|clkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.cdr_refclk_mux0|clkout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.cdr_refclk_mux0|refiqclk0} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.cdr_refclk_mux0|clkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.cdr_refclk_mux0|clkout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.cdr_refclk_mux0|refiqclk0} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.cdr_refclk_mux0|clkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.cdr_refclk_mux0|clkout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.cdr_refclk_mux0|refiqclk0} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.cdr_refclk_mux0|clkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.cdr_refclk_mux0|clkout}
    Info (332110): create_clock -period 8.000 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|coreclkout}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_cdr|clk90bdes} -divide_by 10 -multiply_by 2 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser|clk90b}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_cdr|clk90bdes} -divide_by 10 -multiply_by 2 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser|clk90b}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_cdr|clk90bdes} -divide_by 10 -multiply_by 2 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser|clk90b}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_cdr|clk90bdes} -divide_by 10 -multiply_by 2 -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser|clk90b}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk}
    Info (332110): create_generated_clock -source {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs} -duty_cycle 50.00 -name {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk} {top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk}
    Info (332110): set_max_delay -to [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN }] 20.000
    Info (332110): set_min_delay -to [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT }] -10.000
    Info (332110): set_max_delay -to [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN }] 20.000
    Info (332110): set_min_delay -to [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_IN }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[3].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[3].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[2].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[2].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[1].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[1].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] -10.000
    Info (332110): set_max_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] 20.000
    Info (332110): set_min_delay -from [get_ports { top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pld_pcs_interface_rbc:inst_av_hssi_common_pld_pcs_interface|pldnfrzdrv }] -10.000
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at top_hw.sdc(9): altera_reserved_tck could not be matched with a clock
Warning (332174): Ignored filter at top_hw.sdc(9): altera_reserved_tdi could not be matched with a port
Warning (332049): Ignored set_input_delay at top_hw.sdc(9): Argument <targets> is an empty collection
    Info (332050): set_input_delay  -add_delay  -clock [get_clocks {altera_reserved_tck}]  20.000 [get_ports {altera_reserved_tdi}]
Warning (332049): Ignored set_input_delay at top_hw.sdc(9): Argument -clock is an empty collection
Warning (332174): Ignored filter at top_hw.sdc(10): altera_reserved_tms could not be matched with a port
Warning (332049): Ignored set_input_delay at top_hw.sdc(10): Argument <targets> is an empty collection
    Info (332050): set_input_delay  -add_delay  -clock [get_clocks {altera_reserved_tck}]  20.000 [get_ports {altera_reserved_tms}]
Warning (332049): Ignored set_input_delay at top_hw.sdc(10): Argument -clock is an empty collection
Warning (332174): Ignored filter at top_hw.sdc(11): altera_reserved_tdo could not be matched with a port
Warning (332049): Ignored set_output_delay at top_hw.sdc(11): Argument <targets> is an empty collection
    Info (332050): set_output_delay -add_delay  -clock [get_clocks {altera_reserved_tck}]  20.000 [get_ports {altera_reserved_tdo}]
Warning (332049): Ignored set_output_delay at top_hw.sdc(11): Argument -clock is an empty collection
Warning (332049): Ignored set_false_path at top_hw.sdc(25): Argument <from> is an empty collection
    Info (332050): set_false_path -from [get_clocks {altera_reserved_tck}] -to [get_clocks *]
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top|pldclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|g_cavhip.arriav_hd_altpe2_hip_top~BURIED_SYNC_DATA108
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[1].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[1].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[2].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[2].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|txpmaclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pcs:inst_av_pcs|av_pcs_ch:ch[3].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys~BURIED_SYNC_DATA139
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pcs|ch[3].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys  from: txpmalocalclk  to: clkout
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[1].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[2].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_rx_pma|rx_pmas[3].rx_pma.rx_pma_deser  from: clk90b  to: clkdivrxrx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[1].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): Cell: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_pma|av_tx_pma|tx_pma_insts[3].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser  from: lfclk  to: clkdivtx
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst|avmmclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_SYNC_DATA18
    Info (332098): From: top|pcie_256_hip_avmm_0|a5_hip_ast|altpcie_av_hip_128bit_atom|g_pcie_xcvr.av_xcvr_pipe_native_hip|inst_av_xcvr_native|inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst|avmmclk  to: top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[3].av_hssi_avmm_interface_inst~BURIED_SYNC_DATA18
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Warning (308027): (Medium) Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized. Found 1 node(s) related to this rule.
    Warning (308010): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|state.DPRIO_WRITE"
Info (308046): (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 272 node(s) with highest fan-out.
    Info (308011): Node  "reconfig_xcvr_clk~inputCLKENA0"
    Info (308011): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_resync:inst_reconfig_reset_sync|resync_chains[0].sync_r[1]"
    Info (308011): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|basic_address[1]~1"
    Info (308011): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|ifsel_notdone_resync"
    Info (308011): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|basic_reconfig_waitrequest~2"
    Info (308011): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|basic_reconfig_waitrequest~1"
    Info (308011): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|basic_reconfig_waitrequest~0"
    Info (308011): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_dcd:dcd.sc_dcd|alt_xcvr_reconfig_dcd_av:inst_alt_xcvr_reconfig_dcd_av|alt_xcvr_reconfig_dcd_cal_av:inst_alt_xcvr_reconfig_dcd_cal|state_done.STATE_DONE2"
    Info (308011): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_reconfig_dcd:dcd.sc_dcd|alt_xcvr_reconfig_dcd_av:inst_alt_xcvr_reconfig_dcd_av|alt_xcvr_reconfig_dcd_cal_av:inst_alt_xcvr_reconfig_dcd_cal|alt_xcvr_reconfig_dcd_control_av:inst_alt_xcvr_reconfig_dcd_control|ctrl_addr~0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|coreclkout~CLKENA0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcierd_hip_rs:rs_hip|app_rstn~CLKENA0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcierd_hip_rs:rs_hip|app_rstn"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcierd_hip_rs:rs_hip|npor_sync_pld_clk"
    Info (308011): Node  "any_rstn_rr"
    Info (308011): Node  "~GND"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|fifo_transmit~0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|tlp_val"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|tlp_file_num[7]~0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|data_fifo_rdreq"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|hdr_address[52]~0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|tx_side_fifo_rdreq"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_reg[0][4]~0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcie_fifo:tx_side_fifo|fifo_wrreq[0]~1"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_txs:txs_slave|txs_wait_cnt~DUPLICATE"
    Info (308011): Node  "top:top|top_mm_interconnect_3:mm_interconnect_3|top_mm_interconnect_3_cmd_mux:cmd_mux|WideOr1"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|dcm_state[1]"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[127]~1"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|ep_last_data[8]"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rxm:rxm_master|RxFifoRdReq_o~1"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|avmm_burst_cntr[5]~0"
    Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Info (308044): (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out.
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|coreclkout~CLKENA0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcierd_hip_rs:rs_hip|app_rstn~CLKENA0"
    Info (308011): Node  "top:top|altera_reset_controller:rst_controller_001|r_sync_rst"
    Info (308011): Node  "reconfig_xcvr_clk~inputCLKENA0"
    Info (308011): Node  "~GND"
    Info (308011): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|ifsel_notdone_resync"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcierd_hip_rs:rs_hip|app_rstn"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:write_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[0]~0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|dma_control:dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo|fifo_wrreq[0]~0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|rd_pop_desc_state"
    Info (308011): Node  "top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:pcie_256_hip_avmm_0_dma_rd_master_translator|uav_address[4]~1"
    Info (308011): Node  "top:top|alt_xcvr_reconfig:alt_xcvr_reconfig_0|alt_xcvr_resync:inst_reconfig_reset_sync|resync_chains[0].sync_r[1]"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcie_av_hip_ast_hwtcl:a5_hip_ast|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|altpcie_rs_serdes:g_soft_reset.altpcie_rs_serdes|arst_r[2]"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|tx_side_fifo_rdreq"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|RxFifoRdReq_o~3"
    Info (308011): Node  "top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_width_adapter:pcie_256_hip_avmm_0_dma_rd_master_to_pcie_256_hip_avmm_0_rd_dts_slave_cmd_width_adapter|always10~0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|hdr_gen_sm.CONT_FILE"
    Info (308011): Node  "top:top|top_mm_interconnect_1:mm_interconnect_1|top_mm_interconnect_1_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|grant[1]~1"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_rd:read_data_mover|rd_dma_state[3]"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[0]~2"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_reg[0][104]~0"
    Info (308011): Node  "top:top|top_mm_interconnect_1:mm_interconnect_1|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter_13_1|altera_merlin_burst_adapter_full_13_1:altera_merlin_burst_adapter_full.the_ba_13_1|NON_PIPELINED_INPUTS.load_next_cmd"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|WrDmaReadDataValid_reg"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_dma_wr:write_data_mover|desc_fifo_rdreq"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|fifo_transmit~0"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[8]~14"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[2]~5"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[6]~10"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[4]~8"
    Info (308011): Node  "top:top|altpcie_256_hip_avmm_hwtcl:pcie_256_hip_avmm_0|altpcieav_256_app:altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo|fifo_wrreq[3]~6"
    Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Info (308007): Design Assistant information: finished post-fitting analysis of current design -- generated 322 information messages and 1 warning messages
Info: Quartus II 64-Bit Design Assistant was successful. 0 errors, 19 warnings
    Info: Peak virtual memory: 1414 megabytes
    Info: Processing ended: Tue Aug  5 17:48:43 2014
    Info: Elapsed time: 00:00:20
    Info: Total CPU time (on all processors): 00:00:19


