To use a third-party Root Complex BFM: 

1. Generate Gen3x16 AvST example design from QAR archive project. 
   Before doing example design generation, you need to add IP search path to the tcl directory inside QAR. Please refer to Qsys User Guide for detailed information.
   You need to choose Third-party BFM for simulation under Example Design tab. Otherwise, it will generate Intel FPGA default BFM, which will downtrain design to Gen3x8.
   Click Generate HDL under Generate tab menu, and then Generate Testbench System. For more details, please refer to User Guide.

2. Place this extracted Avery BFM reference example zip folder in the same directory with the generated design.
   Get the 3rd party BFM resource and simulator resources ready.
   Avery BFM version requirement--1.8d.h1 or later
   Avery example simulator version requirement--VCS J-2014.12 or later
                                              --ModelSim SE 10.3c or later.

3. Create the 3rd party BFM filelist for VCS simulation or Modelsim_SE simulation.
   Intel FPGA provides an Avery RC BFM example. The filelist examples are vcs/avery_files.f and modelsim/avery_files_ms.f in the zip folder. 
   By default, you should not have to make any changes to these files.   
   
4. Create Gen3x16 AvST example design simulation scripts.  
   Intel FPGA provides an VCS file list example, which is vcs/ep_g3x16_ast_tb.f in the zip folder. You could take use of <work_directory>/ep_g3x16_ast_tb/ep_g3x16_ast_tb/sim/synopsys/vcs/vcs_setup.sh to update vcs/ep_g3x16_ast_tb.f. 
   Many file names are uniquely generated when you create the example design and they must be transferred to the example design file list, so you must add the file names yourself.
   Remember to replace $QUARTUS_INSTALL_DIR and $QSYS_SIMDIR with proper path, refer to our example in vcs/ep_g3x16_ast_tb.f. Also remove the tailing '\' at the end of each line for VCS filelist after copying. 
   As for Modelsim, take use of <work_directory>/ep_g3x16_ast_tb/ep_g3x16_ast_tb/sim/mentor/msim_setup.tcl to update file path in modelsim/msim_setup_avery.tcl in the zip folder.
   When using Modelsim, remember to modify $QUARTUS_INSTALL_DIR, $AVERY_PCIE and $AVERY_PCIE in modelsim/mentor.do.
   
5. Configure 3rd party RC BFM and create a BFM testbench top file. 
   Intel FPGA provides Avery BFM testbench top file as an example. It's apci_top_rc.sv in the zip folder. 
   For further BFM download information, please consult Avery Design (sales@avery-design.com).

6. Change Gen3x16 AvST example design testbench top file.
   For example, <work_directory>/ep_g3x16_ast_tb/ep_g3x16_ast_tb/sim/ep_g3x16_ast_tb.v, to .sv file format. 
   If you use Avery BFM, you should be able to directly use ep_g3x16_ast_tb.sv in zip folder.
   The file format is changed from Verilog to System Verilog to facilitate integration with the Avery BFM.

7. Replace generated 3rd party BFM instance in ep_g3x16_ast_tb.sv to the one you'll use. 
   Refer to our example ep_g3x16_ast_tb.sv in the zip folder. It includes the created Avery BFM testbench top file instead. 
   If you use Avery BFM as the 3rd party BFM, you should be able to directly use ep_g3x16_ast_tb.sv in zip folder.
   
8. Use the following example simulation scripts inside the zip folder to compile and run testcase.
   VCS     --vcstest.sh, command is sh vcstest.sh
   Modelsim--mentor.do, command is vsim -c -do mentor.do
   To dump VCS waveform, add +define+APCI_DUMP_VPD -debug_pp to vcs command before +plusarg_save inside vcstest.sh.
   To dump Modelsim waveform, add +define+APCI_DUMP_VCD or +define+APCI_DUMP_WLF to USER_DEFINED_COMPILE_OPTIONS inside mentor.do.
   
9. This Avery RC BFM example includes bus enumeration and simple memory loopback transaction testcases. 
   One memory write is followed by one loopback memory read to the same address.  
   Only Serial mode is supported for this example design.
