ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** readme_patch_9.0_1.41.txt Readme file for Quartus II 9.0 Patch 1.41 Copyright (C) Altera Corporation 2010 All right reserved. Patch created on June 22 2010 Patch SPR#: 346943 SPRs fixed: 345382 //**************************************************************** Problem: Stratix III DDR input registers fail to capture edge-aligned input data correctly while TimeQuest shows positive slack. Solution: The path from corner clock pin to corner PLL has problem. Center PLL is fine. Center clock pin to corner PLL is fine too. The problem only affects Stratix III 3S200, 3S260 and 3S340 devices. This patch updates the Stratix III timing models to fix the problem. Caution - You must either have previously installed the Quartus II software version 9.0 SP1 or must install the Quartus II software version 9.0 SP1 before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.