ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** quartusii-13.0sp1-1.dp5-readme.txt Readme file for Quartus II 13.0 SP1 Patch 1.dp5 Copyright (C) Altera Corporation 2013 All right reserved. Patch created on September 13 2013 Patch Case#: 139016 //**************************************************************** This device patch addresses known software issues for Stratix V, Arria V, and Cyclone V devices in the Quartus II software version 13.0 SP1. Device patches are cumulative. You must either have previously installed the Quartus II 13.0 SP1 software or must install the Quartus II 13.0 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly. ====================================================================== Known issue with patch 1.dp5: ModelSim Altera Edition simulation error ====================================================================== After installing patch 1.dp5, users may see an error message when simulating designs targeting Arria V or Cyclone V devices with external memory interface IP with Modelsim Altera Edition. The error message for VHDL users is Error: Unknown formal identifier "hphy_datapath_ac_delay", and the error message for Verilog users is Error: Unresolved defparam reference to “hphy_datapath_ac_delay”. To eliminate the error, use a different simulator such as Modelsim-SE or VCS. ============================================= The following issues are addressed in 1.dp1: ============================================= --------------------- Issue 1 (case 134991) --------------------- This patch fixes the following Internal Error: Internal Error: Sub-system:ASMCC, File:/quartus/comp/asmcc/asmcc_bitfield.cpp,Line:989 Assembler bitfield error: Found conflicting assignments for CRAM address:address=142 ppm select and cpri mode on native phy for AV & CV HSSI interface (pcs_pma_if and pld_pcs_if) --------------------- Issue 2 (case 135275) --------------------- This patch fixes a bug in 10GBASE-KR Link Training algorithm that mistakenly set post-tap to minimum in certain high error rate conditions. You must regenerate your "1G/10GbE and 10GBASE-KR PHY" IP and recompile your design after installing this patch. --------------------- Issue 3 (case 130633) --------------------- This patch fixes the following Internal Error that happens when NIOS II plugin is used to add nodes into SignalTap II: Internal Error: Sub-system: SDR, File: /quartus/sld/sdr/sdr_tx_trigger_gen2.cpp, Line: 840 node_index < this->m_nodes_vec_cache.size() Stack Trace: 0x7202a: SDR_TX_TRIGGER_GEN2::set_node_alias(char const*, char const*) + 0xb6 (sld_sdr) --------------------- Issue 4 (case 137044) --------------------- This patch enables SOF file generation for these Cyclone V SoC devices: 5CSEA5 5CSEA6 5CSXC5 5CSXC6 5CSTD5 5CSTD6 ============================================= The following issues are addressed in 1.dp5: ============================================= --------------------- Issue 5 (case 154872) --------------------- This patch includes timing model updates to Stratix V and Arria V devices, including devices that had been at "Final" timing status. For more information on how to detect if these changes impact your design, refer to the following Knowledge base solution: www.altera.com/support/kdb/solutions/rd08122013_511.html This patch includes the following timing model changes: *Stratix V and Arria V GZ Timing Model Change: Input Pin to fPLL Reference Clock Path* This patch address a timing miscorrelation in input delay when the fPLL reference clock is fed directly by a dedicated clock input pin in Stratix V and Arria V GZ devices. The issue impacts a design only if a design relies on a specified relationship between the reference clock input pin and fPLL output. *Arria V GX and GT Timing Model Change: Periphery Routing Mux Paths* This patch address timing miscorrelations related to periphery routing multiplexer paths in Arria V GX and GT devices. Without the patch, the I/O pin to core path is missing up to 1 ns delay and the D3 delay chain is not correctly analyzed. In addition, routing between core and the peripheral clock (PCLK) clock buffer is missing ~300ps delay. *Arria V GX and GT TimeQuest Issue: Clock Polarity Timing into MLAB* This patch corrects an issue with the TimeQuest timing analyzer incorrectly analyzing the timing path in Arria V GX and GT devices when there is mixed polarity of clocks into a MLAB memory block, such as a positive-edge write address register feeding a MLAB memory with a negative-edge write clock signal. Without the patch, TimeQuest analyzes this connection as a full cycle transfer when it should be a half cycle. --------------------- Issue 6 (case 145044) --------------------- This patch addresses an issue with timing reporting in the TimeQuest Timing Analyzer that sometimes reported small (a few ps) differences in timing delays between a TimeQuest report run immediately after placement and routing compared to a TimeQuest report run after a database import. This patch ensures TimeQuest uses the correct number for all calculations. --------------------- Issue 7 (case 143133) --------------------- This patch provides an updated clock timing model for Cyclone V 5CGXC3, 5CGXC4, 5CGXC5, 5CEA5 and 5CGTD5 devices, which do not yet have final timing models. --------------------- Issue 8 (case 143061) --------------------- The following Arria V and Cyclone V devices now have final power models in this device patch: Cyclone V 5CEA2, 5CEA4, 5CEA7, 5CEA9, 5CGXC7, 5CGXC9, 5CGTD7, 5CGTD9 Arria V 5AGXB1, 5AGXB3, 5AGXB5, 5AGXB7, 5AGTD3, 5AGTD7 --------------------- Issue 9 (case 154874) --------------------- This patch updates Arria V and Cyclone V transceiver power models to improve the overall quality and accuracy of transceiver power models. This includes fixes as well as model updates to achieve silicon correlation, and updates to ensure consistency between Power Play Power Analyzer (PPPA), PPPA export, and the Early Power Estimator (EPE). --------------------- Issue 10 (case 120566) --------------------- This patch reduces high LAB clock power usage in Arria V and Cyclone V by adding proper tie-offs. To take advantage of this power reduction, recompile your design and rerun power analysis. --------------------- Issue 11 (case 148545) --------------------- This patch updates the Arria V and Cyclone V static power model based on silicon correlation. --------------------- Issue 12 (case 137403 --------------------- This patch fixes a bug that prevented bypassing of I/O differential pad placement rule by setting IO_MAXIMUM_TOGGLE_RATE to 0 in the QSF file. --------------------- Issue 13 (case 140325 --------------------- This patch adds the SFL images for the following Cyclone V SoC devices: 5CSEA5, 5CSEA6, 5CSXC5, 5CSXC6, 5CSTD5, 5CSTD6 --------------------- Issue 14 (case 140417) --------------------- This patch improves the jitter and ppm tolerance for CDR PLL during the data tracking. --------------------- Issue 15 (case 140425) --------------------- This patch provides a fix for Cyclone V PLL DPA output annotation. --------------------- Issue 16 (case 140730) --------------------- This patch updates the av_xcvr_avmm block to prevent a Fitter failure for Arria V production devices. A Fitter failure could occur when Arria V PIPE x8 (PHY IP Core for PCI Express) applies same channels placement location as Arria V PCIe Hard IP x8. --------------------- Issue 17 (case 143712) --------------------- This patch adds compilation support for the following Arria V ES devices: 5ASXMB5E6F31C6ES 5ASXFB5G6F35C6ES --------------------- Issue 18 (case 146576) --------------------- The Vref pin for the HPS DDR on the CycloneV SoC devices is configured as output pin, creating a contention and driving between 4mA to 11mA depending on the board design. This patch configures the VREF pin properly as input pin, fixing the contention. The FPGA Vref pin is not affected. --------------------- Issue 19 (case 146793) --------------------- This patch provides write access to UniPHY calibration settings. --------------------- Issue 20 (case 147683) --------------------- Customer reported Cyclone V E series HMC 400MHz bit failure when operating at VCC 1.07V at high ambient temperature (~70C) due to incorrect cram bit setting in the address and command path between HMC and hard PHY. This effectively reduced the timing margin from 1 full clock cycle to half clock cycle. This patch adds one additional parameter in PHY atom to allow controller on address command datapath to increase the timing margin back to 1 full clock cycle. --------------------- Issue 21 (case 147779) --------------------- This patch updates the PCIe hard reset controller setting to prevent infrequent PCIe link training failure due to partially reset PMA modules. --------------------- Issue 22 (case 148381) --------------------- This patch resolves the unstable TX PLL lock in Arria V PIPE mode for Arria V devices. Arria V PCIe Hard IP is not affected. --------------------- Issue 23 (case 149893) --------------------- Customer reported read capture failures in AV/CV on memory interface designs, as a result of a glitch that can occur in the DQS delay chain, as a result of codeword changes in the DLL when voltage and temperature operating conditions change, when operating at low frequencies (below 450MHz). This causes the rest of the read datapath to fail operating as expected. This patch, depending on the operating frequency of the memory interface, eiterh changes the clock frequency that is used to clock the DLL or bypasses the DQS delay chain completely, both of which remove the possibility of the glitch occurring in the DQS delay chain. --------------------- Issue 24 (case 151048) --------------------- This patch resolves the issue programming files unable to program into hardware for these SOC devices: 5ASXB3 5ASXB5 5ASTD3 5ASTD5. --------------------- Issue 25 (case 152547) --------------------- This patch fixes a problem in which Partial Reconfiguration (PR) of one of the PR regions in the design using the SCRUB mode could have an unintended affect on the behavior of an adjacent PR region. The problem did not exist with the AND-OR mode of PR, and this patch has no implication on the AND-OR mode.