ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** quartusii-13.0sp1-1.dp6-readme.txt (rev 1.1) Readme file for Quartus II 13.0 SP1 Patch 1.dp6 Copyright (C) Altera Corporation 2013 All right reserved. Patch created on December 6 2013 Patch Case#: 139016 //**************************************************************** This device patch addresses known software issues for Stratix V, Arria V, and Cyclone V devices in the Quartus II software version 13.0 SP1. Device patches are cumulative. You must either have previously installed the Quartus II 13.0 SP1 software or must install the Quartus II 13.0 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly. ====================================================================== Known issue with patch 1.dp6: ModelSim Altera Edition simulation error ====================================================================== After installing patch 1.dp6, you may see an error message when simulating designs targeting Arria V or Cyclone V devices with external memory interface IP with Modelsim Altera Edition. The error message for VHDL users is Error: Unknown formal identifier "hphy_datapath_ac_delay", and the error message for Verilog users is Error: Unresolved defparam reference to "hphy_datapath_ac_delay". To eliminate the error, use a different simulator such as Modelsim-SE or VCS. ============================================= The following issues are addressed in 1.dp1: ============================================= --------------------- Issue 1 (case 134991) --------------------- This patch fixes the following Internal Error: Internal Error: Sub-system:ASMCC, File:/quartus/comp/asmcc/asmcc_bitfield.cpp,Line:989 Assembler bitfield error: Found conflicting assignments for CRAM address:address=142 ppm select and cpri mode on native phy for AV & CV HSSI interface (pcs_pma_if and pld_pcs_if) --------------------- Issue 2 (case 135275) --------------------- This patch fixes a bug in 10GBASE-KR Link Training algorithm that incorrectly set post-tap to minimum in certain high error rate conditions. You must regenerate your "1G/10GbE and 10GBASE-KR PHY" IP and recompile your design after installing this patch. --------------------- Issue 3 (case 130633) --------------------- This patch fixes the following Internal Error that happens when NIOS II plugin is used to add nodes into SignalTap II: Internal Error: Sub-system: SDR, File: /quartus/sld/sdr/sdr_tx_trigger_gen2.cpp, Line: 840 node_index < this->m_nodes_vec_cache.size() Stack Trace: 0x7202a: SDR_TX_TRIGGER_GEN2::set_node_alias(char const*, char const*) + 0xb6 (sld_sdr) --------------------- Issue 4 (case 137044) --------------------- This patch enables SOF file generation for these Cyclone V SoC devices: 5CSEA5, 5CSEA6, 5CSXC5, 5CSXC6, 5CSTD5, 5CSTD6 ============================================= The following issues are addressed in 1.dp5: ============================================= --------------------- Issue 5 (case 154872) --------------------- This patch includes timing updates for Stratix V and Arria V devices. The following devices have been updated with "Final" timing model status: 5AGXBA5, 5AGXFA5, 5AGXMA5, 5AGXBA7, 5AGXMA7, 5AGTFC7, and 5AGTMC7 devices There are also timing changes for devices that had "Final" timing model status in 13.0 SP1. For more information on how to detect if the timing model changes impact your design, refer to the following Knowledge Base solution: www.altera.com/support/kdb/solutions/rd08122013_511.html This patch includes the following "Final" timing model changes: *Stratix V and Arria V GZ Timing Model Change: Input Pin to fPLL Reference Clock Path* This patch address a timing miscorrelation in input delay when the fPLL reference clock is fed directly by a dedicated clock input pin in Stratix V and Arria V GZ devices. The issue impacts a design only if a design relies on a specified relationship between the reference clock input pin and fPLL output. *Arria V GX and GT Timing Model Change: Periphery Routing Mux Paths* This patch address timing miscorrelations related to periphery routing multiplexer paths in Arria V GX and GT devices. Without the patch, the I/O pin-to-core path is missing up to 1 ns delay, the D3 delay chain is not correctly analyzed, and routing between the core and the peripheral clock (PCLK) clock buffer is missing ~300ps delay. *Arria V GX and GT TimeQuest Issue: Clock Polarity Timing into MLAB* This patch corrects an issue with the TimeQuest timing analyzer incorrectly analyzing the timing path in Arria V GX and GT devices when there is mixed polarity of clocks into a MLAB memory block, such as a positive-edge write address register feeding a MLAB memory with a negative-edge write clock signal. Without the patch, TimeQuest analyzes this connection as a full cycle transfer when it should be a half cycle. --------------------- Issue 6 (case 145044) --------------------- This patch addresses an issue with timing reporting in the TimeQuest Timing Analyzer that sometimes reported small (a few ps) differences in timing delays between a TimeQuest report run immediately after placement and routing compared to a TimeQuest report run after a database import. This patch ensures TimeQuest uses the correct number for all calculations. --------------------- Issue 7 (case 143133) --------------------- This patch provides an updated clock timing model for Cyclone V 5CGXC3, 5CGXC4, 5CGXC5, 5CEA5 and 5CGTD5 devices, which do not yet have "Final" timing models. --------------------- Issue 8 (case 143061) --------------------- The following Arria V and Cyclone V devices now have "Final" power models in this device patch: Cyclone V 5CEA2, 5CEA4, 5CEA7, 5CEA9, 5CGXC7, 5CGXC9, 5CGTD7, 5CGTD9 Arria V 5AGXB1, 5AGXB3, 5AGXB5, 5AGXB7, 5AGTD3, 5AGTD7 --------------------- Issue 9 (case 154874) --------------------- This patch updates Arria V and Cyclone V transceiver power models to improve the overall quality and accuracy of transceiver power models. This includes fixes as well as model updates to achieve silicon correlation, and updates to ensure consistency between Power Play Power Analyzer (PPPA), PPPA export, and the Early Power Estimator (EPE). --------------------- Issue 10 (case 120566) --------------------- This patch reduces high LAB clock power usage in Arria V and Cyclone V by adding proper tie-offs. To take advantage of this power reduction, recompile your design and rerun power analysis. --------------------- Issue 11 (case 148545) --------------------- This patch updates the Arria V and Cyclone V static power model based on silicon correlation. --------------------- Issue 12 (case 137403) --------------------- This patch fixes a bug that prevented bypassing of I/O differential pad placement rule by setting IO_MAXIMUM_TOGGLE_RATE to 0 in the QSF file. --------------------- Issue 13 (case 140325) --------------------- This patch adds the SFL images for the following Cyclone V SoC devices: 5CSEA5, 5CSEA6, 5CSXC5, 5CSXC6, 5CSTD5, 5CSTD6 --------------------- Issue 14 (case 140417) --------------------- This patch includes an updated simulation model to improve the jitter and PPM tolerance for CDR PLL during data tracking in Stratix V devices. Re-simulate your design if you were experiencing problems with the CDR PLL recovered clock. --------------------- Issue 15 (case 140425) --------------------- This patch provides a fix for Cyclone V PLL DPA output annotation. --------------------- Issue 16 (case 140730) --------------------- This patch updates the av_xcvr_avmm block to prevent a Fitter failure for Arria V production devices. A Fitter failure could occur when Arria V PIPE x8 (PHY IP Core for PCI Express) applies the same channel placement location as the Arria V PCIe Hard IP x8. --------------------- Issue 17 (case 143712) --------------------- This patch adds compilation support for the following Arria V ES devices: 5ASXMB5E6F31C6ES, 5ASXFB5G6F35C6ES --------------------- Issue 18 (case 146576) --------------------- The Vref pin for the HPS DDR on the Cyclone V SoC devices was configured as an output pin, creating contention and driving 4 mA to 11 mA depending on the board design. This patch configures the VREF pin properly as an input pin, fixing the contention. The FPGA Vref pin is not affected. --------------------- Issue 19 (case 146793) --------------------- This patch provides write access to UniPHY calibration settings. --------------------- Issue 20 (case 147683) --------------------- This patch addresses a DDR2/DDR3 read/write failure that can occur in the hard memory controller (HMC) of Cyclone V GX/GT and Arria V GX/GT devices in certain frequency ranges when operating in low Vcc core voltage and extreme hot/cold temperature. To avoid these issues, regenerate your HMC IP with this patch and recompile. For more information, refer to the following Knowledge base solution: http://www.altera.com/support/kdb/solutions/fb153997.html --------------------- Issue 21 (case 147779) --------------------- This patch updates the PCIe hard reset controller setting in Stratix V devices to prevent infrequent PCIe link training failure due to partially reset PMA modules. --------------------- Issue 22 (case 148381) --------------------- This patch resolves an unstable TX PLL lock in Arria V PIPE mode for Arria V devices. Arria V PCIe Hard IP is not affected. --------------------- Issue 23 (case 149893) --------------------- This patch addresses possible read capture failures in Arria V and Cyclone V memory interface designs. A glitch could occur in the DQS delay chain, as a result of codeword changes in the DLL when voltage and temperature operating conditions change, which could cause read capture failure. This issue can occur when operating at the following usage modes: - Arria V: DDR3 and DDR3L SDRAM designs operating below 450 MHz - Arria V: All supported operating frequencies for DDR2/LPDDR2 SDRAM - Cyclone V: All supported operating frequencies for DDR3/DDR3L/DDR2/LPDDR2 SDRAM This patch changes the clock frequency that is used to clock the DLL or bypasses the DQS delay chain completely (depending on the operating frequency of the memory interface), which removes the possibility of the glitch occurring in the DQS delay chain. --------------------- Issue 24 (case 151048) --------------------- This patch resolves an issue that programming files were unable to program into hardware for these SOC devices: 5ASXB3, 5ASXB5, 5ASTD3, 5ASTD5. --------------------- Issue 25 (case 152547) --------------------- This patch fixes a problem in which Partial Reconfiguration (PR) of one PR region in a design using the SCRUB mode could have an unintended affect on the behavior of an adjacent PR region. The problem did not exist with the AND-OR mode of PR, and this patch has no implication on the AND-OR mode. ============================================= The following issues are addressed in 1.dp6: ============================================= --------------------- Issue 26 (case 154787) --------------------- This patch fixes an issue affecting Quad-Serial Configuration (EPCQ) Devices of capacity 256 Mbit or larger, when programmed with JAM, JBC, or SVF programming file formats. --------------------- Issue 27 (case 155481) --------------------- This patch marks the timing models for the following Arria V C7 parts as "Final": 5AGXFA7H4F35C4 5AGXFA7H4F35C5 5AGXFA7H6F35C6 5AGXFA7H4F35I3 5AGXFA7H4F35I5 No other changes are made to these timing models in 1.dp6. --------------------- Issue 28 (case 156312) --------------------- This patch fixes Gen2 link issues for Cyclone V Hard IP for PCI Express IP Core --------------------- Issue 29 (case 157406) --------------------- This patch modifies sequencer initialization-time and reset-time counters to account for frequency as well as GUI settings for Arria V hard memory controller. --------------------- Issue 30 (case 153569) --------------------- This patch fixes Autosweep and EyeQ to set the PMA settings during sweep operations. --------------------- Issue 31 (case 160363) --------------------- This patch addresses possible read capture failures in Stratix V memory interface designs. A glitch can occur in the DQS delay chain, as a result of codeword changes in the DLL when voltage and temperature operating conditions change, which could cause read capture failure. This issue can occur when operating at the following usage modes: - DDR2, DDR3, and DDR3L SDRAM designs with -1/-2 speedgrade FPGA devices operating below 480 MHz - DDR2, DDR3, and DDR3L SDRAM designs with -3/-4 speedgrade FPGA devices operating below 445 MHz This patch changes the clock frequency that is used to clock the DLL or bypasses the DQS delay chain completely (depending on the operating frequency of the memory interface), which removes the possibility of this glitch occurring in the DQS delay chain. --------------------- Issue 32 (case 164099) --------------------- This patch fixes a problem with the register packer where register banks could be accidentally merged within DSP inputs when the input to the fitter came from EDA synthesis tools. --------------------- Issue 33 (case 147814) --------------------- This patch resolves a potential failure in the HPS hard memory controller for DDR3 and DDR2 that can occur at high memory clock speeds. This change affects Cyclone V SoC and Arria V SoC devices. --------------------- Issue 34 (case 167195) --------------------- This patch corrects the behavior of the FPGA-side on-chip termination power-saving circuitry for read operations in DDR devices. In normal circumstances, the FPGA OCT circuitry is set to parallel termination mode for read operations, and series mode for write operations as well as during idle mode. However, an incorrect setting in the power-saving circuitry makes it possible for the OCT circuitry to momentarily switch to series termination in the middle of a read data burst. This only occurs for very specific read data patterns that include BC4 operations. This momentary switch causes an increase in DQ/DQS amplitude measured at the FPGA. This update resolves the incorrect OCT switching behavior. Devices Affected: Arria V, Cyclone V (hard memory controller only) Protocols Affected: DDR2, DDR3 --------------------- Issue 35 (case 153134) --------------------- This patch fixes the following Internal Error: Internal Error: Sub-system: ASMCC, File: /quartus/comp/asmcc/asmcc_const_cache.cpp, Line: 270 Constant Duplication --------------------- Issue 36 (case 168013, 168015, 168017) --------------------- This patch updates the timing models for Cyclone V 5CGXC3, 5CEA5, 5CGXC4, 5CGXC5, and 5CGTD5 parts and the models for these parts are now "Final".