ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** quartusii-13.0sp1-1.dp6c-readme.txt Readme file for Quartus II 13.0 SP1 DP6 Patch 1.dp6c Copyright (C) Altera Corporation 2015 All right reserved. Patch created on June 24 2015 Patch Case#: 301245 //**************************************************************** This patch provides: 1)Cyclone V FPGA/SoC and Arria V FPGA/SoC (excluding GZ devices) DQS delay chain glitch fix 2)Arria V FPGA/SoC Core-to-Periphery (C2P) timing model update 3)Phase shift for UniPHY DDR3 Quarter-Rate for timing closure 4)Phase shift for LVDS Tx for timing closure Caution - You must either have previously installed the Quartus II 13.0 SP1 DP6 software or must install the Quartus II 13.0 SP1 DP6 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.