Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:13.1 (WebPack) - O.40d Target Family: Spartan6
OS Platform: NT Target Device: xc6slx45
Project ID (random number) d557c6c4bb5b4e4fa669c510e7b04848.2C5BE631B69F48AB8C2F24035AF7A13B.5 Target Package: csg324
Registration ID 205970357_0_0_751 Target Speed: -2
Date Generated 2011-08-29T00:11:27 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 32-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz CPU Speed 3066 MHz
OS Name Microsoft Windows 7 , 32-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz CPU Speed 3066 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=2
  • 4-bit subtractor=2
 Comparators=14
  • 4-bit comparator greater=8
  • 6-bit comparator equal=1
  • 6-bit comparator not equal=2
  • 8-bit comparator equal=1
  • 8-bit comparator not equal=2
 Counters=5
  • 1-bit up counter=3
  • 15-bit up counter=2
 FSMs=3 Multiplexers=47
  • 1-bit 2-to-1 multiplexer=21
  • 4-bit 2-to-1 multiplexer=12
  • 8-bit 2-to-1 multiplexer=14
 Registers=206
  • Flip-Flops=206
 		MiscellaneousStatistics
  • AGG_BONDED_IO=63
  • AGG_IO=63
  • AGG_LOCED_IO=47
  • AGG_SLICE=102
  • NUM_BONDED_IOB=63
  • NUM_BSFULL=113
  • NUM_BSLUTONLY=64
  • NUM_BSREGONLY=95
  • NUM_BSUSED=272
  • NUM_BUFG=2
  • NUM_LOCED_IOB=47
  • NUM_LOGIC_O5ANDO6=27
  • NUM_LOGIC_O5ONLY=28
  • NUM_LOGIC_O6ONLY=112
  • NUM_LUT_RT_DRIVES_CARRY4=2
  • NUM_LUT_RT_DRIVES_FLOP=4
  • NUM_LUT_RT_EXO5=4
  • NUM_LUT_RT_EXO6=2
  • NUM_LUT_RT_O6=26
  • NUM_SLICEL=12
  • NUM_SLICEM=1
  • NUM_SLICEX=89
  • NUM_SLICE_CARRY4=8
  • NUM_SLICE_CONTROLSET=26
  • NUM_SLICE_CYINIT=232
  • NUM_SLICE_F7MUX=4
  • NUM_SLICE_FF=224
  • NUM_SLICE_UNUSEDCTRL=17
  • NUM_SRL_O6ONLY=4
  • NUM_UNUSABLE_FF_BELS=68
 		NetStatistics
  • NumNets_Active=398
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=9
  • NumNodesOfType_Active_BOUNCEIN=49
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=8
  • NumNodesOfType_Active_CLKPIN=85
  • NumNodesOfType_Active_CLKPINFEED=12
  • NumNodesOfType_Active_CNTRLPIN=43
  • NumNodesOfType_Active_DOUBLE=338
  • NumNodesOfType_Active_GENERIC=77
  • NumNodesOfType_Active_GLOBAL=66
  • NumNodesOfType_Active_INPUT=12
  • NumNodesOfType_Active_IOBIN2OUT=62
  • NumNodesOfType_Active_IOBOUTPUT=62
  • NumNodesOfType_Active_LUTINPUT=758
  • NumNodesOfType_Active_OUTBOUND=344
  • NumNodesOfType_Active_OUTPUT=335
  • NumNodesOfType_Active_PADINPUT=48
  • NumNodesOfType_Active_PADOUTPUT=15
  • NumNodesOfType_Active_PINBOUNCE=248
  • NumNodesOfType_Active_PINFEED=903
  • NumNodesOfType_Active_QUAD=603
  • NumNodesOfType_Active_REGINPUT=109
  • NumNodesOfType_Active_SINGLE=504
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_HVCCOUT=24
  • NumNodesOfType_Vcc_KVCCOUT=2
  • NumNodesOfType_Vcc_LUTINPUT=61
  • NumNodesOfType_Vcc_PINBOUNCE=2
  • NumNodesOfType_Vcc_PINFEED=61
  • NumNodesOfType_Vcc_REGINPUT=1
 SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=33
  • IOB-IOBS=30
  • SLICEL-SLICEM=7
  • SLICEX-SLICEL=12
  • SLICEX-SLICEM=30
 		SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=8
  • FF_SR=22
  • HARD0=2
  • IOB=63
  • IOB_IMUX=15
  • IOB_INBUF=15
  • IOB_OUTBUF=48
  • LUT5=59
  • LUT6=167
  • LUT_OR_MEM6=4
  • PAD=63
  • REG_SR=202
  • SELMUX2_1=4
  • SLICEL=12
  • SLICEM=1
  • SLICEX=89
 
Configuration Data
FF_SR
  • CK=[CK:22] [CK_INV:0]
  • SRINIT=[SRINIT0:22]
  • SYNC_ATTR=[ASYNC:17] [SYNC:5]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:48]
  • SLEW=[SLOW:48]
  • SUSPEND=[3STATE:48]
 LUT_OR_MEM6
  • CLK=[CLK:4] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:4]
  • RAMMODE=[SRL16:4]
 REG_SR
  • CK=[CK:200] [CK_INV:2]
  • LATCH_OR_FF=[FF:202]
  • SRINIT=[SRINIT0:198] [SRINIT1:4]
  • SYNC_ATTR=[ASYNC:193] [SYNC:9]
 SLICEL
  • CLK=[CLK:4] [CLK_INV:1]
 SLICEM
  • CLK=[CLK:1] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:78] [CLK_INV:1]
 
Pin Data
BUFG
  • I0=2
  • O=2
 BUFG_BUFG
  • I0=2
  • O=2
 CARRY4
  • CIN=6
  • CO3=6
  • CYINIT=2
  • DI0=8
  • DI1=8
  • DI2=6
  • DI3=6
  • O0=8
  • O1=8
  • O2=8
  • O3=6
  • S0=8
  • S1=8
  • S2=8
  • S3=6
 FF_SR
  • CE=6
  • CK=22
  • D=22
  • Q=22
  • SR=7
 HARD0
  • 0=2
 IOB
  • I=15
  • O=48
  • PAD=63
 IOB_IMUX
  • I=15
  • OUT=15
 IOB_INBUF
  • OUT=15
  • PAD=15
 IOB_OUTBUF
  • IN=48
  • OUT=48
 LUT5
  • A1=16
  • A2=18
  • A3=22
  • A4=25
  • A5=26
  • O5=59
 LUT6
  • A1=63
  • A2=123
  • A3=127
  • A4=134
  • A5=165
  • A6=167
  • O6=167
 LUT_OR_MEM6
  • A1=4
  • A2=4
  • A3=4
  • A4=4
  • A5=4
  • A6=4
  • CLK=4
  • DI2=4
  • O6=4
  • WE=4
 PAD
  • PAD=63
 REG_SR
  • CE=106
  • CK=202
  • D=202
  • Q=202
  • SR=12
 SELMUX2_1
  • 0=4
  • 1=4
  • OUT=4
  • S0=4
 SLICEL
  • A=1
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • A5=9
  • A6=9
  • AMUX=8
  • AQ=2
  • AX=1
  • B=1
  • B1=1
  • B2=1
  • B3=1
  • B4=1
  • B5=9
  • B6=9
  • BMUX=8
  • BQ=2
  • BX=2
  • C1=1
  • C2=4
  • C3=4
  • C4=4
  • C5=10
  • C6=12
  • CIN=6
  • CLK=5
  • CMUX=9
  • COUT=6
  • CQ=4
  • CX=5
  • D1=3
  • D2=3
  • D3=4
  • D4=4
  • D5=10
  • D6=10
  • DMUX=6
  • DQ=2
  • DX=2
 SLICEM
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • AI=1
  • AQ=1
  • B1=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • BI=1
  • BQ=1
  • C1=1
  • C2=1
  • C3=1
  • C4=1
  • C5=1
  • C6=1
  • CE=1
  • CI=1
  • CLK=1
  • CQ=1
  • D1=1
  • D2=1
  • D3=1
  • D4=1
  • D5=1
  • D6=1
  • DI=1
  • DQ=1
 SLICEX
  • A=12
  • A1=25
  • A2=38
  • A3=38
  • A4=42
  • A5=44
  • A6=43
  • AMUX=10
  • AQ=64
  • AX=30
  • B=10
  • B1=15
  • B2=27
  • B3=28
  • B4=28
  • B5=29
  • B6=28
  • BMUX=5
  • BQ=43
  • BX=24
  • C=9
  • C1=14
  • C2=25
  • C3=25
  • C4=25
  • C5=26
  • C6=25
  • CE=34
  • CLK=79
  • CMUX=6
  • CQ=38
  • CX=20
  • D=15
  • D1=16
  • D2=30
  • D3=30
  • D4=32
  • D5=34
  • D6=31
  • DMUX=10
  • DQ=43
  • DX=26
  • SR=9
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd
  • map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd
  • map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -ar Structure -tm <design> -w -dir netgen/synthesis -ofmt vhdl -sim <fname>.ngc <fname>.vhd
  • netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -ar Structure -tm <design> -w -dir netgen/synthesis -ofmt vhdl -sim <fname>.ngc <fname>.vhd
  • netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd
  • netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -ar Structure -tm <design> -w -dir netgen/synthesis -ofmt vhdl -sim <fname>.ngc <fname>.vhd
  • netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd
  • netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
XSLTProcess 1 1 0 0 0 0 0
_impact 3 3 0 0 0 0 0
bitgen 184 184 0 0 0 0 0
compxlib 2 2 0 0 0 0 0
cpldfit 1 1 0 0 0 0 0
cse_server 1 1 0 0 0 0 0
hprep6 1 1 0 0 0 0 0
ibiswriter 1 1 0 0 0 0 0
map 515 499 0 0 0 0 0
netgen 504 496 0 0 0 0 0
ngc2edif 10 10 0 0 0 0 0
ngdbuild 561 561 0 0 0 0 0
par 531 473 14 0 0 0 0
taengine 1 1 0 0 0 0 0
trce 500 500 0 0 0 0 0
tsim 1 1 0 0 0 0 0
xpwr 2 2 0 0 0 0 0
xst 878 873 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ise_c_fpga_design_flow_overview.htm ( 1 ) /doc/usenglish/isehelp/ise_c_overview.htm ( 1 )
/doc/usenglish/isehelp/ise_c_simulation_test_bench.htm ( 1 ) /doc/usenglish/isehelp/ise_c_using_the_design_views.htm ( 1 )
/doc/usenglish/isehelp/ise_c_working_with_vhdl_libraries.htm ( 1 ) /doc/usenglish/isehelp/ise_p_using_smartguide.htm ( 1 )
/doc/usenglish/isehelp/ism_r_p_printing.htm ( 1 ) /doc/usenglish/isehelp/pce_db_period-dialog.htm ( 1 )
/doc/usenglish/isehelp/pn_c_using_console_error_warning_tabs.htm ( 1 ) /doc/usenglish/isehelp/pn_db_adding_source_files.htm ( 1 )
/doc/usenglish/isehelp/pn_db_nsw_summary.htm ( 1 ) /doc/usenglish/isehelp/pn_p_changing_source_properties.htm ( 1 )
/doc/usenglish/isehelp/pn_r_library_tab.htm ( 1 ) /doc/usenglish/isehelp/pp_p_process_generate_post_translate_simulation_model.htm ( 1 )
 
Project Statistics
PROPEXT_MapGlobalOptimization_spartan6=Area PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_MapLUTCombining_spartan6=Area PROP_ProjectDescription=Testbed for the spi master/slave cores for continuous transmission mode
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/testbench
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthExtractRAM=false
PROP_SynthExtractROM=false PROP_SynthFsmEncode=Gray
PROP_SynthOptEffort_spartan6=High PROP_SynthShiftRegExtract=false
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserBrowsedStrategyFiles=C:/Xilinx/13.1/ISE_DS/ISE/data/default.xds
PROP_UserConstraintEditorPreference=Constraints Editor PROP_VHDLSourceAnalysisStandard=VHDL-200X
PROP_intProjectCreationTimestamp=2011-07-07T09:55:20 PROP_intWbtProjectID=2C5BE631B69F48AB8C2F24035AF7A13B
PROP_intWbtProjectIteration=5 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.testbench
PROP_selectedSimRootSourceNode_par=work.testbench PROP_selectedSimRootSourceNode_translate=work.testbench
PROP_selectedSimSourceNode=Inst_spi_master_atlys_top PROP_xilxBitgStart_Clk_DriveDone=true
PROP_xilxMapReportDetail=true PROP_xstLUTCombining_spartan6=Area
PROP_AutoTop=false PROP_DevFamily=Spartan6
PROP_ISimSimulationRun_behav_tb=false PROP_ISimSimulationRun_translate_tb=false
PROP_MapExtraEffort_spartan6=Normal PROP_xilxMapEnableMultiThreading=2
PROPEXT_xilxPARextraEffortLevel_spartan6=Normal PROP_DevDevice=xc6slx45
PROP_DevFamilyPMName=spartan6 PROP_ISimSimulationRunTime_behav_tb=30000 ns
PROP_ISimSimulationRunTime_par_tb=12000 ns PROP_ISimSimulationRunTime_translate_tb=12 us
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_parEnableMultiThreading_spartan6=4 PROP_DevSpeed=-2
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=5
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=97 NGDBUILD_NUM_FDC=8
NGDBUILD_NUM_FDE=111 NGDBUILD_NUM_FDP_1=1 NGDBUILD_NUM_FDR=10 NGDBUILD_NUM_FDRE=4
NGDBUILD_NUM_FD_1=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=14 NGDBUILD_NUM_INV=4
NGDBUILD_NUM_LUT1=28 NGDBUILD_NUM_LUT2=3 NGDBUILD_NUM_LUT3=26 NGDBUILD_NUM_LUT4=17
NGDBUILD_NUM_LUT5=62 NGDBUILD_NUM_LUT6=55 NGDBUILD_NUM_MUXCY=28 NGDBUILD_NUM_MUXF7=4
NGDBUILD_NUM_OBUF=48 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=30
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=97 NGDBUILD_NUM_FDC=8 NGDBUILD_NUM_FDE=111
NGDBUILD_NUM_FDP_1=1 NGDBUILD_NUM_FDR=10 NGDBUILD_NUM_FDRE=4 NGDBUILD_NUM_FD_1=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=14 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=4
NGDBUILD_NUM_LUT1=28 NGDBUILD_NUM_LUT2=3 NGDBUILD_NUM_LUT3=26 NGDBUILD_NUM_LUT4=17
NGDBUILD_NUM_LUT5=62 NGDBUILD_NUM_LUT6=55 NGDBUILD_NUM_MUXCY=28 NGDBUILD_NUM_MUXF7=4
NGDBUILD_NUM_OBUF=48 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=30
 
ISim Statistics
Xilinx HDL Libraries Used=simprim
Fuse Resource Usage=2183 ms, 136068 KB
Total Signals=10373
Total Nets=7082
Total Blocks=2081
Total Processes=6468
Total Simulation Time=21100 ns
Simulation Resource Usage=4.55523 sec, 480030 KB
Simulation Mode=gui
Hardware CoSim=0