spi_master_atlys_top Project Status (08/28/2011 - 23:35:14)
Project File: spi_ms_atlys.xise Parser Errors: No Errors
Module Name: spi_master_atlys_top Implementation State: Synthesized
Target Device: xc6slx45-2csg324
  • Errors:
 No Errors
Product Version:ISE 13.1
  • Warnings:
 28 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 218 54576 0%
Number of Slice LUTs 166 27288 0%
Number of fully used LUT-FF pairs 112 272 41%
Number of bonded IOBs 63 218 28%
Number of BUFG/BUFGCTRLs 2 16 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun Aug 28 23:35:13 2011028 Warnings (0 new)24 Infos (0 new)
Translation ReportOut of DateSun Aug 28 23:23:42 2011000
Map ReportOut of DateSun Aug 28 23:24:01 20110013 Infos (0 new)
Place and Route ReportOut of DateSun Aug 28 23:24:13 201101 Warning (0 new)4 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportOut of DateSun Aug 28 23:24:19 2011003 Infos (0 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSun Aug 28 23:30:20 2011
Post-Synthesis Simulation Model ReportOut of DateSun Aug 28 23:19:42 2011
Post-Translate Simulation Model ReportOut of DateSun Aug 28 23:19:45 2011
Post-Map Simulation Model ReportOut of DateSun Aug 28 23:20:15 2011
Physical Synthesis ReportOut of DateSun Aug 28 23:24:01 2011
Post-Place and Route Simulation Model ReportOut of DateSun Aug 28 23:24:26 2011
WebTalk ReportOut of DateWed Aug 10 23:31:06 2011

Date Generated: 08/28/2011 - 23:44:54