| Environment Settings | ||||
| Environment Variable | xst | ngdbuild | map | par |
| PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
| Path | C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt; C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt; C:\Xilinx\13.1\ISE_DS\PlanAhead\bin; C:\Xilinx\13.1\ISE_DS\ISE\bin\nt; C:\Xilinx\13.1\ISE_DS\ISE\lib\nt; C:\Xilinx\13.1\ISE_DS\EDK\bin\nt; C:\Xilinx\13.1\ISE_DS\EDK\lib\nt; C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\13.1\ISE_DS\common\bin\nt; C:\Xilinx\13.1\ISE_DS\common\lib\nt; C:\Windows; C:\csvn\bin\; C:\csvn\Python25\; C:\Program Files\Common Files\Microsoft Shared\Windows Live; C:\Xilinx\11.1\PlanAhead\bin; C:\Xilinx\11.1\common\bin\nt; C:\Xilinx\11.1\ISE\bin\nt; C:\Xilinx\11.1\ISE\lib\nt; C:\Windows\system32; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Flash Magic; C:\Cadence\Orcad_9.2.3\tools\Capture; C:\Cadence\Orcad_9.2.3\tools\bin; C:\Cadence\Orcad_9.2.3\tools\jre\bin; C:\Cadence\Orcad_9.2.3\tools\fet\bin; C:\Cadence\Orcad_9.2.3\tools\specctra\bin; C:\Program Files\Altium Designer Winter 09\System; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\Program Files\Windows Live\Shared; C:\Program Files\QuickTime\QTSystem\; C:\Program Files\TortoiseSVN\bin; C:\Program Files\IDM Computer Solutions\UltraEdit\ |
C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt; C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt; C:\Xilinx\13.1\ISE_DS\PlanAhead\bin; C:\Xilinx\13.1\ISE_DS\ISE\bin\nt; C:\Xilinx\13.1\ISE_DS\ISE\lib\nt; C:\Xilinx\13.1\ISE_DS\EDK\bin\nt; C:\Xilinx\13.1\ISE_DS\EDK\lib\nt; C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\13.1\ISE_DS\common\bin\nt; C:\Xilinx\13.1\ISE_DS\common\lib\nt; C:\Windows; C:\csvn\bin\; C:\csvn\Python25\; C:\Program Files\Common Files\Microsoft Shared\Windows Live; C:\Xilinx\11.1\PlanAhead\bin; C:\Xilinx\11.1\common\bin\nt; C:\Xilinx\11.1\ISE\bin\nt; C:\Xilinx\11.1\ISE\lib\nt; C:\Windows\system32; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Flash Magic; C:\Cadence\Orcad_9.2.3\tools\Capture; C:\Cadence\Orcad_9.2.3\tools\bin; C:\Cadence\Orcad_9.2.3\tools\jre\bin; C:\Cadence\Orcad_9.2.3\tools\fet\bin; C:\Cadence\Orcad_9.2.3\tools\specctra\bin; C:\Program Files\Altium Designer Winter 09\System; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\Program Files\Windows Live\Shared; C:\Program Files\QuickTime\QTSystem\; C:\Program Files\TortoiseSVN\bin; C:\Program Files\IDM Computer Solutions\UltraEdit\ |
C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt; C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt; C:\Xilinx\13.1\ISE_DS\PlanAhead\bin; C:\Xilinx\13.1\ISE_DS\ISE\bin\nt; C:\Xilinx\13.1\ISE_DS\ISE\lib\nt; C:\Xilinx\13.1\ISE_DS\EDK\bin\nt; C:\Xilinx\13.1\ISE_DS\EDK\lib\nt; C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\13.1\ISE_DS\common\bin\nt; C:\Xilinx\13.1\ISE_DS\common\lib\nt; C:\Windows; C:\csvn\bin\; C:\csvn\Python25\; C:\Program Files\Common Files\Microsoft Shared\Windows Live; C:\Xilinx\11.1\PlanAhead\bin; C:\Xilinx\11.1\common\bin\nt; C:\Xilinx\11.1\ISE\bin\nt; C:\Xilinx\11.1\ISE\lib\nt; C:\Windows\system32; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Flash Magic; C:\Cadence\Orcad_9.2.3\tools\Capture; C:\Cadence\Orcad_9.2.3\tools\bin; C:\Cadence\Orcad_9.2.3\tools\jre\bin; C:\Cadence\Orcad_9.2.3\tools\fet\bin; C:\Cadence\Orcad_9.2.3\tools\specctra\bin; C:\Program Files\Altium Designer Winter 09\System; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\Program Files\Windows Live\Shared; C:\Program Files\QuickTime\QTSystem\; C:\Program Files\TortoiseSVN\bin; C:\Program Files\IDM Computer Solutions\UltraEdit\ |
C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt; C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt; C:\Xilinx\13.1\ISE_DS\PlanAhead\bin; C:\Xilinx\13.1\ISE_DS\ISE\bin\nt; C:\Xilinx\13.1\ISE_DS\ISE\lib\nt; C:\Xilinx\13.1\ISE_DS\EDK\bin\nt; C:\Xilinx\13.1\ISE_DS\EDK\lib\nt; C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\13.1\ISE_DS\common\bin\nt; C:\Xilinx\13.1\ISE_DS\common\lib\nt; C:\Windows; C:\csvn\bin\; C:\csvn\Python25\; C:\Program Files\Common Files\Microsoft Shared\Windows Live; C:\Xilinx\11.1\PlanAhead\bin; C:\Xilinx\11.1\common\bin\nt; C:\Xilinx\11.1\ISE\bin\nt; C:\Xilinx\11.1\ISE\lib\nt; C:\Windows\system32; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Flash Magic; C:\Cadence\Orcad_9.2.3\tools\Capture; C:\Cadence\Orcad_9.2.3\tools\bin; C:\Cadence\Orcad_9.2.3\tools\jre\bin; C:\Cadence\Orcad_9.2.3\tools\fet\bin; C:\Cadence\Orcad_9.2.3\tools\specctra\bin; C:\Program Files\Altium Designer Winter 09\System; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\Program Files\Windows Live\Shared; C:\Program Files\QuickTime\QTSystem\; C:\Program Files\TortoiseSVN\bin; C:\Program Files\IDM Computer Solutions\UltraEdit\ |
| XILINX | C:\Xilinx\13.1\ISE_DS\ISE\ | C:\Xilinx\13.1\ISE_DS\ISE\ | C:\Xilinx\13.1\ISE_DS\ISE\ | C:\Xilinx\13.1\ISE_DS\ISE\ |
| XILINX_DSP | C:\Xilinx\13.1\ISE_DS\ISE | C:\Xilinx\13.1\ISE_DS\ISE | C:\Xilinx\13.1\ISE_DS\ISE | C:\Xilinx\13.1\ISE_DS\ISE |
| XILINX_EDK | C:\Xilinx\13.1\ISE_DS\EDK | C:\Xilinx\13.1\ISE_DS\EDK | C:\Xilinx\13.1\ISE_DS\EDK | C:\Xilinx\13.1\ISE_DS\EDK |
| XILINX_PLANAHEAD | C:\Xilinx\13.1\ISE_DS\PlanAhead | C:\Xilinx\13.1\ISE_DS\PlanAhead | C:\Xilinx\13.1\ISE_DS\PlanAhead | C:\Xilinx\13.1\ISE_DS\PlanAhead |
| Synthesis Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ifn | spi_master_atlys_top.prj | ||
| -ifmt | mixed | Mixed | |
| -ofn | spi_master_atlys_top | ||
| -ofmt | NGC | NGC | |
| -p | xc6slx45-2-csg324 | ||
| -top | spi_master_atlys_top | ||
| -opt_mode | Optimization Goal | Speed | Speed |
| -opt_level | Optimization Effort | 2 | 1 |
| -power | Power Reduction | NO | No |
| -iuc | Use synthesis Constraints File | NO | No |
| -keep_hierarchy | Keep Hierarchy | No | No |
| -netlist_hierarchy | Netlist Hierarchy | As_Optimized | As_Optimized |
| -rtlview | Generate RTL Schematic | Yes | No |
| -glob_opt | Global Optimization Goal | AllClockNets | AllClockNets |
| -read_cores | Read Cores | YES | Yes |
| -write_timing_constraints | Write Timing Constraints | NO | No |
| -cross_clock_analysis | Cross Clock Analysis | NO | No |
| -bus_delimiter | Bus Delimiter | <> | <> |
| -slice_utilization_ratio | Slice Utilization Ratio | 100 | 100 |
| -bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100 |
| -dsp_utilization_ratio | DSP Utilization Ratio | 100 | 100 |
| -reduce_control_sets | Auto | Auto | |
| -fsm_extract | YES | Yes | |
| -fsm_encoding | Gray | Auto | |
| -safe_implementation | No | No | |
| -fsm_style | LUT | LUT | |
| -ram_extract | No | Yes | |
| -rom_extract | No | Yes | |
| -shreg_extract | NO | Yes | |
| -auto_bram_packing | NO | No | |
| -resource_sharing | YES | Yes | |
| -async_to_sync | NO | No | |
| -use_dsp48 | Auto | Auto | |
| -iobuf | YES | Yes | |
| -max_fanout | 100000 | 100000 | |
| -bufg | 16 | 16 | |
| -register_duplication | YES | Yes | |
| -register_balancing | No | No | |
| -optimize_primitives | NO | No | |
| -use_clock_enable | Auto | Auto | |
| -use_sync_set | Auto | Auto | |
| -use_sync_reset | Auto | Auto | |
| -iob | Auto | Auto | |
| -equivalent_register_removal | YES | Yes | |
| -slice_utilization_ratio_maxmargin | 5 | 0 | |
| Translation Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -intstyle | ise | None | |
| -dd | _ngo | None | |
| -p | xc6slx45-csg324-2 | None | |
| -uc | spi_master_atlys.ucf | None | |
| Map Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -detail | Generate Detailed MAP Report | TRUE | TRUE |
| -ol | Place & Route Effort Level (Overall) | high | high |
| -xe | Placer Extra Effort Map | NORMAL | |
| -xt | Extra Cost Tables | 0 | 0 |
| -global_opt | Global Optimization map | TRUE | FALSE |
| -ir | Use RLOC Constraints | OFF | OFF |
| -mt | Enable Multi-Threading | 2 | 0 |
| -t | Starting Placer Cost Table (1-100) Map | 1 | 0 |
| -r | Register Ordering | 4 | 4 |
| -equivalent_register_removal | Equivalent Register Removal | TRUE | TRUE |
| -intstyle | ise | None | |
| -lc | LUT Combining | area | off |
| -o | spi_master_atlys_top_map.ncd | None | |
| -w | true | false | |
| -pr | Pack I/O Registers/Latches into IOBs | off | off |
| -p | xc6slx45-csg324-2 | None | |
| Place and Route Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -xe | n | None | |
| -intstyle | ise | ||
| -mt | Enable Multi-Threading | 4 | off |
| -ol | Place & Route Effort Level (Overall) | high | std |
| -w | true | false | |
| Operating System Information | ||||
| Operating System Information | xst | ngdbuild | map | par |
| CPU Architecture/Speed | Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz | Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz | Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz | Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz |
| Host | Develop-W7 | Develop-W7 | Develop-W7 | Develop-W7 |
| OS Name | Microsoft Windows 7 , 32-bit | Microsoft Windows 7 , 32-bit | Microsoft Windows 7 , 32-bit | Microsoft Windows 7 , 32-bit |
| OS Release | Service Pack 1 (build 7601) | Service Pack 1 (build 7601) | Service Pack 1 (build 7601) | Service Pack 1 (build 7601) |