ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** quartusii-12.1sp1-1.dp7-readme.txt Readme file for Quartus II 12.1 SP1 Patch 1.dp7 Copyright (C) Altera Corporation 2013 All rights reserved. Patch created on May 10 2013 Patch Case#: 100654 //**************************************************************** This patch addresses known software issues for Stratix V, Arria V, and Cyclone V devices in the Quartus II software version 12.1 SP1. You must either have previously installed the Quartus II 12.1 SP1 software or must install the Quartus II 12.1 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly. The device patches are cumulative. ============================================= The following issues are addressed in 1.dp1: ============================================= -------------------- Issue 1 (case 89010) -------------------- This patch fixes locking issues during video standard switching in SDI IP cores that target Cyclone V devices. This patch also fixes an error in the Quartus II software that occurs during compilation of a Tx-only SDI core. -------------------- Issue 2 (case 93848) -------------------- This patch fixes an incorrectly labeled pin name for Cyclone V SoC and Arria V SoC devices. The affected pin was named VCC_HPS. It has been renamed VCCRSTCLK_HPS. -------------------- Issue 3 (case 93932) -------------------- This patch enables pseudo differential I/O standards for Arria V 5AGXFA3 side I/O banks such as Bank 5A and Bank 6A. Pseudo differential I/O standards include Differential SSTL, Differential HSUL, Differential HSTL, LVDS 1R/3R, RSDS 1R/3R, and MINI LVDS 1R/3R. Note: True differential I/O standards such as LVDS, MINI LVDS and RSDS are not supported. -------------------- Issue 4 (case 94484) -------------------- This patch fixes the following internal error in the Quartus II software during partition merging when compiling a design that imports a previously exported compilation database: Internal Error: Sub-system: AMERGE, File: /quartus/atm/amerge/amerge_merger_op.cpp, Line: 2357 gid != DEV_ILLEGAL_GLOBAL_ID Stack Trace: 0x15841: amerge_mini_merge + 0x110f1 (atm_amerge) 0x1cfaa: amerge_mini_merge + 0x1885a (atm_amerge) -------------------- Issue 5 (case 96329) -------------------- In Cyclone V, only dedicated REFCLK pins are counted as available resources and it does not include "RX pins as REFCLK". Customer design, using an RX pin as a REFCLK (for additional REFCLKs), will fail during Fitter when the number of REFCLKs (in design) exceed the number of dedicated REFCLK pins in the device. This patch fixes this problem. -------------------- Issue 6 (case 98380) -------------------- This patch fixes the following error in the Quartus II software during compilation: Internal Error: Sub-system: CUT, File: /quartus/db/cut/cut_stratixv_pll_merge_legality.cpp, Line: 435 Illegal PLL Atom Type -------------------- Issue 7 (case 99331) -------------------- If you reprogram a Stratix V production device with PCIe x1 HIP multiple times, occasionally LTSSM can be stuck in DETECT.QUIET state. In failing cases, the parallel clock from the transceiver (PCLK) becomes nonresponsive. This patch fixes the problem. You must recompile your design after installing this patch. -------------------- Issue 8 (case 99557) -------------------- The ALTLVDS_RX megafunction simulation model does not phase shift the latching clock for the incoming serial data according to the clock-data relationship you have specified in the GUI. The megafunction configures itself with a legacy "inclock_data_alignment" parameter that is not ignored when a legal "inclock_phase_shift" parameter exists. This patch reverses this, so that RTL simulation matches what is seen in hardware. -------------------- Issue 9 (case 99706) -------------------- This patch fixes the rate match FIFO issue in Stratix V Native PHY IP for Standard PCS Basic protocol mode. Rate match FIFO does not work properly in Custom Single Width (Standard PCS Basic protocol Single width) and Custom Double Width (Standard PCS Basic protocol Double width) modes using Native PHY IP. Rate Match FIFO full or empty flags cyclically go high, and received data is corrupted. If there is a ppm difference between the write clock and the read clock, SKIP deletion and insertion do not occur. The one-out-of-two bits for FIFO status are missing from the rx_rmfifostatus signal when simplified data interface is enabled. You must regenerate the Native PHY IP after installing this patch. ---------------------- Issue 10 (case 100338) ---------------------- This patch adds the delay values from the core I/O to the G/Q clkmuxes for the Arria V B3 device. ---------------------- Issue 11 (case 100594) ---------------------- This patch provides an option to override specific termination settings under INI control. Please contact your Altera FAE/AE if you need this support. ---------------------- Issue 12 (case 100723) ---------------------- Support for the Cyclone V Hard LPDDR2 300MHz/333MHz memory interface is incomplete in the Quartus II software v12.1 SP1. This patch adds the correct configuration for the Hard LPDDR2 memory interface. ============================================= The following issues are addressed in 1.dp4: ============================================= ---------------------- Issue 13 (case 94437) ---------------------- This patch corrects the offset calibration values when traffic is present on the RX pin for Stratix V devices. You must regenerate your alt_xcvr_reconfig IP and recompile your design after installing this patch. * For a Qsys-based design you must open your design in Qsys, regenerate the IP, then recompile your design. * For a Megawizard-based design you must regenerate the IP in the Megawizard, then recompile your design. ---------------------- Issue 14 (case 99882) ---------------------- This patch provides the final power models for Arria V GZ and non-GT Stratix V devices. ---------------------- Issue 15 (case 100341) ---------------------- This patch updates the Fitter's timing information to improve hold timing closure for Arria V devices. ---------------------- Issue 16 (case 102326) ---------------------- This patch allows designs to see the association between the DSP enable signal and the input registers and output registers for Arria V, Cyclone V, and Stratix V devices. This feature is under INI control. Please contact your Altera FAE/AE if you need this support. ---------------------- Issue 17 (case 98417) ---------------------- This patch updates the PLL simulation models for Arria V, Cyclone V, and Stratix V devices. The patch applies to PLLs set in modes "reconfigurable", "dynamic phase shift", or "Enable physical output clock parameters". It adds support for DSM order settings in fractional mode. It also fixes the issue of no VCO toggling when M counters are set to bypass. ---------------------- Issue 18 (case 102722) ---------------------- The PMA TX channel slew rate 4 (30ps) is now available for data rate between 1G-3G for Stratix V devices. If you do not specify the slew rate explicitly, 30ps is used as the default slew rate (previously 50ps). ---------------------- Issue 19 (case 100339) ---------------------- CDR simulation model might cause disagreement in results between different simulators. This patch eliminates the race condition in the CDR simulation model and ensures results consistency. ============================================= The following issues are addressed in 1.dp5: ============================================= ---------------------- Issue 20 (case 86194) ---------------------- You may encounter locking issues with SDI core (both SDI I and II) when receiving 3G data. The SDI core detects the data incorrectly as HD and results in long locking times. ---------------------- Issue 21 (case 104431) ---------------------- This patch fixes the incorrect Vcm at HSSI reference clock for Arria V devices. ---------------------- Issue 22 (case 104402) ---------------------- When you perform manual assignments to the clkdivtx port and/or clkdivrx port to be promoted to GCLK/RCLK, for production Arria V devices, the Fitter generates "no fit" error messages. The patch allows clkdixtx port and clkdivrx port to be promoted to GCLK/RCLK. ---------------------- Issue 23 (case 104017) ---------------------- This patch fixes the invalid boundary scan chain count and CONF_DONE JTAG sequence issue on the Programmer tool. Invalid boundary scan chain count and CONF_DONE JTAG sequence which causes the Programmer to falsely detect the completion of JTAG programming on Stratix V 5SGSD3, 5SGSD4, and 5SGXA3 devices. ---------------------- Issue 24 (case 104213) ---------------------- This patch allows Arria V and Cyclone V Native PHY to accept 1620 Mbps as RX datarate in 20-bit mode. ============================================= The following issues are addressed in 1.dp6: ============================================= ---------------------- Issue 25 (case 102722) ---------------------- This patch reverts the default slew rate for the PMA TX channel for Stratix V devices to 50ps which was set to 30ps in device patch 1.dp4 (see Issue 18) ---------------------- Issue 26 (case 105557) ---------------------- This patch fixes the following error in the Quartus II Assembler when the CLKDIVRX/CLKDIVTX outputs from the PMA RX/TX are directly routed to GCLK/QCLK: Internal Error: Sub-system: ASMGX, File: /quartus/comp/asmgx/asmgx_arriav.cpp, Line: 493 bus_line != -1 ---------------------- Issue 27 (case 107331) ---------------------- This patch resolves an issue with the Quartus II 12.1 SP1 software where QIP_FILE assignments may be reordered in the QSF when the project is opened in the GUI, or when the "Regenerate IP Components" command is selected from the Project menu. This reordering can lead to errors in compilation, or incorrect timing constraints. The patch also addresses an issue where assignments made in QIP or SIP files may be erroneously written back into the project's QSF file, by both preventing the bug from occuring, and by removing assignments from the QSF if they originated in one of these file types. ============================================= The following issues are addressed in 1.dp7: ============================================= ---------------------- Issue 28 (case 107512) (1.dp6a) ---------------------- This patch updates the PCIe hard reset controller setting to prevent infrequent PCIe link training failure due to partially reset PMA modules. ---------------------- Issue 29 (case 106454) (1.dp6b) ---------------------- This patch provides two updates to the ATX PLL calibration IP Both updates affect designs which require the user to manually re-calibrate the ATX PLL after the initial calibration attempt (when the reconfiguration controller is released from initial reset). Such cases may occur when the user's PLL reference clock is not available until some time after initial calibration. 1) A behavior was observed with ATX PLLs where calibrating one PLL in a quadrant of the device would cause a temporary loss-of-lock in other ATX PLLs in the quadrant. 2) Prior to this update, should the ATX calibration fail for whatever reason (meaning a working setting could not be identified) the calibration IP would leave the ATX PLL in the last attempted setting. The IP was updated to restore the original setting to the ATX PLL before calibration was attempted. ---------------------- Issue 30 (case 103408) (1.dp6f) ---------------------- This patch fixes the issue where the Stratix V device QSF setting XCVR_RX_LINEAR_EQUALIZER_CONTROL does not affect the bit in the programming POF file. ---------------------- Issue 31 (case 110709) (1.dp6g) ---------------------- This patch provides an update to the Stratix V HIP simulation model where the LTSSM transition to L0 state transition time is reduced. ---------------------- Issue 32 (case 114247) (1.dp6k) ---------------------- This patch fixes a bug in the Quartus II software that checks if I/Os are placed in a reserved location when a Hard Memory Controller is used. The bug triggers the following Internal Error: Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen5_postproc.cpp, Line: 266 pad_dev Stack Trace: 0xa68f1: EMIF_GEN5::post_process_legal_placement + 0x931 (periph_emif) 0x5362f: FPP_ENV_IMPL::perform_op + 0x12f (periph_fpp) 0x124b73: FITCC_PERIPHERY_FLOW::do_constraint_propagation + 0x183 (FITTER_FITCC) ---------------------- Issue 33 (case 119740) ---------------------- This patch includes timing model fixes to Stratix V and Arria V devices, including devices that had been at "Final" timing status. This patch includes the following changes to these devices, to match the timing models in the Quartus II software version 13.0: Stratix V clr input of M20K blocks -- The clr input of M20K memories, when driven directly by a global, regional, or periphery clock buffer is not analyzed by the TimeQuest timing analyzer in the Quartus II software version 12.1 SP1 and earlier. Refer to solution http://www.altera.com/support/kdb/solutions/rd02202013_401.html in the Altera Knowledge Base. Stratix V logic and routing delays -- A software error in the Quartus II software version 12.1 SP1 and earlier caused minor timing modeling errors for some logic and routing delays (typically < 20 ps). Refer to solution http://www.altera.com/support/kdb/solutions/rd02202013_401.html in the Altera Knowledge Base. Arria V -- Arria V timing models have changed. Refer to solution http://www.altera.com/support/kdb/solutions/rd04252013_701.html in the Altera Knowledge Base.