ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** quartusii-12.1sp1-1.dp4-readme.txt Readme file for Quartus II 12.1 SP1 Patch 1.dp4 Copyright (C) Altera Corporation 2013 All rights reserved. Patch created on March 1 2013 Patch Case#: 100654 //**************************************************************** This patch addresses known software issues for Stratix V, Arria V, and Cyclone V devices in the Quartus II software version 12.1 SP1. You must either have previously installed the Quartus II 12.1 SP1 software or must install the Quartus II 12.1 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly. The device patches are cumulative. ============================================= The following issues are addressed in 1.dp1: ============================================= -------------------- Issue 1 (case 89010) -------------------- This patch fixes locking issues during video standard switching in SDI IP cores that target Cyclone V devices. This patch also fixes an error in the Quartus II software that occurs during compilation of a Tx-only SDI core. -------------------- Issue 2 (case 93848) -------------------- This patch fixes an incorrectly labeled pin name for Cyclone V SoC and Arria V SoC devices. The affected pin was named VCC_HPS. It has been renamed VCCRSTCLK_HPS. -------------------- Issue 3 (case 93932) -------------------- This patch enables pseudo differential I/O standards for Arria V 5AGXFA3 side I/O banks such as Bank 5A and Bank 6A. Pseudo differential I/O standards include Differential SSTL, Differential HSUL, Differential HSTL, LVDS 1R/3R, RSDS 1R/3R, and MINI LVDS 1R/3R. Note: True differential I/O standards such as LVDS, MINI LVDS and RSDS are not supported. -------------------- Issue 4 (case 94484) -------------------- This patch fixes the following internal error in the Quartus II software during partition merging when compiling a design that imports a previously exported compilation database: Internal Error: Sub-system: AMERGE, File: /quartus/atm/amerge/amerge_merger_op.cpp, Line: 2357 gid != DEV_ILLEGAL_GLOBAL_ID Stack Trace: 0x15841: amerge_mini_merge + 0x110f1 (atm_amerge) 0x1cfaa: amerge_mini_merge + 0x1885a (atm_amerge) -------------------- Issue 5 (case 96329) -------------------- In Cyclone V, REFCLK resource check does not include for "RX pins as REFCLK" while counting resources. Customer designs targeting Cyclone V devices experience Fitter failures when using an RX pin as a refclk for additional REFCLKs. This patch fixes this problem. -------------------- Issue 6 (case 98380) -------------------- This patch fixes the following error in the Quartus II software during compilation: Internal Error: Sub-system: CUT, File: /quartus/db/cut/cut_stratixv_pll_merge_legality.cpp, Line: 435 Illegal PLL Atom Type -------------------- Issue 7 (case 99331) -------------------- If you reprogram a Stratix V production device with PCIe x1 HIP multiple times, occasionally LTSSM can be stuck in DETECT.QUIET state. In failing cases, the parallel clock from the transceiver (PCLK) becomes nonresponsive. This patch fixes the problem. You need to recompile your design after installing this patch. -------------------- Issue 8 (case 99557) -------------------- The ALTLVDS_RX megafunction simulation model does not phase shift the latching clock for the incoming serial data according to the clock-data relationship you have specified in the GUI. The megafunction configures itself with a legacy "inclock_data_alignment" parameter that is not ignored when a legal "inclock_phase_shift" parameter exists. This patch reverses this, so that RTL simulation matches what is seen in hardware. -------------------- Issue 9 (case 99706) -------------------- This patch fixes the rate match FIFO issue in Stratix V Native PHY IP for Standard PCS Basic protocol mode. Rate match FIFO does not work properly in Custom Single Width (Standard PCS Basic protocol Single width) and Custom Double Width (Standard PCS Basic protocol Double width) modes using Native PHY IP. Rate Match FIFO full or empty flags cyclically go high, and received data is corrupted. If there is a ppm difference between the write clock and the read clock, SKIP deletion and insertion do not occur. The one-out-of-two bits for FIFO status are missing from the rx_rmfifostatus signal when simplified data interface is enabled. You need to regenerate the Native PHY IP after installing this patch. ---------------------- Issue 10 (case 100338) ---------------------- This patch adds the delay values from the core I/O to the G/Q clkmuxes for the Arria V B3 device. ---------------------- Issue 11 (case 100594) ---------------------- This patch provides an option to override specific termination settings under INI control. Please contact your Altera FAE/AE if you need this support. ---------------------- Issue 12 (case 100723) ---------------------- Support for the Cyclone V Hard LPDDR2 300MHz/333MHz memory interface is incomplete in the Quartus II software v12.1 SP1. This patch adds the correct configuration for the Hard LPDDR2 memory interface. ============================================= The following issues are addressed in 1.dp4: ============================================= ---------------------- Issue 13 (case 94437) ---------------------- This patch corrects the offset calibration values when traffic is present on the RX pin for Stratix V devices. You need to regenerate your alt_xcvr_reconfig IP and recompile your design after installing this patch. * For a Qsys-based design you need to open your design in Qsys, regenerate the IP, then recompile your design. * For a Megawizard-based design you need to regenerate the IP in the Megawizard, then recompile your design. ---------------------- Issue 14 (case 99882) ---------------------- This patch provides the final power models for Arria V GZ and non-GT Stratix V devices. ---------------------- Issue 15 (case 100341) ---------------------- This patch updates the Fitter's timing information to improve hold timing closure for Arria V devices. ---------------------- Issue 16 (case 102326) ---------------------- This patch allows designs to see the association between the DSP enable signal and the input registers and output registers for Arria V, Cyclone V, and Stratix V devices. This feature is under INI control. Please contact your Altera FAE/AE if you need this support. ---------------------- Issue 17 (case 98417) ---------------------- This patch updates the PLL simulation models for Arria V, Cyclone V, and Stratix V devices. The patch applies to PLLs set in modes "reconfigurable", "dynamic phase shift", or "Enable physical output clock parameters". It adds support for DSM order settings in fractional mode. It also fixes the issue of no VCO toggling when M counters are set to bypass. ---------------------- Issue 18 (case 102722) ---------------------- The PMA TX channel slew rate 4 (30ps) is now available for data rate between 1G-3G for Stratix V devices. If you do not specify the slew rate explicitly, it will be used as default slew rate (previously 50ps). ---------------------- Issue 19 (case 100339) ---------------------- CDR simulation model might cause results disagreement between different simulators. This patch eliminates the race condition in the CDR simulation model and ensures results consistency.